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[X86][BMI1]: X86DAGToDAGISel: select BEXTR from x & ((1 << nbits) + (-1)) pattern
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Authored by lebedev.ri on Sep 21 2018, 2:56 AM.

Details

Summary

Trivial continuation of D52304.
While this pattern is not canonical, we do select it in the BZHI case,
so this should not be any different.

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rL LLVM

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I believe i will have to move BZHI selection from tablegen into here, due to https://reviews.llvm.org/D48768#inline-461084,
else we will have test coverage issues, and code duplication.

Rebased, NFC.

Rebased, NFC.

craig.topper added inline comments.Oct 10 2018, 11:48 PM
lib/Target/X86/X86ISelDAGToDAG.cpp
2674 ↗(On Diff #167779)

I think you can use ISD::isAllOnesConstant

2681 ↗(On Diff #167779)

ISD::isOneConstant

lebedev.ri marked 2 inline comments as done.

Rebased.

RKSimon added inline comments.Oct 22 2018, 4:09 AM
test/CodeGen/X86/extract-bits.ll
85 ↗(On Diff #169160)

Could we not do this?

shll $8, %edx
orl %esi, %edx
bextrl %edx, %edi, %eax

Or are there concerns about overflows etc?

lebedev.ri added inline comments.Oct 22 2018, 4:16 AM
test/CodeGen/X86/extract-bits.ll
85 ↗(On Diff #169160)

That's the idea, there is a TODO in the code about it.
I want to finish with the other 2 patterns before looking into that.

I *think* it should be safe to do, *if* it was lshr, not ashr, since
https://www.felixcloutier.com/x86/BEXTR.html

The destination register is cleared if no bits are extracted.

RKSimon accepted this revision.Oct 22 2018, 4:31 AM

LGTM

This revision is now accepted and ready to land.Oct 22 2018, 4:31 AM

LGTM

Thank you for the review!

This revision was automatically updated to reflect the committed changes.