Add a thread-model knob for lowering atomics on baremetal & single threaded systems

[morisset]

A few inline comments.

I would also suggest tests for atomic loads/stores/fences and not just atomicRMW.

lib/Target/ARM/ARMISelLowering.cpp

752

single threded -> single threaded

757

This repetition of the test for ThreadModel::Single looks unnecessary to me.

Why not test for it first, then put the rest in an else block ?

if (TM.Options>ThreadModel == ThreadModel::Single) {
  setOperationAction(ISD::ATOMIC_FENCE,  MVT::Other, Expand);
else if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
...

As a bonus, it makes the logic simpler, avoiding setting insertFencesForAtomic (which is a no-op in that case I believe, since all atomic operations will have been lowered before).

lib/Target/ARM/ARMTargetMachine.cpp

161

Shouldn't this pass be disabled when the ThreadModel is single? Especially as it runs first, I expect it will turn for example atomicrmw add in a loop of ldrex/strex instead of a simple add instruction (whenever the subtarget does not disable it at least).

[jroelofs]

lib/Target/ARM/ARMISelLowering.cpp

757

That does look cleaner.

lib/Target/ARM/ARMTargetMachine.cpp

161

Oh, good point!

[jroelofs]

Follow up on morisset's comments.

[rengolin]

I wasn't following the atomics discussion, but this patch looks good. If Morisset is happy with your changer, LGTM.

thanks,
--renato

[jroelofs]

I added a couple load, store, and fence tests, and committed this as r216182.

Thanks for the review!

Jon

include/llvm/CodeGen/CommandFlags.h

                       "Relocatable external references, non-relocatable code"),
               clEnumValEnd));
 
+cl::opt<ThreadModel::Model>
+TMModel("thread-model",
+        cl::desc("Choose threading model"),
+        cl::init(ThreadModel::POSIX),
+        cl::values(clEnumValN(ThreadModel::POSIX, "posix",
+                              "POSIX thread model"),
+                   clEnumValN(ThreadModel::Single, "single",
+                              "Single thread model"),
+                   clEnumValEnd));
+
 cl::opt<llvm::CodeModel::Model>
 CMModel("code-model",
         cl::desc("Choose code model"),

   Options.MCOptions = InitMCTargetOptionsFromFlags();
   Options.JTType = JTableType;
 
+  Options.ThreadModel = TMModel;
+
   return Options;
 }
 

include/llvm/Target/TargetOptions.h

     };
   }
 
+  namespace ThreadModel {
+    enum Model {
+      POSIX,  // POSIX Threads
+      Single  // Single Threaded Environment
+    };
+  }
+
   class TargetOptions {
   public:
     TargetOptions()

     /// create for functions that have the jumptable attribute.
     JumpTable::JumpTableType JTType;
 
+    /// ThreadModel - This flag specifies the type of threading model to assume
+    /// for things like atomics
+    ThreadModel::Model ThreadModel;
+
     /// Machine level options.
     MCTargetOptions MCOptions;
   };

lib/Target/ARM/ARMISelLowering.cpp

     setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
 
   // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
-  // the default expansion.
-  if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
+  // the default expansion. If we are targeting a single threaded system,
+  // then set them all for expand so we can lower them later into their
+  // non-atomic form.
+  if (TM.Options.ThreadModel == ThreadModel::Single)
+    setOperationAction(ISD::ATOMIC_FENCE,   MVT::Other, Expand);
+  else if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
     // ATOMIC_FENCE needs custom lowering; the others should have been expanded
     // to ldrex/strex loops already.
     setOperationAction(ISD::ATOMIC_FENCE,     MVT::Other, Custom);

lib/Target/ARM/ARMTargetMachine.cpp

 }
 
 void ARMPassConfig::addIRPasses() {
-  addPass(createAtomicExpandLoadLinkedPass(TM));
+  if (TM->Options.ThreadModel == ThreadModel::Single)
+    addPass(createLowerAtomicPass());
+  else
+    addPass(createAtomicExpandLoadLinkedPass(TM));
 
   // Cmpxchg instructions are often used with a subsequent comparison to
   // determine whether it succeeded. We can exploit existing control-flow in

test/CodeGen/ARM/atomic-op.ll

 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s
 ; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-T1
 ; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-M0
+; RUN: llc < %s -mtriple=armv4t--none-eabi -thread-model single -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-BAREMETAL
 
 define void @func(i32 %argc, i8** %argv) nounwind {
 entry:

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_add_4
   ; CHECK-M0: bl ___sync_fetch_and_add_4
+  ; CHECK-BAREMETAL: add
+  ; CHECK-BAREMETAL-NOT: __sync
   %0 = atomicrmw add i32* %val1, i32 %tmp monotonic
   store i32 %0, i32* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_sub_4
   ; CHECK-M0: bl ___sync_fetch_and_sub_4
+  ; CHECK-BAREMETAL: sub
+  ; CHECK-BAREMETAL-NOT: __sync
   %1 = atomicrmw sub i32* %val2, i32 30 monotonic
   store i32 %1, i32* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_add_4
   ; CHECK-M0: bl ___sync_fetch_and_add_4
+  ; CHECK-BAREMETAL: add
+  ; CHECK-BAREMETAL-NOT: __sync
   %2 = atomicrmw add i32* %val2, i32 1 monotonic
   store i32 %2, i32* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_sub_4
   ; CHECK-M0: bl ___sync_fetch_and_sub_4
+  ; CHECK-BAREMETAL: sub
+  ; CHECK-BAREMETAL-NOT: __sync
   %3 = atomicrmw sub i32* %val2, i32 1 monotonic
   store i32 %3, i32* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_and_4
   ; CHECK-M0: bl ___sync_fetch_and_and_4
+  ; CHECK-BAREMETAL: and
+  ; CHECK-BAREMETAL-NOT: __sync
   %4 = atomicrmw and i32* %andt, i32 4080 monotonic
   store i32 %4, i32* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_or_4
   ; CHECK-M0: bl ___sync_fetch_and_or_4
+  ; CHECK-BAREMETAL: or
+  ; CHECK-BAREMETAL-NOT: __sync
   %5 = atomicrmw or i32* %ort, i32 4080 monotonic
   store i32 %5, i32* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_xor_4
   ; CHECK-M0: bl ___sync_fetch_and_xor_4
+  ; CHECK-BAREMETAL: eor
+  ; CHECK-BAREMETAL-NOT: __sync
   %6 = atomicrmw xor i32* %xort, i32 4080 monotonic
   store i32 %6, i32* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_min_4
   ; CHECK-M0: bl ___sync_fetch_and_min_4
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %7 = atomicrmw min i32* %val2, i32 16 monotonic
   store i32 %7, i32* %old
   %neg = sub i32 0, 1

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_min_4
   ; CHECK-M0: bl ___sync_fetch_and_min_4
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %8 = atomicrmw min i32* %val2, i32 %neg monotonic
   store i32 %8, i32* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_max_4
   ; CHECK-M0: bl ___sync_fetch_and_max_4
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %9 = atomicrmw max i32* %val2, i32 1 monotonic
   store i32 %9, i32* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_max_4
   ; CHECK-M0: bl ___sync_fetch_and_max_4
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %10 = atomicrmw max i32* %val2, i32 0 monotonic
   store i32 %10, i32* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_umin_4
   ; CHECK-M0: bl ___sync_fetch_and_umin_4
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %11 = atomicrmw umin i32* %val2, i32 16 monotonic
   store i32 %11, i32* %old
   %uneg = sub i32 0, 1

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_umin_4
   ; CHECK-M0: bl ___sync_fetch_and_umin_4
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %12 = atomicrmw umin i32* %val2, i32 %uneg monotonic
   store i32 %12, i32* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_umax_4
   ; CHECK-M0: bl ___sync_fetch_and_umax_4
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %13 = atomicrmw umax i32* %val2, i32 1 monotonic
   store i32 %13, i32* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_umax_4
   ; CHECK-M0: bl ___sync_fetch_and_umax_4
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %14 = atomicrmw umax i32* %val2, i32 0 monotonic
   store i32 %14, i32* %old
 

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_umin_2
   ; CHECK-M0: bl ___sync_fetch_and_umin_2
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %0 = atomicrmw umin i16* %val, i16 16 monotonic
   store i16 %0, i16* %old
   %uneg = sub i16 0, 1

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_umin_2
   ; CHECK-M0: bl ___sync_fetch_and_umin_2
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %1 = atomicrmw umin i16* %val, i16 %uneg monotonic
   store i16 %1, i16* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_umax_2
   ; CHECK-M0: bl ___sync_fetch_and_umax_2
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %2 = atomicrmw umax i16* %val, i16 1 monotonic
   store i16 %2, i16* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_umax_2
   ; CHECK-M0: bl ___sync_fetch_and_umax_2
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %3 = atomicrmw umax i16* %val, i16 0 monotonic
   store i16 %3, i16* %old
   ret void

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_umin_1
   ; CHECK-M0: bl ___sync_fetch_and_umin_1
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %0 = atomicrmw umin i8* %val, i8 16 monotonic
   store i8 %0, i8* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_umin_1
   ; CHECK-M0: bl ___sync_fetch_and_umin_1
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %uneg = sub i8 0, 1
   %1 = atomicrmw umin i8* %val, i8 %uneg monotonic
   store i8 %1, i8* %old

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_umax_1
   ; CHECK-M0: bl ___sync_fetch_and_umax_1
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %2 = atomicrmw umax i8* %val, i8 1 monotonic
   store i8 %2, i8* %old
   ; CHECK: ldrex

   ; CHECK: strex
   ; CHECK-T1: blx ___sync_fetch_and_umax_1
   ; CHECK-M0: bl ___sync_fetch_and_umax_1
+  ; CHECK-BAREMETAL: cmp
+  ; CHECK-BAREMETAL-NOT: __sync
   %3 = atomicrmw umax i8* %val, i8 0 monotonic
   store i8 %3, i8* %old
   ret void