[AArch64] Implement execute-only CodeGen Support.

[ivanlozano]

Summary

This implements execute-only support for AArch64 targets, similar to the ARM code generation for execute-only.

[srhines]

This is really cool. I just had one minor suggestion for testing, and will otherwise defer to the ARM64-related folks to accept the patch. The rest looks quite reasonable to me, though.

test/CodeGen/AArch64/execute-only-section.ll

1

Does it make sense to have another test that runs llvm-readobj on an assembled object and verifies that these sections are indeed marked as execute-only?

[srhines]

test/CodeGen/AArch64/execute-only-section.ll

1

And I just realized that the corresponding llvm repository change has exactly that test. Sorry for the noise.

[ivanlozano]

test/CodeGen/AArch64/execute-only-section.ll

1

No problem!

[efriedma]

It looks like this patch does two things:

1. Adds MC layer support for the SHF_ARM_PURECODE flag on AArch64.
2. Adds the AArch64 SHF_ARM_PURECODE flag to all sections containing code if the "execute-only" subtarget feature is enabled.

I guess nothing else is necessary because the AArch64 backend doesn't generate inline constant pools anyway?

What happens if the input IR has a mix of execute-only and non-execute-only functions? Does the output .text section have the SHF_ARM_PURECODE flag?

[ivanlozano]

In D48791#1148658, @efriedma wrote:

What happens if the input IR has a mix of execute-only and non-execute-only functions? Does the output .text section have the SHF_ARM_PURECODE flag?

All sections that go into the final combined .text in a binary need to have the SHF_ARM_PURECODE flag set, otherwise the flag gets removed by the linker. D48795 adds this behavior for AArch64 to LLD.

[efriedma]

No, I meant, what happens if two functions in the same IR module have different execute-only settings?

[ivanlozano]

Passed an IR file to llc with a mix of functions that have the execute-only attribute set and ones that don't to test this. Two .text sections are generated in the object file, one with the SHF_ARM_PURECODE flag set and one without, and functions reside in their respective sections.

[peter.smith]

There is an ABI issue with using an Arm specific flag that isn't defined in AArch64. I've not had a chance to check over the code yet, but will try to do so later today.

tools/llvm-readobj/ELFDumper.cpp

1106

SHF_ARM_PURECODE is defined in the Processor specific part of ELF Section flags (SHF_MASKPROC [1]) it is only defined for Arm (see SHF_NOREAD) [2] and is not currently defined for AArch64. If we use it here we risk the ABI using the same flag for something else and we will have a binary compatibility problem.

In practice I think that it would make sense to define SHF_AARCH64_PURECODE with the same value. I will raise an issue with the AArch64 ABI, it would be good to get at least some indication that this value will be reserved so that we can use it.

[1] Generic ELF Spec http://www.sco.com/developers/gabi/latest/ch4.sheader.html
[2] ELF for the Arm Architecture http://infocenter.arm.com/help/topic/com.arm.doc.ihi0044f/IHI0044F_aaelf.pdf
[3] ELF for the Arm 64-bit Architecture http://infocenter.arm.com/help/topic/com.arm.doc.ihi0056b/IHI0056B_aaelf64.pdf

[peter.smith]

Some early feedback from the AArch64 ABI along the lines of "Do you actually need SHF_AARCH64_PURECODE?" In Arm there has been a long history of using literal pools so it is important to mark code that has been compiled to avoid them as SHF_ARM_PURECODE. In AArch64 the expectation is that code is execute-only unless someone has forced it otherwise. An alternative model is to assume that all executable sections are implicitly execute-only and therefore all that you would need is an option at link time to remove PF_R from a program header that contained only executable sections. In essence we can have a one time declare all executable sections as execute-only at link time. I think that this would be compatible with adding SHF_AARCH64_PURECODE later if there was a code-generation model that made use of literal pools.

[ivanlozano]

This seems reasonable to me. I'll look into putting together an LLD patch that does this. Thanks!

[ivanlozano]

Alternative solution committed: rL338271

lib/MC/MCSectionELF.cpp

void MCSectionELF::PrintSwitchToSection(const MCAsmInfo &MAI, const Triple &T,
 
   // If there are target-specific flags, print them.
   Triple::ArchType Arch = T.getArch();
   if (Arch == Triple::xcore) {
     if (Flags & ELF::XCORE_SHF_CP_SECTION)
       OS << 'c';
     if (Flags & ELF::XCORE_SHF_DP_SECTION)
       OS << 'd';
-  } else if (T.isARM() || T.isThumb()) {
+  } else if (T.isARM() || T.isThumb() || T.isAArch64() ) {
     if (Flags & ELF::SHF_ARM_PURECODE)
       OS << 'y';
   }
 
   OS << '"';
 
   OS << ',';
 

lib/ObjectYAML/ELFYAML.cpp

#define BCase(X) IO.bitSetCase(Value, #X, ELF::X)
   BCase(SHF_STRINGS);
   BCase(SHF_INFO_LINK);
   BCase(SHF_LINK_ORDER);
   BCase(SHF_OS_NONCONFORMING);
   BCase(SHF_GROUP);
   BCase(SHF_TLS);
   BCase(SHF_COMPRESSED);
   switch (Object->Header.Machine) {
+  case ELF::EM_AARCH64:
+    BCase(SHF_ARM_PURECODE);
+    break;
   case ELF::EM_ARM:
     BCase(SHF_ARM_PURECODE);
     break;
   case ELF::EM_HEXAGON:
     BCase(SHF_HEX_GPREL);
     break;
   case ELF::EM_MIPS:
     BCase(SHF_MIPS_NODUPES);

lib/Target/AArch64/AArch64.td

 
 def FeatureReserveX20 : SubtargetFeature<"reserve-x20", "ReserveX20", "true",
                                          "Reserve X20, making it unavailable "
                                          "as a GPR">;
 
 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
                                     "Use alias analysis during codegen">;
 
+def FeatureExecuteOnly
+    : SubtargetFeature<"execute-only", "GenExecuteOnly", "true",
+                       "Enable the generation of execute only code.">;
+
 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
     "true",
     "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
 
 def FeaturePredictableSelectIsExpensive : SubtargetFeature<
     "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
     "Prefer likely predicted branches over selects">;
 

lib/Target/AArch64/AArch64AsmPrinter.cpp

AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
         SM(*this) {}
 
   StringRef getPassName() const override { return "AArch64 Assembly Printer"; }
 
   /// Wrapper for MCInstLowering.lowerOperand() for the
   /// tblgen'erated pseudo lowering.
   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
-    return MCInstLowering.lowerOperand(MO, MCOp);
+    return MCInstLowering.lowerOperand(MO, MCOp, STI);
   }
 
   void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
                      const MachineInstr &MI);
   void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
                        const MachineInstr &MI);
 
   void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI);
case AArch64::TCRETURNri: {
     MCInst TmpInst;
     TmpInst.setOpcode(AArch64::BR);
     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
     EmitToStreamer(*OutStreamer, TmpInst);
     return;
   }
   case AArch64::TCRETURNdi: {
     MCOperand Dest;
-    MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
+    MCInstLowering.lowerOperand(MI->getOperand(0), Dest, STI);
     MCInst TmpInst;
     TmpInst.setOpcode(AArch64::B);
     TmpInst.addOperand(Dest);
     EmitToStreamer(*OutStreamer, TmpInst);
     return;
   }
   case AArch64::TLSDESC_CALLSEQ: {
     /// lower this to:
     ///    adrp  x0, :tlsdesc:var
     ///    ldr   x1, [x0, #:tlsdesc_lo12:var]
     ///    add   x0, x0, #:tlsdesc_lo12:var
     ///    .tlsdesccall var
     ///    blr   x1
     ///    (TPIDR_EL0 offset now in x0)
     const MachineOperand &MO_Sym = MI->getOperand(0);
     MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
     MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
     MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF);
     MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
-    MCInstLowering.lowerOperand(MO_Sym, Sym);
-    MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
-    MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
+    MCInstLowering.lowerOperand(MO_Sym, Sym, STI);
+    MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12, STI);
+    MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc, STI);
 
     MCInst Adrp;
     Adrp.setOpcode(AArch64::ADRP);
     Adrp.addOperand(MCOperand::createReg(AArch64::X0));
     Adrp.addOperand(SymTLSDesc);
     EmitToStreamer(*OutStreamer, Adrp);
 
     MCInst Ldr;

lib/Target/AArch64/AArch64ISelLowering.cpp

case ISD::BR_CC:
     return LowerBR_CC(Op, DAG);
   case ISD::SELECT:
     return LowerSELECT(Op, DAG);
   case ISD::SELECT_CC:
     return LowerSELECT_CC(Op, DAG);
   case ISD::JumpTable:
     return LowerJumpTable(Op, DAG);
   case ISD::ConstantPool:
+    if (Subtarget->genExecuteOnly())
+      llvm_unreachable("execute-only should not generate constant pools");
     return LowerConstantPool(Op, DAG);
   case ISD::BlockAddress:
     return LowerBlockAddress(Op, DAG);
   case ISD::VASTART:
     return LowerVASTART(Op, DAG);
   case ISD::VACOPY:
     return LowerVACOPY(Op, DAG);
   case ISD::VAARG:

lib/Target/AArch64/AArch64InstrInfo.td

def HasFuseAES       : Predicate<"Subtarget->hasFuseAES()">,
                                  "fuse-aes">;
 def HasSVE           : Predicate<"Subtarget->hasSVE()">,
                                  AssemblerPredicate<"FeatureSVE", "sve">;
 def HasRCPC          : Predicate<"Subtarget->hasRCPC()">,
                                  AssemblerPredicate<"FeatureRCPC", "rcpc">;
 
 def IsLE             : Predicate<"Subtarget->isLittleEndian()">;
 def IsBE             : Predicate<"!Subtarget->isLittleEndian()">;
+def GenExecuteOnly   : Predicate<"Subtarget->genExecuteOnly()">;
 def UseAlternateSExtLoadCVTF32
     : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">;
 
 def UseNegativeImmediates
     : Predicate<"false">, AssemblerPredicate<"!FeatureNoNegativeImmediates",
                                              "NegativeImmediates">;
 
 

lib/Target/AArch64/AArch64MCInstLower.h

 //===-- AArch64MCInstLower.h - Lower MachineInstr to MCInst ---------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MCINSTLOWER_H
 #define LLVM_LIB_TARGET_AARCH64_AARCH64MCINSTLOWER_H
 
 #include "llvm/ADT/Triple.h"
+#include "AArch64Subtarget.h"
 #include "llvm/Support/Compiler.h"
 
 namespace llvm {
 class AsmPrinter;
 class MCAsmInfo;
 class MCContext;
 class MCInst;
 class MCOperand;
 class MCSymbol;
 class MachineInstr;
 class MachineModuleInfoMachO;
 class MachineOperand;
 class Mangler;
 
 /// AArch64MCInstLower - This class is used to lower an MachineInstr
 /// into an MCInst.
 class LLVM_LIBRARY_VISIBILITY AArch64MCInstLower {
   MCContext &Ctx;
   AsmPrinter &Printer;
   Triple TargetTriple;
 
 public:
   AArch64MCInstLower(MCContext &ctx, AsmPrinter &printer);
 
-  bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
+  bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp,
+                    const AArch64Subtarget* ST) const;
   void Lower(const MachineInstr *MI, MCInst &OutMI) const;
 
   MCOperand lowerSymbolOperandDarwin(const MachineOperand &MO,
                                      MCSymbol *Sym) const;
   MCOperand lowerSymbolOperandELF(const MachineOperand &MO,
                                   MCSymbol *Sym) const;
   MCOperand lowerSymbolOperandCOFF(const MachineOperand &MO,
                                    MCSymbol *Sym) const;
   MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
 
   MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const;
   MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const;
 };
 }
 
 #endif

lib/Target/AArch64/AArch64MCInstLower.cpp

MCOperand AArch64MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
   if (Printer.TM.getTargetTriple().isOSBinFormatCOFF())
     return lowerSymbolOperandCOFF(MO, Sym);
 
   assert(Printer.TM.getTargetTriple().isOSBinFormatELF() && "Invalid target");
   return lowerSymbolOperandELF(MO, Sym);
 }
 
 bool AArch64MCInstLower::lowerOperand(const MachineOperand &MO,
-                                      MCOperand &MCOp) const {
+                                      MCOperand &MCOp,
+                                      const AArch64Subtarget *STI) const {
   switch (MO.getType()) {
   default:
     llvm_unreachable("unknown operand type");
   case MachineOperand::MO_Register:
     // Ignore all implicit register operands.
     if (MO.isImplicit())
       return false;
     MCOp = MCOperand::createReg(MO.getReg());
case MachineOperand::MO_ExternalSymbol:
     break;
   case MachineOperand::MO_MCSymbol:
     MCOp = LowerSymbolOperand(MO, MO.getMCSymbol());
     break;
   case MachineOperand::MO_JumpTableIndex:
     MCOp = LowerSymbolOperand(MO, Printer.GetJTISymbol(MO.getIndex()));
     break;
   case MachineOperand::MO_ConstantPoolIndex:
+    if (STI->genExecuteOnly())
+      llvm_unreachable("execute-only should not generate constant pools");
     MCOp = LowerSymbolOperand(MO, Printer.GetCPISymbol(MO.getIndex()));
     break;
   case MachineOperand::MO_BlockAddress:
     MCOp = LowerSymbolOperand(
         MO, Printer.GetBlockAddressSymbol(MO.getBlockAddress()));
     break;
   }
   return true;
 }
 
 void AArch64MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
   OutMI.setOpcode(MI->getOpcode());
 
   for (const MachineOperand &MO : MI->operands()) {
     MCOperand MCOp;
-    if (lowerOperand(MO, MCOp))
+    const AArch64Subtarget *STI =
+        static_cast<const AArch64Subtarget *>(&MI->getMF()->getSubtarget());
+    if (lowerOperand(MO, MCOp, STI))
       OutMI.addOperand(MCOp);
   }
 }

lib/Target/AArch64/AArch64Subtarget.h

enum ARMProcFamilyEnum : uint8_t {
     ThunderXT83,
     ThunderXT88
   };
 
 protected:
   /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
   ARMProcFamilyEnum ARMProcFamily = Others;
 
+  // Generate code that does not contain data access to code sections.
+  bool GenExecuteOnly = false;
+
   bool HasV8_1aOps = false;
   bool HasV8_2aOps = false;
   bool HasV8_3aOps = false;
 
   bool HasFPARMv8 = false;
   bool HasNEON = false;
   bool HasCrypto = false;
   bool HasDotProd = false;
private:
   /// subtarget initialization.
   AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
                                                     StringRef CPUString);
 
   /// Initialize properties based on the selected processor family.
   void initializeProperties();
 
 public:
+
+  bool genExecuteOnly() const { return GenExecuteOnly; }
+
   /// This constructor initializes the data members to match that
   /// of the specified triple.
   AArch64Subtarget(const Triple &TT, const std::string &CPU,
                    const std::string &FS, const TargetMachine &TM,
                    bool LittleEndian);
 
   const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
     return &TSInfo;

lib/Target/AArch64/AArch64TargetObjectFile.h

 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
 #include "llvm/Target/TargetLoweringObjectFile.h"
 
 namespace llvm {
 class AArch64TargetMachine;
 
 /// This implementation is used for AArch64 ELF targets (Linux in particular).
 class AArch64_ELFTargetObjectFile : public TargetLoweringObjectFileELF {
     void Initialize(MCContext &Ctx, const TargetMachine &TM) override;
+
+  public:
+    MCSection *getExplicitSectionGlobal(const GlobalObject *GO, SectionKind Kind,
+                                        const TargetMachine &TM) const override;
+
+    MCSection *SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind,
+                                      const TargetMachine &TM) const override;
+
 };
 
 /// AArch64_MachoTargetObjectFile - This TLOF implementation is used for Darwin.
 class AArch64_MachoTargetObjectFile : public TargetLoweringObjectFileMachO {
 public:
   AArch64_MachoTargetObjectFile();
 
   const MCExpr *getTTypeGlobalReference(const GlobalValue *GV,

lib/Target/AArch64/AArch64TargetObjectFile.cpp

 //===-- AArch64TargetObjectFile.cpp - AArch64 Object Info -----------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "AArch64TargetObjectFile.h"
 #include "AArch64TargetMachine.h"
 #include "llvm/BinaryFormat/Dwarf.h"
 #include "llvm/IR/Mangler.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCValue.h"
 using namespace llvm;
 using namespace dwarf;
 
 void AArch64_ELFTargetObjectFile::Initialize(MCContext &Ctx,
                                              const TargetMachine &TM) {
   TargetLoweringObjectFileELF::Initialize(Ctx, TM);

 
 void AArch64_MachoTargetObjectFile::getNameWithPrefix(
     SmallVectorImpl<char> &OutName, const GlobalValue *GV,
     const TargetMachine &TM) const {
   // AArch64 does not use section-relative relocations so any global symbol must
   // be accessed via at least a linker-private symbol.
   getMangler().getNameWithPrefix(OutName, GV, /* CannotUsePrivateLabel */ true);
 }
+
+static bool isExecuteOnlyFunction(const GlobalObject *GO, SectionKind SK,
+                                  const TargetMachine &TM) {
+  if (const Function *F = dyn_cast<Function>(GO)){
+    if (TM.getSubtarget<AArch64Subtarget>(*F).genExecuteOnly() && SK.isText()){
+      return true;
+    }
+  }
+  return false;
+}
+
+
+MCSection *
+AArch64_ELFTargetObjectFile::getExplicitSectionGlobal(
+    const GlobalObject *GO, SectionKind SK, const TargetMachine &TM) const {
+  // Set execute-only access for the explicit section
+  if (isExecuteOnlyFunction(GO, SK, TM))
+    SK = SectionKind::getExecuteOnly();
+
+  return TargetLoweringObjectFileELF::getExplicitSectionGlobal(GO, SK, TM);
+}
+
+MCSection *
+AArch64_ELFTargetObjectFile::SelectSectionForGlobal(
+    const GlobalObject *GO, SectionKind SK, const TargetMachine &TM) const {
+  // Place the global in the execute-only text section
+  if (isExecuteOnlyFunction(GO, SK, TM))
+    SK = SectionKind::getExecuteOnly();
+
+  return TargetLoweringObjectFileELF::SelectSectionForGlobal(GO, SK, TM);
+}

test/CodeGen/AArch64/execute-only-section.ll

+; RUN: llc < %s -mtriple=aarch64 -mattr=+execute-only %s -o - | FileCheck %s
+
+; CHECK:     .section .text,"axy",@progbits,unique,0
+; CHECK-NOT: .section
+; CHECK-NOT: .text
+; CHECK:     .globl test_SectionForGlobal
+; CHECK:     .type test_SectionForGlobal,@function
+define void @test_SectionForGlobal() {
+entry:
+  ret void
+}
+
+; CHECK:     .section .test,"axy",@progbits
+; CHECK-NOT: .section
+; CHECK-NOT: .text
+; CHECK:     .globl test_ExplicitSectionForGlobal
+; CHECK:     .type test_ExplicitSectionForGlobal,@function
+define void @test_ExplicitSectionForGlobal() section ".test" {
+entry:
+  ret void
+}

tools/llvm-readobj/ELFDumper.cpp

static const EnumEntry<unsigned> ElfXCoreSectionFlags[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, XCORE_SHF_CP_SECTION),
   LLVM_READOBJ_ENUM_ENT(ELF, XCORE_SHF_DP_SECTION)
 };
 
 static const EnumEntry<unsigned> ElfARMSectionFlags[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_ARM_PURECODE)
 };
 
+static const EnumEntry<unsigned> ElfAArch64SectionFlags[] = {
+  LLVM_READOBJ_ENUM_ENT(ELF, SHF_ARM_PURECODE)
+};
+
 static const EnumEntry<unsigned> ElfHexagonSectionFlags[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_HEX_GPREL)
 };
 
 static const EnumEntry<unsigned> ElfMipsSectionFlags[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_NODUPES),
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_NAMES  ),
   LLVM_READOBJ_ENUM_ENT(ELF, SHF_MIPS_LOCAL  ),
W.printHex(
         Sec.sh_type);
     std::vector<EnumEntry<unsigned>> SectionFlags(std::begin(ElfSectionFlags),
                                                   std::end(ElfSectionFlags));
     switch (Obj->getHeader()->e_machine) {
     case EM_ARM:
       SectionFlags.insert(SectionFlags.end(), std::begin(ElfARMSectionFlags),
                           std::end(ElfARMSectionFlags));
       break;
+    case EM_AARCH64:
+      SectionFlags.insert(SectionFlags.end(), std::begin(ElfAArch64SectionFlags),
+                          std::end(ElfAArch64SectionFlags));
+      break;
     case EM_HEXAGON:
       SectionFlags.insert(SectionFlags.end(),
                           std::begin(ElfHexagonSectionFlags),
                           std::end(ElfHexagonSectionFlags));
       break;
     case EM_MIPS:
       SectionFlags.insert(SectionFlags.end(), std::begin(ElfMipsSectionFlags),
                           std::end(ElfMipsSectionFlags));