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[compiler-rt] [msan] Variadic support for AArch64
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Authored by zatrazz on Dec 9 2015, 10:54 AM.

Details

Summary

Now with variadic support for msan on aarch6 there is no need for
XFAIL signal_stress_test anymore. Also to garantee aligned stores
for the FP/SIMD arguments enforce the '__msan_va_arg_tls' alignment
to sizeof the SIMD register (16).

This patch relies on llvm patch http://reviews.llvm.org/D15386

Diff Detail

Event Timeline

zatrazz updated this revision to Diff 42320.Dec 9 2015, 10:54 AM
zatrazz retitled this revision from to [compiler-rt] [msan] Variadic support for AArch64.
zatrazz updated this object.
zatrazz added reviewers: pcc, rengolin, kcc, eugenis, samsonov.
zatrazz added a subscriber: llvm-commits.
eugenis added inline comments.Dec 9 2015, 11:04 AM
lib/msan/msan.cc
58

This only aligns the first element of the array. Why is that sufficient?
Do you need to change instrumentation as well to align each next store location to 16 bytes?

eugenis added inline comments.Dec 9 2015, 11:08 AM
lib/msan/msan.cc
58

OK, just saw the instrumentation change.

zatrazz added inline comments.Dec 9 2015, 11:10 AM
lib/msan/msan.cc
58

Aligning the first element is just what it requires, since the instrumentation phase will store in a 16 aligned offset (64 currently).

eugenis accepted this revision.Dec 9 2015, 11:27 AM
eugenis edited edge metadata.

LGTM, once the llvm change is in.

This revision is now accepted and ready to land.Dec 9 2015, 11:27 AM
zatrazz closed this revision.Dec 14 2015, 6:18 AM