[AArch64] Add ARMv8.2-A UAO PSTATE bit

[olista01]

Summary

ARMv8.2-A adds a new PSTATE bit, PSTATE.UAO, which allows the LDTR/STTR
instructions to behave the same as LDR/STR with respect to execute-only
pages at higher privilege levels. New variants of the MSR/MRS
instructions are added to allow reading and writing this bit. It is a
required part of ARMv8.2-A, so no additional subtarget features are
required.

[t.p.northover]

This looks fine too, with one nit.

Tim.

lib/Target/AArch64/Utils/AArch64BaseInfo.h

468 ↗

(On Diff #41240)

Missing comment here, for consistency.

llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

SDNode *AArch64DAGToDAGISel::SelectWriteRegister(SDNode *N) {
   Reg = PMapper.fromString(RegString->getString(),
                            Subtarget->getFeatureBits(),
                            IsValidSpecialReg);
   if (IsValidSpecialReg) {
     assert (isa<ConstantSDNode>(N->getOperand(2))
               && "Expected a constant integer expression.");
     uint64_t Immed = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
     unsigned State;
-    if (Reg == AArch64PState::PAN) {
+    if (Reg == AArch64PState::PAN || Reg == AArch64PState::UAO) {
       assert(Immed < 2 && "Bad imm");
       State = AArch64::MSRpstateImm1;
     } else {
       assert(Immed < 16 && "Bad imm");
       State = AArch64::MSRpstateImm4;
     }
     return CurDAG->getMachineNode(State, DL, MVT::Other,
                                   CurDAG->getTargetConstant(Reg, DL, MVT::i32),

llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

bool isMRSSystemRegister() const {
     return SysReg.MRSReg != -1U;
   }
   bool isMSRSystemRegister() const {
     if (!isSysReg()) return false;
     return SysReg.MSRReg != -1U;
   }
   bool isSystemPStateFieldWithImm0_1() const {
     if (!isSysReg()) return false;
-    return SysReg.PStateField == AArch64PState::PAN;
+    return (SysReg.PStateField == AArch64PState::PAN ||
+            SysReg.PStateField == AArch64PState::UAO);
   }
   bool isSystemPStateFieldWithImm0_15() const {
     if (!isSysReg() || isSystemPStateFieldWithImm0_1()) return false;
     return SysReg.PStateField != -1U;
   }
   bool isReg() const override { return Kind == k_Register && !Reg.isVector; }
   bool isVectorReg() const { return Kind == k_Register && Reg.isVector; }
   bool isVectorRegLo() const {

llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

static DecodeStatus DecodeSystemPStateInstruction(llvm::MCInst &Inst,
                                                   uint32_t insn, uint64_t Addr,
                                                   const void *Decoder) {
   uint64_t op1 = fieldFromInstruction(insn, 16, 3);
   uint64_t op2 = fieldFromInstruction(insn, 5, 3);
   uint64_t crm = fieldFromInstruction(insn, 8, 4);
 
   uint64_t pstate_field = (op1 << 3) | op2;
 
-  if (pstate_field == AArch64PState::PAN && crm > 1)
+  if ((pstate_field == AArch64PState::PAN  ||
+       pstate_field == AArch64PState::UAO) && crm > 1)
     return Fail;
 
   Inst.addOperand(MCOperand::createImm(pstate_field));
   Inst.addOperand(MCOperand::createImm(crm));
 
   bool ValidNamed;
   const AArch64Disassembler *Dis = 
       static_cast<const AArch64Disassembler *>(Decoder);

llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h

namespace AArch64PState {
   enum PStateValues {
     Invalid = -1,
     SPSel = 0x05,
     DAIFSet = 0x1e,
     DAIFClr = 0x1f,
 
     // v8.1a "Privileged Access Never" extension-specific PStates
     PAN = 0x04,
+
+    // v8.2a "User Access Override" extension-specific PStates
+    UAO = 0x03
   };
 
   struct PStateMapper : AArch64NamedImmMapper {
     const static Mapping PStateMappings[];
 
     PStateMapper();
   };
 
enum SysRegValues {
     CNTP_CTL_EL02     = 0xef11, // 11  101  1110  0010  001
     CNTP_CVAL_EL02    = 0xef12, // 11  101  1110  0010  010
     CNTV_TVAL_EL02    = 0xef18, // 11  101  1110  0011  000
     CNTV_CTL_EL02     = 0xef19, // 11  101  1110  0011  001
     CNTV_CVAL_EL02    = 0xef1a, // 11  101  1110  0011  010
     SPSR_EL12         = 0xea00, // 11  101  0100  0000  000
     ELR_EL12          = 0xea01, // 11  101  0100  0000  001
 
+    // v8.2a registers
+    UAO               = 0xc214, // 11  000  0100  0010  100
+
     // Cyclone specific system registers
     CPM_IOACC_CTL_EL3 = 0xff90,
   };
 
   // Note that these do not inherit from AArch64NamedImmMapper. This class is
   // sufficiently different in its behaviour that I don't believe it's worth
   // burdening the common AArch64NamedImmMapper with abstractions only needed in
   // this one case.

llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp

 
 const AArch64NamedImmMapper::Mapping AArch64PState::PStateMapper::PStateMappings[] = {
   {"spsel", SPSel, {}},
   {"daifset", DAIFSet, {}},
   {"daifclr", DAIFClr, {}},
 
   // v8.1a "Privileged Access Never" extension-specific PStates
   {"pan", PAN, {AArch64::HasV8_1aOps}},
+
+  // v8.2a
+  {"uao", UAO, {AArch64::HasV8_2aOps}},
 };
 
 AArch64PState::PStateMapper::PStateMapper()
   : AArch64NamedImmMapper(PStateMappings, 0) {}
 
 const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
   {"mdccsr_el0", MDCCSR_EL0, {}},
   {"dbgdtrrx_el0", DBGDTRRX_EL0, {}},
const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegMappings[] = {
   {"cntp_tval_el02", CNTP_TVAL_EL02, {AArch64::HasV8_1aOps}},
   {"cntp_ctl_el02", CNTP_CTL_EL02, {AArch64::HasV8_1aOps}},
   {"cntp_cval_el02", CNTP_CVAL_EL02, {AArch64::HasV8_1aOps}},
   {"cntv_tval_el02", CNTV_TVAL_EL02, {AArch64::HasV8_1aOps}},
   {"cntv_ctl_el02", CNTV_CTL_EL02, {AArch64::HasV8_1aOps}},
   {"cntv_cval_el02", CNTV_CVAL_EL02, {AArch64::HasV8_1aOps}},
   {"spsr_el12", SPSR_EL12, {AArch64::HasV8_1aOps}},
   {"elr_el12", ELR_EL12, {AArch64::HasV8_1aOps}},
+
+  // v8.2a registers
+  {"uao",           UAO,           {AArch64::HasV8_2aOps}},
 };
 
 uint32_t
 AArch64SysReg::SysRegMapper::fromString(StringRef Name, 
     const FeatureBitset& FeatureBits, bool &Valid) const {
   std::string NameLower = Name.lower();
 
   // First search the registers shared by all

llvm/trunk/test/MC/AArch64/armv8.2a-uao.s

+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s 2> %t | FileCheck %s
+// RUN: FileCheck --check-prefix=CHECK-ERROR %s < %t
+
+  msr uao, #0
+  msr uao, #1
+// CHECK: msr     UAO, #0                 // encoding: [0x7f,0x40,0x00,0xd5]
+// CHECK: msr     UAO, #1                 // encoding: [0x7f,0x41,0x00,0xd5]
+
+  msr uao, #2
+// CHECK-ERROR: error: immediate must be an integer in range [0, 1].
+// CHECK-ERROR:   msr uao, #2
+// CHECK-ERROR:            ^
+
+  msr uao, x1
+  mrs x2, uao
+// CHECK: msr     UAO, x1                 // encoding: [0x81,0x42,0x18,0xd5]
+// CHECK: mrs     x2, UAO                 // encoding: [0x82,0x42,0x38,0xd5]

llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-uao.txt

+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu --disassemble < %s 2>&1 | FileCheck --check-prefix=NO_V82A %s
+
+[0x7f,0x40,0x00,0xd5]
+[0x7f,0x41,0x00,0xd5]
+[0x7f,0x42,0x00,0xd5]
+# CHECK: msr UAO, #0
+# CHECK: msr UAO, #1
+# CHECK: msr S0_0_C4_C2_3, xzr
+# NO_V82A: msr S0_0_C4_C0_3, xzr
+# NO_V82A: msr S0_0_C4_C1_3, xzr
+# NO_V82A: msr S0_0_C4_C2_3, xzr
+
+[0x81,0x42,0x18,0xd5]
+[0x82,0x42,0x38,0xd5]
+# CHECK: msr UAO, x1
+# CHECK: mrs x2, UAO
+# NO_V82A: msr S3_0_C4_C2_4, x1
+# NO_V82A: mrs x2, S3_0_C4_C2_4