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Differential D15017

[AArch64] Add ARMv8.2-A ID_A64MMFR2_EL1 register
ClosedPublic

Authored by olista01 on Nov 26 2015, 5:13 AM.

Details

Reviewers
t.p.northover
Commits
rG48b43741d077: [AArch64] Add ARMv8.2-A ID_A64MMFR2_EL1 register
rL254155: [AArch64] Add ARMv8.2-A ID_A64MMFR2_EL1 register
Summary

ARMv8.2-A adds a new ID register, ID_A64MMFR2_EL1, which behaves in the
same way as ID_A64MMFR0_EL1 and ID_A64MMFR1_EL1. It is a required part
of ARMv8.2-A, so no additional subtarget features are required.

Diff Detail

Repository
rL LLVM

Event Timeline

olista01 updated this revision to Diff 41238.Nov 26 2015, 5:13 AM
olista01 retitled this revision from to [AArch64] Add ARMv8.2-A ID_A64MMFR2_EL1 register.
olista01 updated this object.
olista01 added a reviewer: t.p.northover.
olista01 set the repository for this revision to rL LLVM.
olista01 added a subscriber: llvm-commits.
Herald added subscribers: rengolin, aemerson. · View Herald TranscriptNov 26 2015, 5:13 AM
olista01 added a parent revision: D15013: [AArch64] Add subtarget features for ARMv8.2-A.Nov 26 2015, 5:13 AM
t.p.northover accepted this revision.Nov 26 2015, 7:13 AM
t.p.northover edited edge metadata.

This looks fine to me too.

Tim.

This revision is now accepted and ready to land.Nov 26 2015, 7:13 AM
Closed by commit rL254155: [AArch64] Add ARMv8.2-A ID_A64MMFR2_EL1 register (authored by olista01). · Explain WhyNov 26 2015, 7:29 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AArch64/
Utils/
1 line
1 line
test/
MC/
AArch64/
6 lines
Disassembler/
AArch64/
4 lines

Diff 41253

llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h

Show First 20 Lines • Show All 588 Lines • ▼ Show 20 Lines enum SysRegROValues {
ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000 ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001 ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100 ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101 ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000 ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001 ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000 ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001 ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
ID_A64MMFR2_EL1 = 0xc03a, // 11 000 0000 0111 010
MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000 MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001 RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001 RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001 RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
ISR_EL1 = 0xc608, // 11 000 1100 0001 000 ISR_EL1 = 0xc608, // 11 000 1100 0001 000
CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001 CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
▲ Show 20 Lines • Show All 750 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp

Show First 20 Lines • Show All 186 Lines • ▼ Show 20 Linesconst AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
{"id_aa64dfr0_el1", ID_A64DFR0_EL1, {}}, {"id_aa64dfr0_el1", ID_A64DFR0_EL1, {}},
{"id_aa64dfr1_el1", ID_A64DFR1_EL1, {}}, {"id_aa64dfr1_el1", ID_A64DFR1_EL1, {}},
{"id_aa64afr0_el1", ID_A64AFR0_EL1, {}}, {"id_aa64afr0_el1", ID_A64AFR0_EL1, {}},
{"id_aa64afr1_el1", ID_A64AFR1_EL1, {}}, {"id_aa64afr1_el1", ID_A64AFR1_EL1, {}},
{"id_aa64isar0_el1", ID_A64ISAR0_EL1, {}}, {"id_aa64isar0_el1", ID_A64ISAR0_EL1, {}},
{"id_aa64isar1_el1", ID_A64ISAR1_EL1, {}}, {"id_aa64isar1_el1", ID_A64ISAR1_EL1, {}},
{"id_aa64mmfr0_el1", ID_A64MMFR0_EL1, {}}, {"id_aa64mmfr0_el1", ID_A64MMFR0_EL1, {}},
{"id_aa64mmfr1_el1", ID_A64MMFR1_EL1, {}}, {"id_aa64mmfr1_el1", ID_A64MMFR1_EL1, {}},
{"id_aa64mmfr2_el1", ID_A64MMFR2_EL1, {AArch64::HasV8_2aOps}},
{"mvfr0_el1", MVFR0_EL1, {}}, {"mvfr0_el1", MVFR0_EL1, {}},
{"mvfr1_el1", MVFR1_EL1, {}}, {"mvfr1_el1", MVFR1_EL1, {}},
{"mvfr2_el1", MVFR2_EL1, {}}, {"mvfr2_el1", MVFR2_EL1, {}},
{"rvbar_el1", RVBAR_EL1, {}}, {"rvbar_el1", RVBAR_EL1, {}},
{"rvbar_el2", RVBAR_EL2, {}}, {"rvbar_el2", RVBAR_EL2, {}},
{"rvbar_el3", RVBAR_EL3, {}}, {"rvbar_el3", RVBAR_EL3, {}},
{"isr_el1", ISR_EL1, {}}, {"isr_el1", ISR_EL1, {}},
{"cntpct_el0", CNTPCT_EL0, {}}, {"cntpct_el0", CNTPCT_EL0, {}},
▲ Show 20 Lines • Show All 713 Lines • Show Last 20 Lines

llvm/trunk/test/MC/AArch64/armv8.2a-mmfr2.s

// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
mrs x3, id_aa64mmfr2_el1
// CHECK: mrs x3, ID_AA64MMFR2_EL1 // encoding: [0x43,0x07,0x38,0xd5]
// ERROR: error: expected readable system register

llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-mmfr2.txt

# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
[0x43,0x07,0x38,0xd5]
# CHECK: mrs x3, ID_AA64MMFR2_EL1