[AArch64] Add ARMv8.2-A new AT instruction variants

[olista01]

Summary

ARMv8.2-A adds new variants of the "at" (address translate) system
instruction, which take the PSTATE.PAN bit (added in ARMv8.1-A). These
are a required part of ARMv8.2-A, so no additional subtarget features
are required.

[t.p.northover]

Looks good, which just leaves the big ones I think.

Tim.

llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

if (!Op.compare_lower("s1e1r")) {
       // SYS #4, C7, C8, #5
       SYS_ALIAS(4, 7, 8, 5);
     } else if (!Op.compare_lower("s12e0r")) {
       // SYS #4, C7, C8, #6
       SYS_ALIAS(4, 7, 8, 6);
     } else if (!Op.compare_lower("s12e0w")) {
       // SYS #4, C7, C8, #7
       SYS_ALIAS(4, 7, 8, 7);
+    } else if (!Op.compare_lower("s1e1rp")) {
+      if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
+        // SYS #0, C7, C9, #0
+        SYS_ALIAS(0, 7, 9, 0);
+      } else {
+        return TokError("AT S1E1RP requires ARMv8.2a");
+      }
+    } else if (!Op.compare_lower("s1e1wp")) {
+      if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
+        // SYS #0, C7, C9, #1
+        SYS_ALIAS(0, 7, 9, 1);
+      } else {
+        return TokError("AT S1E1WP requires ARMv8.2a");
+      }
     } else {
       return TokError("invalid operand for AT instruction");
     }
   } else if (Mnemonic == "tlbi") {
     if (!Op.compare_lower("vmalle1is")) {
       // SYS #0, C8, C3, #0
       SYS_ALIAS(0, 8, 3, 0);
     } else if (!Op.compare_lower("alle2is")) {

llvm/trunk/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp

case 8:
         default:
           break;
         case 0: Asm = "at\ts1e3r"; break;
         case 1: Asm = "at\ts1e3w"; break;
         }
         break;
       }
       break;
+    case 9:
+      switch (Op1Val) {
+      default:
+        break;
+      case 0:
+        if (STI.getFeatureBits()[AArch64::HasV8_2aOps]) {
+          switch (Op2Val) {
+          default:
+            break;
+          case 0: Asm = "at\ts1e1rp"; break;
+          case 1: Asm = "at\ts1e1wp"; break;
+          }
+        }
+        break;
+      }
     }
   } else if (CnVal == 8) {
     // TLBI aliases
     switch (CmVal) {
     default:
       break;
     case 3:
       switch (Op1Val) {

llvm/trunk/lib/Target/AArch64/Utils/AArch64BaseInfo.h

enum ATValues {
     S1E1W = 0x43c1,  // 01  000  0111  1000  001
     S1E2W = 0x63c1,  // 01  100  0111  1000  001
     S1E3W = 0x73c1,  // 01  110  0111  1000  001
     S1E0R = 0x43c2,  // 01  000  0111  1000  010
     S1E0W = 0x43c3,  // 01  000  0111  1000  011
     S12E1R = 0x63c4, // 01  100  0111  1000  100
     S12E1W = 0x63c5, // 01  100  0111  1000  101
     S12E0R = 0x63c6, // 01  100  0111  1000  110
-    S12E0W = 0x63c7  // 01  100  0111  1000  111
+    S12E0W = 0x63c7, // 01  100  0111  1000  111
+    S1E1RP = 0x43c8, // 01  000  0111  1001  000
+    S1E1WP = 0x43c9  // 01  000  0111  1001  001
   };
 
   struct ATMapper : AArch64NamedImmMapper {
     const static Mapping ATMappings[];
 
     ATMapper();
   };
 

llvm/trunk/test/MC/AArch64/armv8.2a-at.s

+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+  at s1e1rp, x1
+  at s1e1wp, x2
+// CHECK: at      s1e1rp, x1              // encoding: [0x01,0x79,0x08,0xd5]
+// CHECK: at      s1e1wp, x2              // encoding: [0x22,0x79,0x08,0xd5]
+// ERROR: error: AT S1E1RP requires ARMv8.2a
+// ERROR: error: AT S1E1WP requires ARMv8.2a

llvm/trunk/test/MC/Disassembler/AArch64/armv8.2a-at.txt

+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.2a --disassemble < %s | FileCheck %s --check-prefix=NO_V82
+
+[0x01,0x79,0x08,0xd5]
+[0x22,0x79,0x08,0xd5]
+# CHECK: at s1e1rp, x1
+# CHECK: at s1e1wp, x2
+# NO_V82: sys     #0, c7, c9, #0, x1
+# NO_V82: sys     #0, c7, c9, #1, x2