AMDGPU: Exclude SGPRs except m0 from movrel operands

[arsenm]

Summary

Due to the constant bus restriction a literal constant
or SGPR other than m0 can't be used depite the operand
encoding. Fix the operand class to avoid having to manually
legalize the constant bus restriction.

The test change is a surprising scheduling change which
I'm not really sure why it happened since none of these
instructions are used in it. I'm guessing one of the generated
getCommon*Class functions now behaves somewhat differently.
This could probably be avoided by not allowing m0 either,
since that is probably not really useful.

[arsenm]

Set isAllocatable = 0 to fix test changes

[• tstellarAMD]

I've seen scheduler changes like this before. I think adding the new register class affects the register pressure analysis.

lib/Target/AMDGPU/SIInstructions.td

1344–1347

Using M0 as src1, is only possible for V_MOVERELD_B32, because the other two use src1 as the base register and aren't actually reading values from it.

[arsenm]

Only allow for movreld. The test change is apparently still necessary even with isAllocatable = 0 for some reason

[• tstellarAMD]

LGTM.

[Eugene.Zelenko]

Looks like patch was not committed.

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

public:
   bool isVCSrc32() const {
     return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID));
   }
 
   bool isVCSrc64() const {
     return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID));
   }
 
+  bool isVCM0Src32() const {
+    return isInlineImm() || (isReg() && isRegClass(AMDGPU::VM0_32RegClassID));
+  }
+
   bool isVSrc32() const {
     return isImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID));
   }
 
   bool isVSrc64() const {
     return isImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID));
   }
 

lib/Target/AMDGPU/SIInstrInfo.td

 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
 
+// Special case for v_movreld_b32 instructions which have an implicit
+// m0 use. An SGPR besides m0 can't be used for src0 because of the
+// constant bus restriction with the implicit use.
+def VOP_I32_I32_M0 : VOPProfile <[i32, i32, untyped, untyped]> {
+  let Src0RC32 = VCM0Src_32;
+  let Src0RC64 = VCM0Src_32;
+}
+
+// Special case for v_movrels_b32 and v_movrelsd_b32.
+// The source is the base VGPR so it must be a VGPR.
+def VOP_I32_VI32 : VOPProfile <[i32, i32, untyped, untyped]> {
+  let Src0RC32 = RegisterOperand<VGPR_32>;
+  let Src0RC64 = RegisterOperand<VGPR_32>;
+}
+
 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
 

lib/Target/AMDGPU/SIInstructions.td

 defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40, 0x34>, "v_frexp_mant_f32",
   VOP_F32_F32
 >;
 let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in {
 defm V_CLREXCP : VOP1Inst <vop1<0x41,0x35>, "v_clrexcp", VOP_NONE>;
 }
 
 let Uses = [M0, EXEC] in {
-defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_I32_I32>;
-defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_I32_I32>;
-defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_I32_I32>;
+defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_I32_I32_M0>;
+defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_I32_VI32>;
+defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_I32_VI32>;
 } // End Uses = [M0, EXEC]
 
 // These instruction only exist on SI and CI
 let SubtargetPredicate = isSICI in {
 
 let SchedRW = [WriteQuarterRate32] in {
 
 defm V_MOV_FED_B32 : VOP1InstSI <vop1<0x9>, "v_mov_fed_b32", VOP_I32_I32>;
 defm V_LOG_CLAMP_F32 : VOP1InstSI <vop1<0x26>, "v_log_clamp_f32", VOP_F32_F32>;

lib/Target/AMDGPU/SIRegisterInfo.td

 
 def VSrc_64 : RegisterOperand<VS_64> {
   let OperandNamespace = "AMDGPU";
   let OperandType = "OPERAND_REG_IMM32";
   let ParserMatchClass = RegImmMatcher<"VSrc64">;
 }
 
 //===----------------------------------------------------------------------===//
+//  VM0_32_* Operands with an VGPR, m0 or a 32-bit immediate
+//===----------------------------------------------------------------------===//
+
+// FIXME: This somehow is influencing scheduling changes even when
+// unused by any instruction.
+def VM0_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, M0)> {
+  // This is only for modeling operand constraints.
+  let isAllocatable = 0;
+}
+
+// Special case for v_movreld_b32. The encoding allows SGPRs, but due
+// to the constant bus restriction, only m0 could be allowed (although
+// probably not useful).
+def VCM0Src_32 : RegisterOperand<VM0_32> {
+  let OperandNamespace = "AMDGPU";
+  let OperandType = "OPERAND_REG_IMM32";
+  let ParserMatchClass = RegImmMatcher<"VCM0Src32">;
+}
+
+//===----------------------------------------------------------------------===//
 //  VCSrc_* Operands with an SGPR, VGPR or an inline constant
 //===----------------------------------------------------------------------===//
 
 def VCSrc_32 : RegisterOperand<VS_32> {
   let OperandNamespace = "AMDGPU";
   let OperandType = "OPERAND_REG_INLINE_C";
   let ParserMatchClass = RegImmMatcher<"VCSrc32">;
 }

test/CodeGen/AMDGPU/ds_read2st64.ll

define void @simple_read2st64_f32_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
   %sum = fadd float %val0, %val1
   %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
   store float %sum, float addrspace(1)* %out.gep, align 4
   ret void
 }
 
 ; SI-LABEL: @simple_read2st64_f32_over_max_offset
 ; SI-NOT: ds_read2st64_b32
-; SI: v_add_i32_e32 [[BIGADD:v[0-9]+]], vcc, 0x10000, {{v[0-9]+}}
-; SI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:256
-; SI: ds_read_b32 {{v[0-9]+}}, [[BIGADD]]
+; SI-DAG: v_add_i32_e32 [[BIGADD:v[0-9]+]], vcc, 0x10000, {{v[0-9]+}}
+; SI-DAG: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:256
+; SI-DAG: ds_read_b32 {{v[0-9]+}}, [[BIGADD]]
 ; SI: s_endpgm
 define void @simple_read2st64_f32_over_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {
   %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
   %add.x.0 = add nsw i32 %x.i, 64
   %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.0
   %val0 = load float, float addrspace(3)* %arrayidx0, align 4
   %add.x.1 = add nsw i32 %x.i, 16384
   %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.1

test/MC/AMDGPU/vop1-err.s

+// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s
+
+// SGPR not allowed due to constant bus restriction with implicit m0 read.
+
+// CHECK: error: invalid operand for instruction
+v_movreld_b32 v1, s0
+
+// CHECK: error: invalid operand for instruction
+v_movrels_b32 v1, s0
+
+// CHECK: error: invalid operand for instruction
+v_movrelsd_b32 v1, s0
+
+// CHECK: error: invalid operand for instruction
+v_movrels_b32 v1, 7
+
+// CHECK: error: invalid operand for instruction
+v_movrelsd_b32 v1, 7
+
+// CHECK: error: invalid operand for instruction
+v_movrels_b32 v1, m0
+
+// CHECK: error: invalid operand for instruction
+v_movrelsd_b32 v1, m0
+
+// CHECK: error: invalid operand for instruction
+v_movreld_b32 v1, 0x1234
+
+// CHECK: error: invalid operand for instruction
+v_movrels_b32 v1, 0x1234
+
+// CHECK: error: invalid operand for instruction
+v_movrelsd_b32 v1, 0x1234

test/MC/AMDGPU/vop1.s

 // SICI: v_clrexcp ; encoding: [0x00,0x82,0x00,0x7e]
 // VI:   v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
 v_clrexcp
 
 // SICI: v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x85,0x02,0x7e]
 // VI:   v_movreld_b32_e32 v1, v2 ; encoding: [0x02,0x6d,0x02,0x7e]
 v_movreld_b32 v1, v2
 
+// SICI: v_movreld_b32_e32 v1, m0 ; encoding: [0x7c,0x84,0x02,0x7e]
+// VI:   v_movreld_b32_e32 v1, m0 ; encoding: [0x7c,0x6c,0x02,0x7e]
+v_movreld_b32 v1, m0
+
+// SICI: v_movreld_b32_e32 v1, 7 ; encoding: [0x87,0x84,0x02,0x7e]
+// VI:   v_movreld_b32_e32 v1, 7 ; encoding: [0x87,0x6c,0x02,0x7e]
+v_movreld_b32 v1, 7
+
 // SICI: v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x87,0x02,0x7e]
 // VI:   v_movrels_b32_e32 v1, v2 ; encoding: [0x02,0x6f,0x02,0x7e]
 v_movrels_b32 v1, v2
 
 // SICI: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x89,0x02,0x7e]
 // VI:   v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e]
 v_movrelsd_b32 v1, v2