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Differential D117741

[RISCV] Set CostPerUse to 1 iff RVC is enabled
ClosedPublic

Authored by • pcwang-thead on Jan 19 2022, 8:34 PM.

Details

Reviewers
asb
jrtc27
craig.topper
luismarques
sjarus
Commits
rG8def89b5dc82: [RISCV] Set CostPerUse to 1 iff RVC is enabled
Summary

After D86836, we can define multiple cost values for
different cost models. So here we set CostPerUse to
1 iff RVC is enabled to avoid potential impact on RA.

Diff Detail

Event Timeline

• pcwang-thead created this revision.Jan 19 2022, 8:34 PM
Herald added a reviewer: sjarus. · View Herald TranscriptJan 19 2022, 8:34 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 26 others. · View Herald Transcript
• pcwang-thead requested review of this revision.Jan 19 2022, 8:34 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 19 2022, 8:34 PM
Herald added subscribers: llvm-commits, eopXD, MaskRay. · View Herald Transcript
craig.topper added inline comments.Jan 19 2022, 8:48 PM
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
353

Stylistically I'd prefer this as MF.getSubtarget<RISCVSubtarget>().hasStdExtC() ? 1 : 0

That makes it a little more obvious it is returning an index and not boolean.

llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
1

Drop this line. the test is generated by both update_llc_test_checks.py and update_test_checks.py. Having the comment at the top prevents the opposite script from being able to run on the file.

• pcwang-thead updated this revision to Diff 401496.Jan 19 2022, 9:06 PM

Address comments.

jrtc27 added a comment.Jan 19 2022, 9:21 PM

This scheme seems rather inflexible. We can get away with it currently since the default behaviour of zero-filling CostPerUse elements out to the maximum list size works in every case, but I could see there being issues in future where you end up needing to be extremely verbose to avoid such behaviour.

Harbormaster completed remote builds in B144474: Diff 401496.Jan 19 2022, 9:56 PM
Cookfeces added a subscriber: Cookfeces.Jan 19 2022, 10:01 PM
craig.topper added a comment.Jan 19 2022, 11:05 PM

This seems reasonable to me. I think @jrtc27 's is directed at the general cost per use list mechanism and not specifically about the functional change of this patch. @jrtc27, please correct me if I'm wrong.

• pcwang-thead added a comment.Jan 19 2022, 11:11 PM
In D117741#3257026, @jrtc27 wrote:

This scheme seems rather inflexible. We can get away with it currently since the default behaviour of zero-filling CostPerUse elements out to the maximum list size works in every case, but I could see there being issues in future where you end up needing to be extremely verbose to avoid such behaviour.

Correct me if I am wrong, we shall define CostPerUse=[0, 0] explicitly for RVC registers?

• pcwang-thead added a comment.Jan 20 2022, 1:21 AM

I have one question: Should we set CostPerUse for floating point registers? If so, we may need to unroll the register definitions for F&D manually.

• pcwang-thead updated this revision to Diff 401600.Jan 20 2022, 4:52 AM

Set CostPerUse for floating point registers.

Harbormaster completed remote builds in B144555: Diff 401600.Jan 20 2022, 5:35 AM
luismarques added a comment.Jan 20 2022, 5:54 AM
In D117741#3257196, @pcwang-thead wrote:
In D117741#3257026, @jrtc27 wrote:

This scheme seems rather inflexible. We can get away with it currently since the default behaviour of zero-filling CostPerUse elements out to the maximum list size works in every case, but I could see there being issues in future where you end up needing to be extremely verbose to avoid such behaviour.

Correct me if I am wrong, we shall define CostPerUse=[0, 0] explicitly for RVC registers?

If I understand correctly, that would be enough to address @jrtc27's comment, no?

Overall LGTM. Maybe just clarify and address that previous point?

jrtc27 added a comment.Jan 20 2022, 5:57 AM
In D117741#3258034, @luismarques wrote:
In D117741#3257196, @pcwang-thead wrote:
In D117741#3257026, @jrtc27 wrote:

This scheme seems rather inflexible. We can get away with it currently since the default behaviour of zero-filling CostPerUse elements out to the maximum list size works in every case, but I could see there being issues in future where you end up needing to be extremely verbose to avoid such behaviour.

Correct me if I am wrong, we shall define CostPerUse=[0, 0] explicitly for RVC registers?

If I understand correctly, that would be enough to address @jrtc27's comment, no?

Overall LGTM. Maybe just clarify and address that previous point?

No, I would rather not do that. My concern is that if we ever want more than one dimension, much like HwMode, we will have to expand out the 2^N possibilities for every register, with most entries being duplicates. That would only be solved if you could, say, choose the index based on what register is being asked about, not just the MachineFunction, as then you could have different meanings for CostPerUse indices between different sets of registers.

craig.topper added inline comments.Jan 20 2022, 8:33 AM
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
181

We discussed this at the RISC-V sync up this morning. I don't believe this should be part of this patch. Relaxing the restriction on non-RVC as you did in your original revision is non-controversial. Applying a new restriction on floating point with RVC may require performance measurements to be done.

• pcwang-thead added inline comments.Jan 20 2022, 7:00 PM
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
181

Thanks. I will revert this patch to the original version and create another one for floating point registers after running SPEC FP (if it's profitable).

• pcwang-thead updated this revision to Diff 401858.Jan 20 2022, 9:37 PM
  • Rebase.
  • Revert to the original version.
• pcwang-thead marked 3 inline comments as done.Jan 20 2022, 9:38 PM
craig.topper accepted this revision.Jan 20 2022, 9:38 PM

LGTM

llvm/lib/Target/RISCV/RISCVRegisterInfo.td
181

Code size numbers would be good too.

This revision is now accepted and ready to land.Jan 20 2022, 9:38 PM
Harbormaster completed remote builds in B144740: Diff 401858.Jan 20 2022, 10:25 PM
Closed by commit rG8def89b5dc82: [RISCV] Set CostPerUse to 1 iff RVC is enabled (authored by • pcwang-thead). · Explain WhyJan 20 2022, 10:45 PM
This revision was automatically updated to reflect the committed changes.
• pcwang-thead added a commit: rG8def89b5dc82: [RISCV] Set CostPerUse to 1 iff RVC is enabled.

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Diff 401866

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Linesstruct RISCVRegisterInfo : public RISCVGenRegisterInfo {
} }
const TargetRegisterClass * const TargetRegisterClass *
getLargestLegalSuperClass(const TargetRegisterClass *RC, getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &) const override; const MachineFunction &) const override;
void getOffsetOpcodes(const StackOffset &Offset, void getOffsetOpcodes(const StackOffset &Offset,
SmallVectorImpl<uint64_t> &Ops) const override; SmallVectorImpl<uint64_t> &Ops) const override;
unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override;
}; };
} }
#endif #endif

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

Show First 20 Lines • Show All 341 Lines • ▼ Show 20 Linesvoid RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset,
} else if (VLENBSized < 0) { } else if (VLENBSized < 0) {
Ops.push_back(dwarf::DW_OP_constu); Ops.push_back(dwarf::DW_OP_constu);
Ops.push_back(-VLENBSized); Ops.push_back(-VLENBSized);
Ops.append({dwarf::DW_OP_bregx, VLENB, 0ULL}); Ops.append({dwarf::DW_OP_bregx, VLENB, 0ULL});
Ops.push_back(dwarf::DW_OP_mul); Ops.push_back(dwarf::DW_OP_mul);
Ops.push_back(dwarf::DW_OP_minus); Ops.push_back(dwarf::DW_OP_minus);
} }
} }
unsigned
RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const {
return MF.getSubtarget<RISCVSubtarget>().hasStdExtC() ? 1 : 0;
craig.topperUnsubmitted
Done
ReplyInline Actions

Stylistically I'd prefer this as MF.getSubtarget<RISCVSubtarget>().hasStdExtC() ? 1 : 0

That makes it a little more obvious it is returning an index and not boolean.

craig.topper: Stylistically I'd prefer this as `MF.getSubtarget<RISCVSubtarget>().hasStdExtC() ? 1 : 0` That…
}

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Show First 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
} // Namespace = "RISCV" } // Namespace = "RISCV"
// Integer registers // Integer registers
// CostPerUse is set higher for registers that may not be compressible as they // CostPerUse is set higher for registers that may not be compressible as they
// are not part of GPRC, the most restrictive register class used by the // are not part of GPRC, the most restrictive register class used by the
// compressed instruction set. This will influence the greedy register // compressed instruction set. This will influence the greedy register
// allocator to reduce the use of registers that can't be encoded in 16 bit // allocator to reduce the use of registers that can't be encoded in 16 bit
// instructions. This affects register allocation even when compressed // instructions.
// instruction isn't targeted, we see no major negative codegen impact.
let RegAltNameIndices = [ABIRegAltName] in { let RegAltNameIndices = [ABIRegAltName] in {
def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>; def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
let CostPerUse = [1] in { let CostPerUse = [0, 1] in {
def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>; def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>; def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>; def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>; def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>; def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>; def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>; def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>;
} }
def X8 : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>; def X8 : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>;
def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>; def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>;
def X10 : RISCVReg<10,"x10", ["a0"]>, DwarfRegNum<[10]>; def X10 : RISCVReg<10,"x10", ["a0"]>, DwarfRegNum<[10]>;
def X11 : RISCVReg<11,"x11", ["a1"]>, DwarfRegNum<[11]>; def X11 : RISCVReg<11,"x11", ["a1"]>, DwarfRegNum<[11]>;
def X12 : RISCVReg<12,"x12", ["a2"]>, DwarfRegNum<[12]>; def X12 : RISCVReg<12,"x12", ["a2"]>, DwarfRegNum<[12]>;
def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>; def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>;
def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>; def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>;
def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>; def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>;
let CostPerUse = [1] in { let CostPerUse = [0, 1] in {
def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>; def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>;
def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>; def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>;
def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>; def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>;
def X19 : RISCVReg<19,"x19", ["s3"]>, DwarfRegNum<[19]>; def X19 : RISCVReg<19,"x19", ["s3"]>, DwarfRegNum<[19]>;
def X20 : RISCVReg<20,"x20", ["s4"]>, DwarfRegNum<[20]>; def X20 : RISCVReg<20,"x20", ["s4"]>, DwarfRegNum<[20]>;
def X21 : RISCVReg<21,"x21", ["s5"]>, DwarfRegNum<[21]>; def X21 : RISCVReg<21,"x21", ["s5"]>, DwarfRegNum<[21]>;
def X22 : RISCVReg<22,"x22", ["s6"]>, DwarfRegNum<[22]>; def X22 : RISCVReg<22,"x22", ["s6"]>, DwarfRegNum<[22]>;
def X23 : RISCVReg<23,"x23", ["s7"]>, DwarfRegNum<[23]>; def X23 : RISCVReg<23,"x23", ["s7"]>, DwarfRegNum<[23]>;
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
} }
def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> { def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> {
let RegInfos = XLenRI; let RegInfos = XLenRI;
} }
// Floating point registers // Floating point registers
let RegAltNameIndices = [ABIRegAltName] in { let RegAltNameIndices = [ABIRegAltName] in {
def F0_H : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>; def F0_H : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>;
craig.topperUnsubmitted
Done
ReplyInline Actions

We discussed this at the RISC-V sync up this morning. I don't believe this should be part of this patch. Relaxing the restriction on non-RVC as you did in your original revision is non-controversial. Applying a new restriction on floating point with RVC may require performance measurements to be done.

craig.topper: We discussed this at the RISC-V sync up this morning. I don't believe this should be part of…
pcwang-theadAuthorUnsubmitted
Done
ReplyInline Actions

Thanks. I will revert this patch to the original version and create another one for floating point registers after running SPEC FP (if it's profitable).

pcwang-thead: Thanks. I will revert this patch to the original version and create another one for floating…
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Code size numbers would be good too.

craig.topper: Code size numbers would be good too.
def F1_H : RISCVReg16<1, "f1", ["ft1"]>, DwarfRegNum<[33]>; def F1_H : RISCVReg16<1, "f1", ["ft1"]>, DwarfRegNum<[33]>;
def F2_H : RISCVReg16<2, "f2", ["ft2"]>, DwarfRegNum<[34]>; def F2_H : RISCVReg16<2, "f2", ["ft2"]>, DwarfRegNum<[34]>;
def F3_H : RISCVReg16<3, "f3", ["ft3"]>, DwarfRegNum<[35]>; def F3_H : RISCVReg16<3, "f3", ["ft3"]>, DwarfRegNum<[35]>;
def F4_H : RISCVReg16<4, "f4", ["ft4"]>, DwarfRegNum<[36]>; def F4_H : RISCVReg16<4, "f4", ["ft4"]>, DwarfRegNum<[36]>;
def F5_H : RISCVReg16<5, "f5", ["ft5"]>, DwarfRegNum<[37]>; def F5_H : RISCVReg16<5, "f5", ["ft5"]>, DwarfRegNum<[37]>;
def F6_H : RISCVReg16<6, "f6", ["ft6"]>, DwarfRegNum<[38]>; def F6_H : RISCVReg16<6, "f6", ["ft6"]>, DwarfRegNum<[38]>;
def F7_H : RISCVReg16<7, "f7", ["ft7"]>, DwarfRegNum<[39]>; def F7_H : RISCVReg16<7, "f7", ["ft7"]>, DwarfRegNum<[39]>;
def F8_H : RISCVReg16<8, "f8", ["fs0"]>, DwarfRegNum<[40]>; def F8_H : RISCVReg16<8, "f8", ["fs0"]>, DwarfRegNum<[40]>;
▲ Show 20 Lines • Show All 379 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/add-before-shl.ll

Show First 20 Lines • Show All 157 Lines • ▼ Show 20 Lines; RV64C-NEXT: c.jr ra
ret i24 %2 ret i24 %2
} }
define i128 @add_wide_operand(i128 %a) nounwind { define i128 @add_wide_operand(i128 %a) nounwind {
; RV32I-LABEL: add_wide_operand: ; RV32I-LABEL: add_wide_operand:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: lw a3, 4(a1) ; RV32I-NEXT: lw a3, 4(a1)
; RV32I-NEXT: lw a6, 12(a1) ; RV32I-NEXT: lw a4, 12(a1)
; RV32I-NEXT: lw a1, 8(a1) ; RV32I-NEXT: lw a1, 8(a1)
; RV32I-NEXT: srli a5, a2, 29 ; RV32I-NEXT: srli a5, a2, 29
; RV32I-NEXT: slli a4, a3, 3 ; RV32I-NEXT: slli a6, a3, 3
; RV32I-NEXT: or a4, a4, a5 ; RV32I-NEXT: or a5, a6, a5
; RV32I-NEXT: srli a3, a3, 29 ; RV32I-NEXT: srli a3, a3, 29
; RV32I-NEXT: slli a5, a1, 3 ; RV32I-NEXT: slli a6, a1, 3
; RV32I-NEXT: or a3, a5, a3 ; RV32I-NEXT: or a3, a6, a3
; RV32I-NEXT: srli a1, a1, 29 ; RV32I-NEXT: srli a1, a1, 29
; RV32I-NEXT: slli a5, a6, 3 ; RV32I-NEXT: slli a4, a4, 3
; RV32I-NEXT: or a1, a5, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: slli a2, a2, 3 ; RV32I-NEXT: slli a2, a2, 3
; RV32I-NEXT: lui a5, 128 ; RV32I-NEXT: lui a4, 128
; RV32I-NEXT: add a1, a1, a5 ; RV32I-NEXT: add a1, a1, a4
; RV32I-NEXT: sw a2, 0(a0) ; RV32I-NEXT: sw a2, 0(a0)
; RV32I-NEXT: sw a3, 8(a0) ; RV32I-NEXT: sw a3, 8(a0)
; RV32I-NEXT: sw a4, 4(a0) ; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: sw a1, 12(a0) ; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: jalr zero, 0(ra) ; RV32I-NEXT: jalr zero, 0(ra)
; ;
; RV64I-LABEL: add_wide_operand: ; RV64I-LABEL: add_wide_operand:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a2, a0, 61 ; RV64I-NEXT: srli a2, a0, 61
; RV64I-NEXT: slli a1, a1, 3 ; RV64I-NEXT: slli a1, a1, 3
; RV64I-NEXT: or a1, a1, a2 ; RV64I-NEXT: or a1, a1, a2
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/addcarry.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RISCV32 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefix=RISCV32
; Test ADDCARRY node expansion on a target that does not currently support ADDCARRY. ; Test ADDCARRY node expansion on a target that does not currently support ADDCARRY.
; Signed fixed point multiplication eventually expands down to an ADDCARRY. ; Signed fixed point multiplication eventually expands down to an ADDCARRY.
declare i64 @llvm.smul.fix.i64 (i64, i64, i32) declare i64 @llvm.smul.fix.i64 (i64, i64, i32)
define i64 @addcarry(i64 %x, i64 %y) nounwind { define i64 @addcarry(i64 %x, i64 %y) nounwind {
; RISCV32-LABEL: addcarry: ; RISCV32-LABEL: addcarry:
; RISCV32: # %bb.0: ; RISCV32: # %bb.0:
; RISCV32-NEXT: mul a4, a0, a3 ; RISCV32-NEXT: mul a4, a0, a3
; RISCV32-NEXT: mulhu a7, a0, a2 ; RISCV32-NEXT: mulhu a5, a0, a2
; RISCV32-NEXT: add a4, a7, a4 ; RISCV32-NEXT: add a6, a5, a4
; RISCV32-NEXT: mul a5, a1, a2 ; RISCV32-NEXT: mul a4, a1, a2
; RISCV32-NEXT: add a6, a4, a5 ; RISCV32-NEXT: add a4, a6, a4
; RISCV32-NEXT: sltu t0, a6, a4 ; RISCV32-NEXT: sltu a7, a4, a6
; RISCV32-NEXT: sltu a4, a4, a7 ; RISCV32-NEXT: sltu a5, a6, a5
; RISCV32-NEXT: mulhu a5, a0, a3 ; RISCV32-NEXT: mulhu a6, a0, a3
; RISCV32-NEXT: add a4, a5, a4 ; RISCV32-NEXT: add a5, a6, a5
; RISCV32-NEXT: mulhu a5, a1, a2 ; RISCV32-NEXT: mulhu a6, a1, a2
; RISCV32-NEXT: add a4, a4, a5 ; RISCV32-NEXT: add a5, a5, a6
; RISCV32-NEXT: add a4, a4, t0 ; RISCV32-NEXT: add a5, a5, a7
; RISCV32-NEXT: mul a5, a1, a3 ; RISCV32-NEXT: mul a6, a1, a3
; RISCV32-NEXT: add a5, a4, a5 ; RISCV32-NEXT: add a5, a5, a6
; RISCV32-NEXT: bgez a1, .LBB0_2 ; RISCV32-NEXT: bgez a1, .LBB0_2
; RISCV32-NEXT: # %bb.1: ; RISCV32-NEXT: # %bb.1:
; RISCV32-NEXT: sub a5, a5, a2 ; RISCV32-NEXT: sub a5, a5, a2
; RISCV32-NEXT: .LBB0_2: ; RISCV32-NEXT: .LBB0_2:
; RISCV32-NEXT: bgez a3, .LBB0_4 ; RISCV32-NEXT: bgez a3, .LBB0_4
; RISCV32-NEXT: # %bb.3: ; RISCV32-NEXT: # %bb.3:
; RISCV32-NEXT: sub a5, a5, a0 ; RISCV32-NEXT: sub a5, a5, a0
; RISCV32-NEXT: .LBB0_4: ; RISCV32-NEXT: .LBB0_4:
; RISCV32-NEXT: slli a1, a5, 30 ; RISCV32-NEXT: slli a1, a5, 30
; RISCV32-NEXT: srli a3, a6, 2 ; RISCV32-NEXT: srli a3, a4, 2
; RISCV32-NEXT: or a1, a1, a3 ; RISCV32-NEXT: or a1, a1, a3
; RISCV32-NEXT: slli a3, a6, 30 ; RISCV32-NEXT: slli a3, a4, 30
; RISCV32-NEXT: mul a0, a0, a2 ; RISCV32-NEXT: mul a0, a0, a2
; RISCV32-NEXT: srli a0, a0, 2 ; RISCV32-NEXT: srli a0, a0, 2
; RISCV32-NEXT: or a0, a3, a0 ; RISCV32-NEXT: or a0, a3, a0
; RISCV32-NEXT: ret ; RISCV32-NEXT: ret
%tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2); %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2);
ret i64 %tmp; ret i64 %tmp;
} }

llvm/test/CodeGen/RISCV/atomic-rmw.ll

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; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s2, a0, 24
; RV32I-NEXT: j .LBB35_2 ; RV32I-NEXT: j .LBB35_2
; RV32I-NEXT: .LBB35_1: # %atomicrmw.start ; RV32I-NEXT: .LBB35_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB35_4 ; RV32I-NEXT: bnez a0, .LBB35_4
; RV32I-NEXT: .LBB35_2: # %atomicrmw.start ; RV32I-NEXT: .LBB35_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB35_1 ; RV32I-NEXT: blt s2, a0, .LBB35_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB35_1 ; RV32I-NEXT: j .LBB35_1
; RV32I-NEXT: .LBB35_4: # %atomicrmw.end ; RV32I-NEXT: .LBB35_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_monotonic: ; RV32IA-LABEL: atomicrmw_max_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: li a4, 255 ; RV32IA-NEXT: li a4, 255
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 24 ; RV32IA-NEXT: li a5, 24
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a6) ; RV32IA-NEXT: lr.w a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a4, a1, .LBB35_3 ; RV32IA-NEXT: bge a7, a1, .LBB35_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB35_3: # in Loop: Header=BB35_1 Depth=1 ; RV32IA-NEXT: .LBB35_3: # in Loop: Header=BB35_1 Depth=1
; RV32IA-NEXT: sc.w a2, a2, (a6) ; RV32IA-NEXT: sc.w a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB35_1 ; RV32IA-NEXT: bnez a6, .LBB35_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_monotonic: ; RV64I-LABEL: atomicrmw_max_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s2, a0, 56
; RV64I-NEXT: j .LBB35_2 ; RV64I-NEXT: j .LBB35_2
; RV64I-NEXT: .LBB35_1: # %atomicrmw.start ; RV64I-NEXT: .LBB35_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB35_4 ; RV64I-NEXT: bnez a0, .LBB35_4
; RV64I-NEXT: .LBB35_2: # %atomicrmw.start ; RV64I-NEXT: .LBB35_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB35_1 ; RV64I-NEXT: blt s2, a0, .LBB35_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB35_1 ; RV64I-NEXT: j .LBB35_1
; RV64I-NEXT: .LBB35_4: # %atomicrmw.end ; RV64I-NEXT: .LBB35_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_monotonic: ; RV64IA-LABEL: atomicrmw_max_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255 ; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 56 ; RV64IA-NEXT: li a5, 56
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB35_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6) ; RV64IA-NEXT: lr.w a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a4, a1, .LBB35_3 ; RV64IA-NEXT: bge a7, a1, .LBB35_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB35_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB35_3: # in Loop: Header=BB35_1 Depth=1 ; RV64IA-NEXT: .LBB35_3: # in Loop: Header=BB35_1 Depth=1
; RV64IA-NEXT: sc.w a2, a2, (a6) ; RV64IA-NEXT: sc.w a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB35_1 ; RV64IA-NEXT: bnez a6, .LBB35_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b monotonic %1 = atomicrmw max i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_acquire: ; RV32I-LABEL: atomicrmw_max_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s2, a0, 24
; RV32I-NEXT: j .LBB36_2 ; RV32I-NEXT: j .LBB36_2
; RV32I-NEXT: .LBB36_1: # %atomicrmw.start ; RV32I-NEXT: .LBB36_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB36_4 ; RV32I-NEXT: bnez a0, .LBB36_4
; RV32I-NEXT: .LBB36_2: # %atomicrmw.start ; RV32I-NEXT: .LBB36_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB36_1 ; RV32I-NEXT: blt s2, a0, .LBB36_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB36_1 ; RV32I-NEXT: j .LBB36_1
; RV32I-NEXT: .LBB36_4: # %atomicrmw.end ; RV32I-NEXT: .LBB36_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_acquire: ; RV32IA-LABEL: atomicrmw_max_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: li a4, 255 ; RV32IA-NEXT: li a4, 255
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 24 ; RV32IA-NEXT: li a5, 24
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a6) ; RV32IA-NEXT: lr.w.aq a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a4, a1, .LBB36_3 ; RV32IA-NEXT: bge a7, a1, .LBB36_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB36_3: # in Loop: Header=BB36_1 Depth=1 ; RV32IA-NEXT: .LBB36_3: # in Loop: Header=BB36_1 Depth=1
; RV32IA-NEXT: sc.w a2, a2, (a6) ; RV32IA-NEXT: sc.w a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB36_1 ; RV32IA-NEXT: bnez a6, .LBB36_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_acquire: ; RV64I-LABEL: atomicrmw_max_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s2, a0, 56
; RV64I-NEXT: j .LBB36_2 ; RV64I-NEXT: j .LBB36_2
; RV64I-NEXT: .LBB36_1: # %atomicrmw.start ; RV64I-NEXT: .LBB36_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB36_4 ; RV64I-NEXT: bnez a0, .LBB36_4
; RV64I-NEXT: .LBB36_2: # %atomicrmw.start ; RV64I-NEXT: .LBB36_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB36_1 ; RV64I-NEXT: blt s2, a0, .LBB36_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB36_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB36_1 ; RV64I-NEXT: j .LBB36_1
; RV64I-NEXT: .LBB36_4: # %atomicrmw.end ; RV64I-NEXT: .LBB36_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_acquire: ; RV64IA-LABEL: atomicrmw_max_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255 ; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 56 ; RV64IA-NEXT: li a5, 56
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6) ; RV64IA-NEXT: lr.w.aq a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a4, a1, .LBB36_3 ; RV64IA-NEXT: bge a7, a1, .LBB36_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB36_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB36_3: # in Loop: Header=BB36_1 Depth=1 ; RV64IA-NEXT: .LBB36_3: # in Loop: Header=BB36_1 Depth=1
; RV64IA-NEXT: sc.w a2, a2, (a6) ; RV64IA-NEXT: sc.w a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB36_1 ; RV64IA-NEXT: bnez a6, .LBB36_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b acquire %1 = atomicrmw max i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_release: ; RV32I-LABEL: atomicrmw_max_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s2, a0, 24
; RV32I-NEXT: j .LBB37_2 ; RV32I-NEXT: j .LBB37_2
; RV32I-NEXT: .LBB37_1: # %atomicrmw.start ; RV32I-NEXT: .LBB37_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a3, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB37_4 ; RV32I-NEXT: bnez a0, .LBB37_4
; RV32I-NEXT: .LBB37_2: # %atomicrmw.start ; RV32I-NEXT: .LBB37_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB37_1 ; RV32I-NEXT: blt s2, a0, .LBB37_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB37_1 ; RV32I-NEXT: j .LBB37_1
; RV32I-NEXT: .LBB37_4: # %atomicrmw.end ; RV32I-NEXT: .LBB37_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_release: ; RV32IA-LABEL: atomicrmw_max_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: li a4, 255 ; RV32IA-NEXT: li a4, 255
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 24 ; RV32IA-NEXT: li a5, 24
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a6) ; RV32IA-NEXT: lr.w a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a4, a1, .LBB37_3 ; RV32IA-NEXT: bge a7, a1, .LBB37_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB37_3: # in Loop: Header=BB37_1 Depth=1 ; RV32IA-NEXT: .LBB37_3: # in Loop: Header=BB37_1 Depth=1
; RV32IA-NEXT: sc.w.rl a2, a2, (a6) ; RV32IA-NEXT: sc.w.rl a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB37_1 ; RV32IA-NEXT: bnez a6, .LBB37_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_release: ; RV64I-LABEL: atomicrmw_max_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s2, a0, 56
; RV64I-NEXT: j .LBB37_2 ; RV64I-NEXT: j .LBB37_2
; RV64I-NEXT: .LBB37_1: # %atomicrmw.start ; RV64I-NEXT: .LBB37_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB37_4 ; RV64I-NEXT: bnez a0, .LBB37_4
; RV64I-NEXT: .LBB37_2: # %atomicrmw.start ; RV64I-NEXT: .LBB37_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB37_1 ; RV64I-NEXT: blt s2, a0, .LBB37_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB37_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB37_1 ; RV64I-NEXT: j .LBB37_1
; RV64I-NEXT: .LBB37_4: # %atomicrmw.end ; RV64I-NEXT: .LBB37_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_release: ; RV64IA-LABEL: atomicrmw_max_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255 ; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 56 ; RV64IA-NEXT: li a5, 56
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6) ; RV64IA-NEXT: lr.w a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a4, a1, .LBB37_3 ; RV64IA-NEXT: bge a7, a1, .LBB37_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB37_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB37_3: # in Loop: Header=BB37_1 Depth=1 ; RV64IA-NEXT: .LBB37_3: # in Loop: Header=BB37_1 Depth=1
; RV64IA-NEXT: sc.w.rl a2, a2, (a6) ; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB37_1 ; RV64IA-NEXT: bnez a6, .LBB37_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b release %1 = atomicrmw max i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_acq_rel: ; RV32I-LABEL: atomicrmw_max_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s2, a0, 24
; RV32I-NEXT: j .LBB38_2 ; RV32I-NEXT: j .LBB38_2
; RV32I-NEXT: .LBB38_1: # %atomicrmw.start ; RV32I-NEXT: .LBB38_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB38_4 ; RV32I-NEXT: bnez a0, .LBB38_4
; RV32I-NEXT: .LBB38_2: # %atomicrmw.start ; RV32I-NEXT: .LBB38_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB38_1 ; RV32I-NEXT: blt s2, a0, .LBB38_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB38_1 ; RV32I-NEXT: j .LBB38_1
; RV32I-NEXT: .LBB38_4: # %atomicrmw.end ; RV32I-NEXT: .LBB38_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_max_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: li a4, 255 ; RV32IA-NEXT: li a4, 255
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 24 ; RV32IA-NEXT: li a5, 24
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a6) ; RV32IA-NEXT: lr.w.aq a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a4, a1, .LBB38_3 ; RV32IA-NEXT: bge a7, a1, .LBB38_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB38_3: # in Loop: Header=BB38_1 Depth=1 ; RV32IA-NEXT: .LBB38_3: # in Loop: Header=BB38_1 Depth=1
; RV32IA-NEXT: sc.w.rl a2, a2, (a6) ; RV32IA-NEXT: sc.w.rl a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB38_1 ; RV32IA-NEXT: bnez a6, .LBB38_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_acq_rel: ; RV64I-LABEL: atomicrmw_max_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s2, a0, 56
; RV64I-NEXT: j .LBB38_2 ; RV64I-NEXT: j .LBB38_2
; RV64I-NEXT: .LBB38_1: # %atomicrmw.start ; RV64I-NEXT: .LBB38_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB38_4 ; RV64I-NEXT: bnez a0, .LBB38_4
; RV64I-NEXT: .LBB38_2: # %atomicrmw.start ; RV64I-NEXT: .LBB38_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB38_1 ; RV64I-NEXT: blt s2, a0, .LBB38_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB38_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB38_1 ; RV64I-NEXT: j .LBB38_1
; RV64I-NEXT: .LBB38_4: # %atomicrmw.end ; RV64I-NEXT: .LBB38_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_max_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255 ; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 56 ; RV64IA-NEXT: li a5, 56
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6) ; RV64IA-NEXT: lr.w.aq a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a4, a1, .LBB38_3 ; RV64IA-NEXT: bge a7, a1, .LBB38_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB38_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB38_3: # in Loop: Header=BB38_1 Depth=1 ; RV64IA-NEXT: .LBB38_3: # in Loop: Header=BB38_1 Depth=1
; RV64IA-NEXT: sc.w.rl a2, a2, (a6) ; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB38_1 ; RV64IA-NEXT: bnez a6, .LBB38_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b acq_rel %1 = atomicrmw max i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_seq_cst: ; RV32I-LABEL: atomicrmw_max_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s2, a0, 24
; RV32I-NEXT: j .LBB39_2 ; RV32I-NEXT: j .LBB39_2
; RV32I-NEXT: .LBB39_1: # %atomicrmw.start ; RV32I-NEXT: .LBB39_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a4, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB39_4 ; RV32I-NEXT: bnez a0, .LBB39_4
; RV32I-NEXT: .LBB39_2: # %atomicrmw.start ; RV32I-NEXT: .LBB39_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB39_1 ; RV32I-NEXT: blt s2, a0, .LBB39_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB39_1 ; RV32I-NEXT: j .LBB39_1
; RV32I-NEXT: .LBB39_4: # %atomicrmw.end ; RV32I-NEXT: .LBB39_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_max_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: li a4, 255 ; RV32IA-NEXT: li a4, 255
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 24 ; RV32IA-NEXT: li a5, 24
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a5, (a6) ; RV32IA-NEXT: lr.w.aqrl a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a4, a1, .LBB39_3 ; RV32IA-NEXT: bge a7, a1, .LBB39_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB39_3: # in Loop: Header=BB39_1 Depth=1 ; RV32IA-NEXT: .LBB39_3: # in Loop: Header=BB39_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a2, a2, (a6) ; RV32IA-NEXT: sc.w.aqrl a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB39_1 ; RV32IA-NEXT: bnez a6, .LBB39_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_seq_cst: ; RV64I-LABEL: atomicrmw_max_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s2, a0, 56
; RV64I-NEXT: j .LBB39_2 ; RV64I-NEXT: j .LBB39_2
; RV64I-NEXT: .LBB39_1: # %atomicrmw.start ; RV64I-NEXT: .LBB39_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB39_4 ; RV64I-NEXT: bnez a0, .LBB39_4
; RV64I-NEXT: .LBB39_2: # %atomicrmw.start ; RV64I-NEXT: .LBB39_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB39_1 ; RV64I-NEXT: blt s2, a0, .LBB39_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB39_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB39_1 ; RV64I-NEXT: j .LBB39_1
; RV64I-NEXT: .LBB39_4: # %atomicrmw.end ; RV64I-NEXT: .LBB39_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_max_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255 ; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 56 ; RV64IA-NEXT: li a5, 56
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB39_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a6) ; RV64IA-NEXT: lr.w.aqrl a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a4, a1, .LBB39_3 ; RV64IA-NEXT: bge a7, a1, .LBB39_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB39_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB39_3: # in Loop: Header=BB39_1 Depth=1 ; RV64IA-NEXT: .LBB39_3: # in Loop: Header=BB39_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a2, a2, (a6) ; RV64IA-NEXT: sc.w.aqrl a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB39_1 ; RV64IA-NEXT: bnez a6, .LBB39_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b seq_cst %1 = atomicrmw max i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_monotonic: ; RV32I-LABEL: atomicrmw_min_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s2, a0, 24
; RV32I-NEXT: j .LBB40_2 ; RV32I-NEXT: j .LBB40_2
; RV32I-NEXT: .LBB40_1: # %atomicrmw.start ; RV32I-NEXT: .LBB40_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB40_4 ; RV32I-NEXT: bnez a0, .LBB40_4
; RV32I-NEXT: .LBB40_2: # %atomicrmw.start ; RV32I-NEXT: .LBB40_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB40_1 ; RV32I-NEXT: bge s2, a0, .LBB40_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB40_1 ; RV32I-NEXT: j .LBB40_1
; RV32I-NEXT: .LBB40_4: # %atomicrmw.end ; RV32I-NEXT: .LBB40_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_monotonic: ; RV32IA-LABEL: atomicrmw_min_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: li a4, 255 ; RV32IA-NEXT: li a4, 255
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 24 ; RV32IA-NEXT: li a5, 24
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a6) ; RV32IA-NEXT: lr.w a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a1, a4, .LBB40_3 ; RV32IA-NEXT: bge a1, a7, .LBB40_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB40_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB40_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB40_3: # in Loop: Header=BB40_1 Depth=1 ; RV32IA-NEXT: .LBB40_3: # in Loop: Header=BB40_1 Depth=1
; RV32IA-NEXT: sc.w a2, a2, (a6) ; RV32IA-NEXT: sc.w a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB40_1 ; RV32IA-NEXT: bnez a6, .LBB40_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_monotonic: ; RV64I-LABEL: atomicrmw_min_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s2, a0, 56
; RV64I-NEXT: j .LBB40_2 ; RV64I-NEXT: j .LBB40_2
; RV64I-NEXT: .LBB40_1: # %atomicrmw.start ; RV64I-NEXT: .LBB40_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB40_4 ; RV64I-NEXT: bnez a0, .LBB40_4
; RV64I-NEXT: .LBB40_2: # %atomicrmw.start ; RV64I-NEXT: .LBB40_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB40_1 ; RV64I-NEXT: bge s2, a0, .LBB40_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB40_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB40_1 ; RV64I-NEXT: j .LBB40_1
; RV64I-NEXT: .LBB40_4: # %atomicrmw.end ; RV64I-NEXT: .LBB40_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_monotonic: ; RV64IA-LABEL: atomicrmw_min_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255 ; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 56 ; RV64IA-NEXT: li a5, 56
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6) ; RV64IA-NEXT: lr.w a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a1, a4, .LBB40_3 ; RV64IA-NEXT: bge a1, a7, .LBB40_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB40_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB40_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB40_3: # in Loop: Header=BB40_1 Depth=1 ; RV64IA-NEXT: .LBB40_3: # in Loop: Header=BB40_1 Depth=1
; RV64IA-NEXT: sc.w a2, a2, (a6) ; RV64IA-NEXT: sc.w a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB40_1 ; RV64IA-NEXT: bnez a6, .LBB40_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b monotonic %1 = atomicrmw min i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_acquire: ; RV32I-LABEL: atomicrmw_min_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s2, a0, 24
; RV32I-NEXT: j .LBB41_2 ; RV32I-NEXT: j .LBB41_2
; RV32I-NEXT: .LBB41_1: # %atomicrmw.start ; RV32I-NEXT: .LBB41_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB41_4 ; RV32I-NEXT: bnez a0, .LBB41_4
; RV32I-NEXT: .LBB41_2: # %atomicrmw.start ; RV32I-NEXT: .LBB41_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB41_1 ; RV32I-NEXT: bge s2, a0, .LBB41_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB41_1 ; RV32I-NEXT: j .LBB41_1
; RV32I-NEXT: .LBB41_4: # %atomicrmw.end ; RV32I-NEXT: .LBB41_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_acquire: ; RV32IA-LABEL: atomicrmw_min_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: li a4, 255 ; RV32IA-NEXT: li a4, 255
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 24 ; RV32IA-NEXT: li a5, 24
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a6) ; RV32IA-NEXT: lr.w.aq a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a1, a4, .LBB41_3 ; RV32IA-NEXT: bge a1, a7, .LBB41_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB41_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB41_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB41_3: # in Loop: Header=BB41_1 Depth=1 ; RV32IA-NEXT: .LBB41_3: # in Loop: Header=BB41_1 Depth=1
; RV32IA-NEXT: sc.w a2, a2, (a6) ; RV32IA-NEXT: sc.w a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB41_1 ; RV32IA-NEXT: bnez a6, .LBB41_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_acquire: ; RV64I-LABEL: atomicrmw_min_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s2, a0, 56
; RV64I-NEXT: j .LBB41_2 ; RV64I-NEXT: j .LBB41_2
; RV64I-NEXT: .LBB41_1: # %atomicrmw.start ; RV64I-NEXT: .LBB41_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB41_4 ; RV64I-NEXT: bnez a0, .LBB41_4
; RV64I-NEXT: .LBB41_2: # %atomicrmw.start ; RV64I-NEXT: .LBB41_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB41_1 ; RV64I-NEXT: bge s2, a0, .LBB41_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB41_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB41_1 ; RV64I-NEXT: j .LBB41_1
; RV64I-NEXT: .LBB41_4: # %atomicrmw.end ; RV64I-NEXT: .LBB41_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_acquire: ; RV64IA-LABEL: atomicrmw_min_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255 ; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 56 ; RV64IA-NEXT: li a5, 56
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6) ; RV64IA-NEXT: lr.w.aq a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a1, a4, .LBB41_3 ; RV64IA-NEXT: bge a1, a7, .LBB41_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB41_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB41_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB41_3: # in Loop: Header=BB41_1 Depth=1 ; RV64IA-NEXT: .LBB41_3: # in Loop: Header=BB41_1 Depth=1
; RV64IA-NEXT: sc.w a2, a2, (a6) ; RV64IA-NEXT: sc.w a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB41_1 ; RV64IA-NEXT: bnez a6, .LBB41_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b acquire %1 = atomicrmw min i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_release: ; RV32I-LABEL: atomicrmw_min_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s2, a0, 24
; RV32I-NEXT: j .LBB42_2 ; RV32I-NEXT: j .LBB42_2
; RV32I-NEXT: .LBB42_1: # %atomicrmw.start ; RV32I-NEXT: .LBB42_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a3, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB42_4 ; RV32I-NEXT: bnez a0, .LBB42_4
; RV32I-NEXT: .LBB42_2: # %atomicrmw.start ; RV32I-NEXT: .LBB42_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB42_1 ; RV32I-NEXT: bge s2, a0, .LBB42_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB42_1 ; RV32I-NEXT: j .LBB42_1
; RV32I-NEXT: .LBB42_4: # %atomicrmw.end ; RV32I-NEXT: .LBB42_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_release: ; RV32IA-LABEL: atomicrmw_min_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: li a4, 255 ; RV32IA-NEXT: li a4, 255
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 24 ; RV32IA-NEXT: li a5, 24
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a6) ; RV32IA-NEXT: lr.w a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a1, a4, .LBB42_3 ; RV32IA-NEXT: bge a1, a7, .LBB42_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB42_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB42_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB42_3: # in Loop: Header=BB42_1 Depth=1 ; RV32IA-NEXT: .LBB42_3: # in Loop: Header=BB42_1 Depth=1
; RV32IA-NEXT: sc.w.rl a2, a2, (a6) ; RV32IA-NEXT: sc.w.rl a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB42_1 ; RV32IA-NEXT: bnez a6, .LBB42_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_release: ; RV64I-LABEL: atomicrmw_min_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s2, a0, 56
; RV64I-NEXT: j .LBB42_2 ; RV64I-NEXT: j .LBB42_2
; RV64I-NEXT: .LBB42_1: # %atomicrmw.start ; RV64I-NEXT: .LBB42_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB42_4 ; RV64I-NEXT: bnez a0, .LBB42_4
; RV64I-NEXT: .LBB42_2: # %atomicrmw.start ; RV64I-NEXT: .LBB42_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB42_1 ; RV64I-NEXT: bge s2, a0, .LBB42_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB42_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB42_1 ; RV64I-NEXT: j .LBB42_1
; RV64I-NEXT: .LBB42_4: # %atomicrmw.end ; RV64I-NEXT: .LBB42_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_release: ; RV64IA-LABEL: atomicrmw_min_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255 ; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 56 ; RV64IA-NEXT: li a5, 56
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6) ; RV64IA-NEXT: lr.w a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a1, a4, .LBB42_3 ; RV64IA-NEXT: bge a1, a7, .LBB42_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB42_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB42_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB42_3: # in Loop: Header=BB42_1 Depth=1 ; RV64IA-NEXT: .LBB42_3: # in Loop: Header=BB42_1 Depth=1
; RV64IA-NEXT: sc.w.rl a2, a2, (a6) ; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB42_1 ; RV64IA-NEXT: bnez a6, .LBB42_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b release %1 = atomicrmw min i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_acq_rel: ; RV32I-LABEL: atomicrmw_min_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s2, a0, 24
; RV32I-NEXT: j .LBB43_2 ; RV32I-NEXT: j .LBB43_2
; RV32I-NEXT: .LBB43_1: # %atomicrmw.start ; RV32I-NEXT: .LBB43_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB43_4 ; RV32I-NEXT: bnez a0, .LBB43_4
; RV32I-NEXT: .LBB43_2: # %atomicrmw.start ; RV32I-NEXT: .LBB43_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB43_1 ; RV32I-NEXT: bge s2, a0, .LBB43_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB43_1 ; RV32I-NEXT: j .LBB43_1
; RV32I-NEXT: .LBB43_4: # %atomicrmw.end ; RV32I-NEXT: .LBB43_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_min_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: li a4, 255 ; RV32IA-NEXT: li a4, 255
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 24 ; RV32IA-NEXT: li a5, 24
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a6) ; RV32IA-NEXT: lr.w.aq a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a1, a4, .LBB43_3 ; RV32IA-NEXT: bge a1, a7, .LBB43_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB43_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB43_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB43_3: # in Loop: Header=BB43_1 Depth=1 ; RV32IA-NEXT: .LBB43_3: # in Loop: Header=BB43_1 Depth=1
; RV32IA-NEXT: sc.w.rl a2, a2, (a6) ; RV32IA-NEXT: sc.w.rl a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB43_1 ; RV32IA-NEXT: bnez a6, .LBB43_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_acq_rel: ; RV64I-LABEL: atomicrmw_min_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s2, a0, 56
; RV64I-NEXT: j .LBB43_2 ; RV64I-NEXT: j .LBB43_2
; RV64I-NEXT: .LBB43_1: # %atomicrmw.start ; RV64I-NEXT: .LBB43_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB43_4 ; RV64I-NEXT: bnez a0, .LBB43_4
; RV64I-NEXT: .LBB43_2: # %atomicrmw.start ; RV64I-NEXT: .LBB43_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB43_1 ; RV64I-NEXT: bge s2, a0, .LBB43_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB43_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB43_1 ; RV64I-NEXT: j .LBB43_1
; RV64I-NEXT: .LBB43_4: # %atomicrmw.end ; RV64I-NEXT: .LBB43_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_min_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255 ; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 56 ; RV64IA-NEXT: li a5, 56
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6) ; RV64IA-NEXT: lr.w.aq a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a1, a4, .LBB43_3 ; RV64IA-NEXT: bge a1, a7, .LBB43_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB43_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB43_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB43_3: # in Loop: Header=BB43_1 Depth=1 ; RV64IA-NEXT: .LBB43_3: # in Loop: Header=BB43_1 Depth=1
; RV64IA-NEXT: sc.w.rl a2, a2, (a6) ; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB43_1 ; RV64IA-NEXT: bnez a6, .LBB43_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b acq_rel %1 = atomicrmw min i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_seq_cst: ; RV32I-LABEL: atomicrmw_min_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s2, a0, 24
; RV32I-NEXT: j .LBB44_2 ; RV32I-NEXT: j .LBB44_2
; RV32I-NEXT: .LBB44_1: # %atomicrmw.start ; RV32I-NEXT: .LBB44_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a4, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB44_4 ; RV32I-NEXT: bnez a0, .LBB44_4
; RV32I-NEXT: .LBB44_2: # %atomicrmw.start ; RV32I-NEXT: .LBB44_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB44_1 ; RV32I-NEXT: bge s2, a0, .LBB44_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB44_1 ; RV32I-NEXT: j .LBB44_1
; RV32I-NEXT: .LBB44_4: # %atomicrmw.end ; RV32I-NEXT: .LBB44_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_min_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: li a4, 255 ; RV32IA-NEXT: li a4, 255
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 24 ; RV32IA-NEXT: li a5, 24
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a5, (a6) ; RV32IA-NEXT: lr.w.aqrl a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a1, a4, .LBB44_3 ; RV32IA-NEXT: bge a1, a7, .LBB44_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1 ; RV32IA-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a2, a2, (a6) ; RV32IA-NEXT: sc.w.aqrl a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB44_1 ; RV32IA-NEXT: bnez a6, .LBB44_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_seq_cst: ; RV64I-LABEL: atomicrmw_min_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s2, a0, 56
; RV64I-NEXT: j .LBB44_2 ; RV64I-NEXT: j .LBB44_2
; RV64I-NEXT: .LBB44_1: # %atomicrmw.start ; RV64I-NEXT: .LBB44_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB44_4 ; RV64I-NEXT: bnez a0, .LBB44_4
; RV64I-NEXT: .LBB44_2: # %atomicrmw.start ; RV64I-NEXT: .LBB44_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB44_1 ; RV64I-NEXT: bge s2, a0, .LBB44_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB44_1 ; RV64I-NEXT: j .LBB44_1
; RV64I-NEXT: .LBB44_4: # %atomicrmw.end ; RV64I-NEXT: .LBB44_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_min_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255 ; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 56 ; RV64IA-NEXT: li a5, 56
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a6) ; RV64IA-NEXT: lr.w.aqrl a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a1, a4, .LBB44_3 ; RV64IA-NEXT: bge a1, a7, .LBB44_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB44_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1 ; RV64IA-NEXT: .LBB44_3: # in Loop: Header=BB44_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a2, a2, (a6) ; RV64IA-NEXT: sc.w.aqrl a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB44_1 ; RV64IA-NEXT: bnez a6, .LBB44_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b seq_cst %1 = atomicrmw min i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_monotonic: ; RV32I-LABEL: atomicrmw_umax_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s2, a1, 255
; RV32I-NEXT: j .LBB45_2 ; RV32I-NEXT: j .LBB45_2
; RV32I-NEXT: .LBB45_1: # %atomicrmw.start ; RV32I-NEXT: .LBB45_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB45_4 ; RV32I-NEXT: bnez a0, .LBB45_4
; RV32I-NEXT: .LBB45_2: # %atomicrmw.start ; RV32I-NEXT: .LBB45_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB45_1 ; RV32I-NEXT: bltu s2, a0, .LBB45_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB45_1 ; RV32I-NEXT: j .LBB45_1
; RV32I-NEXT: .LBB45_4: # %atomicrmw.end ; RV32I-NEXT: .LBB45_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_monotonic: ; RV32IA-LABEL: atomicrmw_umax_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: li a3, 255 ; RV32IA-NEXT: li a3, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a6) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: and a2, a4, a3 ; RV32IA-NEXT: and a6, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a2, a1, .LBB45_3 ; RV32IA-NEXT: bgeu a6, a1, .LBB45_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1 ; RV32IA-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a6) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB45_1 ; RV32IA-NEXT: bnez a5, .LBB45_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_monotonic: ; RV64I-LABEL: atomicrmw_umax_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s2, a1, 255
; RV64I-NEXT: j .LBB45_2 ; RV64I-NEXT: j .LBB45_2
; RV64I-NEXT: .LBB45_1: # %atomicrmw.start ; RV64I-NEXT: .LBB45_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB45_4 ; RV64I-NEXT: bnez a0, .LBB45_4
; RV64I-NEXT: .LBB45_2: # %atomicrmw.start ; RV64I-NEXT: .LBB45_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB45_1 ; RV64I-NEXT: bltu s2, a0, .LBB45_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB45_1 ; RV64I-NEXT: j .LBB45_1
; RV64I-NEXT: .LBB45_4: # %atomicrmw.end ; RV64I-NEXT: .LBB45_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_monotonic: ; RV64IA-LABEL: atomicrmw_umax_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: li a3, 255 ; RV64IA-NEXT: li a3, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a6) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: and a2, a4, a3 ; RV64IA-NEXT: and a6, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a2, a1, .LBB45_3 ; RV64IA-NEXT: bgeu a6, a1, .LBB45_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB45_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1 ; RV64IA-NEXT: .LBB45_3: # in Loop: Header=BB45_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a6) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB45_1 ; RV64IA-NEXT: bnez a5, .LBB45_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b monotonic %1 = atomicrmw umax i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_acquire: ; RV32I-LABEL: atomicrmw_umax_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s2, a1, 255
; RV32I-NEXT: j .LBB46_2 ; RV32I-NEXT: j .LBB46_2
; RV32I-NEXT: .LBB46_1: # %atomicrmw.start ; RV32I-NEXT: .LBB46_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB46_4 ; RV32I-NEXT: bnez a0, .LBB46_4
; RV32I-NEXT: .LBB46_2: # %atomicrmw.start ; RV32I-NEXT: .LBB46_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB46_1 ; RV32I-NEXT: bltu s2, a0, .LBB46_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB46_1 ; RV32I-NEXT: j .LBB46_1
; RV32I-NEXT: .LBB46_4: # %atomicrmw.end ; RV32I-NEXT: .LBB46_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_acquire: ; RV32IA-LABEL: atomicrmw_umax_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: li a3, 255 ; RV32IA-NEXT: li a3, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a6) ; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: and a2, a4, a3 ; RV32IA-NEXT: and a6, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a2, a1, .LBB46_3 ; RV32IA-NEXT: bgeu a6, a1, .LBB46_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1 ; RV32IA-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a6) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB46_1 ; RV32IA-NEXT: bnez a5, .LBB46_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_acquire: ; RV64I-LABEL: atomicrmw_umax_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s2, a1, 255
; RV64I-NEXT: j .LBB46_2 ; RV64I-NEXT: j .LBB46_2
; RV64I-NEXT: .LBB46_1: # %atomicrmw.start ; RV64I-NEXT: .LBB46_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB46_4 ; RV64I-NEXT: bnez a0, .LBB46_4
; RV64I-NEXT: .LBB46_2: # %atomicrmw.start ; RV64I-NEXT: .LBB46_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB46_1 ; RV64I-NEXT: bltu s2, a0, .LBB46_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB46_1 ; RV64I-NEXT: j .LBB46_1
; RV64I-NEXT: .LBB46_4: # %atomicrmw.end ; RV64I-NEXT: .LBB46_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_acquire: ; RV64IA-LABEL: atomicrmw_umax_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: li a3, 255 ; RV64IA-NEXT: li a3, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a6) ; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: and a2, a4, a3 ; RV64IA-NEXT: and a6, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a2, a1, .LBB46_3 ; RV64IA-NEXT: bgeu a6, a1, .LBB46_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB46_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1 ; RV64IA-NEXT: .LBB46_3: # in Loop: Header=BB46_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a6) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB46_1 ; RV64IA-NEXT: bnez a5, .LBB46_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b acquire %1 = atomicrmw umax i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_release: ; RV32I-LABEL: atomicrmw_umax_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s2, a1, 255
; RV32I-NEXT: j .LBB47_2 ; RV32I-NEXT: j .LBB47_2
; RV32I-NEXT: .LBB47_1: # %atomicrmw.start ; RV32I-NEXT: .LBB47_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a3, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB47_4 ; RV32I-NEXT: bnez a0, .LBB47_4
; RV32I-NEXT: .LBB47_2: # %atomicrmw.start ; RV32I-NEXT: .LBB47_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB47_1 ; RV32I-NEXT: bltu s2, a0, .LBB47_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB47_1 ; RV32I-NEXT: j .LBB47_1
; RV32I-NEXT: .LBB47_4: # %atomicrmw.end ; RV32I-NEXT: .LBB47_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_release: ; RV32IA-LABEL: atomicrmw_umax_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: li a3, 255 ; RV32IA-NEXT: li a3, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a6) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: and a2, a4, a3 ; RV32IA-NEXT: and a6, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a2, a1, .LBB47_3 ; RV32IA-NEXT: bgeu a6, a1, .LBB47_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1 ; RV32IA-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a6) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB47_1 ; RV32IA-NEXT: bnez a5, .LBB47_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_release: ; RV64I-LABEL: atomicrmw_umax_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s2, a1, 255
; RV64I-NEXT: j .LBB47_2 ; RV64I-NEXT: j .LBB47_2
; RV64I-NEXT: .LBB47_1: # %atomicrmw.start ; RV64I-NEXT: .LBB47_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB47_4 ; RV64I-NEXT: bnez a0, .LBB47_4
; RV64I-NEXT: .LBB47_2: # %atomicrmw.start ; RV64I-NEXT: .LBB47_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB47_1 ; RV64I-NEXT: bltu s2, a0, .LBB47_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB47_1 ; RV64I-NEXT: j .LBB47_1
; RV64I-NEXT: .LBB47_4: # %atomicrmw.end ; RV64I-NEXT: .LBB47_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_release: ; RV64IA-LABEL: atomicrmw_umax_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: li a3, 255 ; RV64IA-NEXT: li a3, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB47_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a6) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: and a2, a4, a3 ; RV64IA-NEXT: and a6, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a2, a1, .LBB47_3 ; RV64IA-NEXT: bgeu a6, a1, .LBB47_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB47_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1 ; RV64IA-NEXT: .LBB47_3: # in Loop: Header=BB47_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a6) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB47_1 ; RV64IA-NEXT: bnez a5, .LBB47_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b release %1 = atomicrmw umax i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_acq_rel: ; RV32I-LABEL: atomicrmw_umax_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s2, a1, 255
; RV32I-NEXT: j .LBB48_2 ; RV32I-NEXT: j .LBB48_2
; RV32I-NEXT: .LBB48_1: # %atomicrmw.start ; RV32I-NEXT: .LBB48_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB48_4 ; RV32I-NEXT: bnez a0, .LBB48_4
; RV32I-NEXT: .LBB48_2: # %atomicrmw.start ; RV32I-NEXT: .LBB48_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB48_1 ; RV32I-NEXT: bltu s2, a0, .LBB48_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB48_1 ; RV32I-NEXT: j .LBB48_1
; RV32I-NEXT: .LBB48_4: # %atomicrmw.end ; RV32I-NEXT: .LBB48_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_umax_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: li a3, 255 ; RV32IA-NEXT: li a3, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a6) ; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: and a2, a4, a3 ; RV32IA-NEXT: and a6, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a2, a1, .LBB48_3 ; RV32IA-NEXT: bgeu a6, a1, .LBB48_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1 ; RV32IA-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a6) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB48_1 ; RV32IA-NEXT: bnez a5, .LBB48_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_acq_rel: ; RV64I-LABEL: atomicrmw_umax_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s2, a1, 255
; RV64I-NEXT: j .LBB48_2 ; RV64I-NEXT: j .LBB48_2
; RV64I-NEXT: .LBB48_1: # %atomicrmw.start ; RV64I-NEXT: .LBB48_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB48_4 ; RV64I-NEXT: bnez a0, .LBB48_4
; RV64I-NEXT: .LBB48_2: # %atomicrmw.start ; RV64I-NEXT: .LBB48_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB48_1 ; RV64I-NEXT: bltu s2, a0, .LBB48_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB48_1 ; RV64I-NEXT: j .LBB48_1
; RV64I-NEXT: .LBB48_4: # %atomicrmw.end ; RV64I-NEXT: .LBB48_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_umax_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: li a3, 255 ; RV64IA-NEXT: li a3, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a6) ; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: and a2, a4, a3 ; RV64IA-NEXT: and a6, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a2, a1, .LBB48_3 ; RV64IA-NEXT: bgeu a6, a1, .LBB48_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB48_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1 ; RV64IA-NEXT: .LBB48_3: # in Loop: Header=BB48_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a6) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB48_1 ; RV64IA-NEXT: bnez a5, .LBB48_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b acq_rel %1 = atomicrmw umax i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_seq_cst: ; RV32I-LABEL: atomicrmw_umax_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s2, a1, 255
; RV32I-NEXT: j .LBB49_2 ; RV32I-NEXT: j .LBB49_2
; RV32I-NEXT: .LBB49_1: # %atomicrmw.start ; RV32I-NEXT: .LBB49_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a4, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB49_4 ; RV32I-NEXT: bnez a0, .LBB49_4
; RV32I-NEXT: .LBB49_2: # %atomicrmw.start ; RV32I-NEXT: .LBB49_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB49_1 ; RV32I-NEXT: bltu s2, a0, .LBB49_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB49_1 ; RV32I-NEXT: j .LBB49_1
; RV32I-NEXT: .LBB49_4: # %atomicrmw.end ; RV32I-NEXT: .LBB49_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_umax_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: li a3, 255 ; RV32IA-NEXT: li a3, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a6) ; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: and a2, a4, a3 ; RV32IA-NEXT: and a6, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a2, a1, .LBB49_3 ; RV32IA-NEXT: bgeu a6, a1, .LBB49_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1 ; RV32IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a6) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB49_1 ; RV32IA-NEXT: bnez a5, .LBB49_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s2, a1, 255
; RV64I-NEXT: j .LBB49_2 ; RV64I-NEXT: j .LBB49_2
; RV64I-NEXT: .LBB49_1: # %atomicrmw.start ; RV64I-NEXT: .LBB49_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB49_4 ; RV64I-NEXT: bnez a0, .LBB49_4
; RV64I-NEXT: .LBB49_2: # %atomicrmw.start ; RV64I-NEXT: .LBB49_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB49_1 ; RV64I-NEXT: bltu s2, a0, .LBB49_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB49_1 ; RV64I-NEXT: j .LBB49_1
; RV64I-NEXT: .LBB49_4: # %atomicrmw.end ; RV64I-NEXT: .LBB49_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_umax_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: li a3, 255 ; RV64IA-NEXT: li a3, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a6) ; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: and a2, a4, a3 ; RV64IA-NEXT: and a6, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a2, a1, .LBB49_3 ; RV64IA-NEXT: bgeu a6, a1, .LBB49_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB49_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1 ; RV64IA-NEXT: .LBB49_3: # in Loop: Header=BB49_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a6) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB49_1 ; RV64IA-NEXT: bnez a5, .LBB49_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b seq_cst %1 = atomicrmw umax i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_monotonic: ; RV32I-LABEL: atomicrmw_umin_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s2, a1, 255
; RV32I-NEXT: j .LBB50_2 ; RV32I-NEXT: j .LBB50_2
; RV32I-NEXT: .LBB50_1: # %atomicrmw.start ; RV32I-NEXT: .LBB50_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB50_4 ; RV32I-NEXT: bnez a0, .LBB50_4
; RV32I-NEXT: .LBB50_2: # %atomicrmw.start ; RV32I-NEXT: .LBB50_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB50_1 ; RV32I-NEXT: bgeu s2, a0, .LBB50_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB50_1 ; RV32I-NEXT: j .LBB50_1
; RV32I-NEXT: .LBB50_4: # %atomicrmw.end ; RV32I-NEXT: .LBB50_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_monotonic: ; RV32IA-LABEL: atomicrmw_umin_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: li a3, 255 ; RV32IA-NEXT: li a3, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a6) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: and a2, a4, a3 ; RV32IA-NEXT: and a6, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a1, a2, .LBB50_3 ; RV32IA-NEXT: bgeu a1, a6, .LBB50_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1 ; RV32IA-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a6) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB50_1 ; RV32IA-NEXT: bnez a5, .LBB50_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_monotonic: ; RV64I-LABEL: atomicrmw_umin_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s2, a1, 255
; RV64I-NEXT: j .LBB50_2 ; RV64I-NEXT: j .LBB50_2
; RV64I-NEXT: .LBB50_1: # %atomicrmw.start ; RV64I-NEXT: .LBB50_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB50_4 ; RV64I-NEXT: bnez a0, .LBB50_4
; RV64I-NEXT: .LBB50_2: # %atomicrmw.start ; RV64I-NEXT: .LBB50_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB50_1 ; RV64I-NEXT: bgeu s2, a0, .LBB50_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB50_1 ; RV64I-NEXT: j .LBB50_1
; RV64I-NEXT: .LBB50_4: # %atomicrmw.end ; RV64I-NEXT: .LBB50_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_monotonic: ; RV64IA-LABEL: atomicrmw_umin_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: li a3, 255 ; RV64IA-NEXT: li a3, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a6) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: and a2, a4, a3 ; RV64IA-NEXT: and a6, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a1, a2, .LBB50_3 ; RV64IA-NEXT: bgeu a1, a6, .LBB50_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB50_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1 ; RV64IA-NEXT: .LBB50_3: # in Loop: Header=BB50_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a6) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB50_1 ; RV64IA-NEXT: bnez a5, .LBB50_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b monotonic %1 = atomicrmw umin i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_acquire: ; RV32I-LABEL: atomicrmw_umin_i8_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s2, a1, 255
; RV32I-NEXT: j .LBB51_2 ; RV32I-NEXT: j .LBB51_2
; RV32I-NEXT: .LBB51_1: # %atomicrmw.start ; RV32I-NEXT: .LBB51_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB51_4 ; RV32I-NEXT: bnez a0, .LBB51_4
; RV32I-NEXT: .LBB51_2: # %atomicrmw.start ; RV32I-NEXT: .LBB51_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB51_1 ; RV32I-NEXT: bgeu s2, a0, .LBB51_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB51_1 ; RV32I-NEXT: j .LBB51_1
; RV32I-NEXT: .LBB51_4: # %atomicrmw.end ; RV32I-NEXT: .LBB51_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_acquire: ; RV32IA-LABEL: atomicrmw_umin_i8_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: li a3, 255 ; RV32IA-NEXT: li a3, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a6) ; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: and a2, a4, a3 ; RV32IA-NEXT: and a6, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a1, a2, .LBB51_3 ; RV32IA-NEXT: bgeu a1, a6, .LBB51_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1 ; RV32IA-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a6) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB51_1 ; RV32IA-NEXT: bnez a5, .LBB51_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_acquire: ; RV64I-LABEL: atomicrmw_umin_i8_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s2, a1, 255
; RV64I-NEXT: j .LBB51_2 ; RV64I-NEXT: j .LBB51_2
; RV64I-NEXT: .LBB51_1: # %atomicrmw.start ; RV64I-NEXT: .LBB51_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB51_4 ; RV64I-NEXT: bnez a0, .LBB51_4
; RV64I-NEXT: .LBB51_2: # %atomicrmw.start ; RV64I-NEXT: .LBB51_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB51_1 ; RV64I-NEXT: bgeu s2, a0, .LBB51_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB51_1 ; RV64I-NEXT: j .LBB51_1
; RV64I-NEXT: .LBB51_4: # %atomicrmw.end ; RV64I-NEXT: .LBB51_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_acquire: ; RV64IA-LABEL: atomicrmw_umin_i8_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: li a3, 255 ; RV64IA-NEXT: li a3, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB51_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a6) ; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: and a2, a4, a3 ; RV64IA-NEXT: and a6, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a1, a2, .LBB51_3 ; RV64IA-NEXT: bgeu a1, a6, .LBB51_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB51_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1 ; RV64IA-NEXT: .LBB51_3: # in Loop: Header=BB51_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a6) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB51_1 ; RV64IA-NEXT: bnez a5, .LBB51_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b acquire %1 = atomicrmw umin i8* %a, i8 %b acquire
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_release: ; RV32I-LABEL: atomicrmw_umin_i8_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s2, a1, 255
; RV32I-NEXT: j .LBB52_2 ; RV32I-NEXT: j .LBB52_2
; RV32I-NEXT: .LBB52_1: # %atomicrmw.start ; RV32I-NEXT: .LBB52_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a3, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB52_4 ; RV32I-NEXT: bnez a0, .LBB52_4
; RV32I-NEXT: .LBB52_2: # %atomicrmw.start ; RV32I-NEXT: .LBB52_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB52_1 ; RV32I-NEXT: bgeu s2, a0, .LBB52_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB52_1 ; RV32I-NEXT: j .LBB52_1
; RV32I-NEXT: .LBB52_4: # %atomicrmw.end ; RV32I-NEXT: .LBB52_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_release: ; RV32IA-LABEL: atomicrmw_umin_i8_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: li a3, 255 ; RV32IA-NEXT: li a3, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a6) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: and a2, a4, a3 ; RV32IA-NEXT: and a6, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a1, a2, .LBB52_3 ; RV32IA-NEXT: bgeu a1, a6, .LBB52_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1 ; RV32IA-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a6) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB52_1 ; RV32IA-NEXT: bnez a5, .LBB52_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_release: ; RV64I-LABEL: atomicrmw_umin_i8_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s2, a1, 255
; RV64I-NEXT: j .LBB52_2 ; RV64I-NEXT: j .LBB52_2
; RV64I-NEXT: .LBB52_1: # %atomicrmw.start ; RV64I-NEXT: .LBB52_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB52_4 ; RV64I-NEXT: bnez a0, .LBB52_4
; RV64I-NEXT: .LBB52_2: # %atomicrmw.start ; RV64I-NEXT: .LBB52_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB52_1 ; RV64I-NEXT: bgeu s2, a0, .LBB52_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB52_1 ; RV64I-NEXT: j .LBB52_1
; RV64I-NEXT: .LBB52_4: # %atomicrmw.end ; RV64I-NEXT: .LBB52_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_release: ; RV64IA-LABEL: atomicrmw_umin_i8_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: li a3, 255 ; RV64IA-NEXT: li a3, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a6) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: and a2, a4, a3 ; RV64IA-NEXT: and a6, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a1, a2, .LBB52_3 ; RV64IA-NEXT: bgeu a1, a6, .LBB52_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB52_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1 ; RV64IA-NEXT: .LBB52_3: # in Loop: Header=BB52_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a6) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB52_1 ; RV64IA-NEXT: bnez a5, .LBB52_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b release %1 = atomicrmw umin i8* %a, i8 %b release
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_acq_rel: ; RV32I-LABEL: atomicrmw_umin_i8_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s2, a1, 255
; RV32I-NEXT: j .LBB53_2 ; RV32I-NEXT: j .LBB53_2
; RV32I-NEXT: .LBB53_1: # %atomicrmw.start ; RV32I-NEXT: .LBB53_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB53_4 ; RV32I-NEXT: bnez a0, .LBB53_4
; RV32I-NEXT: .LBB53_2: # %atomicrmw.start ; RV32I-NEXT: .LBB53_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB53_1 ; RV32I-NEXT: bgeu s2, a0, .LBB53_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB53_1 ; RV32I-NEXT: j .LBB53_1
; RV32I-NEXT: .LBB53_4: # %atomicrmw.end ; RV32I-NEXT: .LBB53_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_acq_rel: ; RV32IA-LABEL: atomicrmw_umin_i8_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: li a3, 255 ; RV32IA-NEXT: li a3, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a4, (a6) ; RV32IA-NEXT: lr.w.aq a4, (a2)
; RV32IA-NEXT: and a2, a4, a3 ; RV32IA-NEXT: and a6, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a1, a2, .LBB53_3 ; RV32IA-NEXT: bgeu a1, a6, .LBB53_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1 ; RV32IA-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a6) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB53_1 ; RV32IA-NEXT: bnez a5, .LBB53_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_acq_rel: ; RV64I-LABEL: atomicrmw_umin_i8_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s2, a1, 255
; RV64I-NEXT: j .LBB53_2 ; RV64I-NEXT: j .LBB53_2
; RV64I-NEXT: .LBB53_1: # %atomicrmw.start ; RV64I-NEXT: .LBB53_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB53_4 ; RV64I-NEXT: bnez a0, .LBB53_4
; RV64I-NEXT: .LBB53_2: # %atomicrmw.start ; RV64I-NEXT: .LBB53_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB53_1 ; RV64I-NEXT: bgeu s2, a0, .LBB53_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB53_1 ; RV64I-NEXT: j .LBB53_1
; RV64I-NEXT: .LBB53_4: # %atomicrmw.end ; RV64I-NEXT: .LBB53_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_acq_rel: ; RV64IA-LABEL: atomicrmw_umin_i8_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: li a3, 255 ; RV64IA-NEXT: li a3, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a4, (a6) ; RV64IA-NEXT: lr.w.aq a4, (a2)
; RV64IA-NEXT: and a2, a4, a3 ; RV64IA-NEXT: and a6, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a1, a2, .LBB53_3 ; RV64IA-NEXT: bgeu a1, a6, .LBB53_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB53_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1 ; RV64IA-NEXT: .LBB53_3: # in Loop: Header=BB53_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a6) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB53_1 ; RV64IA-NEXT: bnez a5, .LBB53_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b acq_rel %1 = atomicrmw umin i8* %a, i8 %b acq_rel
ret i8 %1 ret i8 %1
} }
define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind { define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_seq_cst: ; RV32I-LABEL: atomicrmw_umin_i8_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s2, a1, 255
; RV32I-NEXT: j .LBB54_2 ; RV32I-NEXT: j .LBB54_2
; RV32I-NEXT: .LBB54_1: # %atomicrmw.start ; RV32I-NEXT: .LBB54_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a4, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB54_4 ; RV32I-NEXT: bnez a0, .LBB54_4
; RV32I-NEXT: .LBB54_2: # %atomicrmw.start ; RV32I-NEXT: .LBB54_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB54_1 ; RV32I-NEXT: bgeu s2, a0, .LBB54_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB54_1 ; RV32I-NEXT: j .LBB54_1
; RV32I-NEXT: .LBB54_4: # %atomicrmw.end ; RV32I-NEXT: .LBB54_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_seq_cst: ; RV32IA-LABEL: atomicrmw_umin_i8_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: li a3, 255 ; RV32IA-NEXT: li a3, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a4, (a6) ; RV32IA-NEXT: lr.w.aqrl a4, (a2)
; RV32IA-NEXT: and a2, a4, a3 ; RV32IA-NEXT: and a6, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a1, a2, .LBB54_3 ; RV32IA-NEXT: bgeu a1, a6, .LBB54_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1 ; RV32IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a6) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB54_1 ; RV32IA-NEXT: bnez a5, .LBB54_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i8_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s2, a1, 255
; RV64I-NEXT: j .LBB54_2 ; RV64I-NEXT: j .LBB54_2
; RV64I-NEXT: .LBB54_1: # %atomicrmw.start ; RV64I-NEXT: .LBB54_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB54_4 ; RV64I-NEXT: bnez a0, .LBB54_4
; RV64I-NEXT: .LBB54_2: # %atomicrmw.start ; RV64I-NEXT: .LBB54_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB54_1 ; RV64I-NEXT: bgeu s2, a0, .LBB54_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB54_1 ; RV64I-NEXT: j .LBB54_1
; RV64I-NEXT: .LBB54_4: # %atomicrmw.end ; RV64I-NEXT: .LBB54_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_seq_cst: ; RV64IA-LABEL: atomicrmw_umin_i8_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: li a3, 255 ; RV64IA-NEXT: li a3, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a4, (a6) ; RV64IA-NEXT: lr.w.aqrl a4, (a2)
; RV64IA-NEXT: and a2, a4, a3 ; RV64IA-NEXT: and a6, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a1, a2, .LBB54_3 ; RV64IA-NEXT: bgeu a1, a6, .LBB54_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB54_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1 ; RV64IA-NEXT: .LBB54_3: # in Loop: Header=BB54_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a6) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB54_1 ; RV64IA-NEXT: bnez a5, .LBB54_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b seq_cst %1 = atomicrmw umin i8* %a, i8 %b seq_cst
ret i8 %1 ret i8 %1
} }
▲ Show 20 Lines • Show All 2,062 Lines • ▼ Show 20 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s2, a0, 16
; RV32I-NEXT: j .LBB90_2 ; RV32I-NEXT: j .LBB90_2
; RV32I-NEXT: .LBB90_1: # %atomicrmw.start ; RV32I-NEXT: .LBB90_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB90_4 ; RV32I-NEXT: bnez a0, .LBB90_4
; RV32I-NEXT: .LBB90_2: # %atomicrmw.start ; RV32I-NEXT: .LBB90_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB90_1 ; RV32I-NEXT: blt s2, a0, .LBB90_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB90_1 ; RV32I-NEXT: j .LBB90_1
; RV32I-NEXT: .LBB90_4: # %atomicrmw.end ; RV32I-NEXT: .LBB90_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_monotonic: ; RV32IA-LABEL: atomicrmw_max_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 16 ; RV32IA-NEXT: li a5, 16
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a6) ; RV32IA-NEXT: lr.w a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a4, a1, .LBB90_3 ; RV32IA-NEXT: bge a7, a1, .LBB90_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB90_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB90_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB90_3: # in Loop: Header=BB90_1 Depth=1 ; RV32IA-NEXT: .LBB90_3: # in Loop: Header=BB90_1 Depth=1
; RV32IA-NEXT: sc.w a2, a2, (a6) ; RV32IA-NEXT: sc.w a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB90_1 ; RV32IA-NEXT: bnez a6, .LBB90_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_monotonic: ; RV64I-LABEL: atomicrmw_max_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s2, a0, 48
; RV64I-NEXT: j .LBB90_2 ; RV64I-NEXT: j .LBB90_2
; RV64I-NEXT: .LBB90_1: # %atomicrmw.start ; RV64I-NEXT: .LBB90_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB90_4 ; RV64I-NEXT: bnez a0, .LBB90_4
; RV64I-NEXT: .LBB90_2: # %atomicrmw.start ; RV64I-NEXT: .LBB90_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB90_1 ; RV64I-NEXT: blt s2, a0, .LBB90_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB90_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB90_1 ; RV64I-NEXT: j .LBB90_1
; RV64I-NEXT: .LBB90_4: # %atomicrmw.end ; RV64I-NEXT: .LBB90_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_monotonic: ; RV64IA-LABEL: atomicrmw_max_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 48 ; RV64IA-NEXT: li a5, 48
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB90_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6) ; RV64IA-NEXT: lr.w a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a4, a1, .LBB90_3 ; RV64IA-NEXT: bge a7, a1, .LBB90_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB90_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB90_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB90_3: # in Loop: Header=BB90_1 Depth=1 ; RV64IA-NEXT: .LBB90_3: # in Loop: Header=BB90_1 Depth=1
; RV64IA-NEXT: sc.w a2, a2, (a6) ; RV64IA-NEXT: sc.w a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB90_1 ; RV64IA-NEXT: bnez a6, .LBB90_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b monotonic %1 = atomicrmw max i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_acquire: ; RV32I-LABEL: atomicrmw_max_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s2, a0, 16
; RV32I-NEXT: j .LBB91_2 ; RV32I-NEXT: j .LBB91_2
; RV32I-NEXT: .LBB91_1: # %atomicrmw.start ; RV32I-NEXT: .LBB91_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB91_4 ; RV32I-NEXT: bnez a0, .LBB91_4
; RV32I-NEXT: .LBB91_2: # %atomicrmw.start ; RV32I-NEXT: .LBB91_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB91_1 ; RV32I-NEXT: blt s2, a0, .LBB91_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB91_1 ; RV32I-NEXT: j .LBB91_1
; RV32I-NEXT: .LBB91_4: # %atomicrmw.end ; RV32I-NEXT: .LBB91_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_acquire: ; RV32IA-LABEL: atomicrmw_max_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 16 ; RV32IA-NEXT: li a5, 16
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a6) ; RV32IA-NEXT: lr.w.aq a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a4, a1, .LBB91_3 ; RV32IA-NEXT: bge a7, a1, .LBB91_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB91_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB91_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB91_3: # in Loop: Header=BB91_1 Depth=1 ; RV32IA-NEXT: .LBB91_3: # in Loop: Header=BB91_1 Depth=1
; RV32IA-NEXT: sc.w a2, a2, (a6) ; RV32IA-NEXT: sc.w a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB91_1 ; RV32IA-NEXT: bnez a6, .LBB91_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_acquire: ; RV64I-LABEL: atomicrmw_max_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s2, a0, 48
; RV64I-NEXT: j .LBB91_2 ; RV64I-NEXT: j .LBB91_2
; RV64I-NEXT: .LBB91_1: # %atomicrmw.start ; RV64I-NEXT: .LBB91_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB91_4 ; RV64I-NEXT: bnez a0, .LBB91_4
; RV64I-NEXT: .LBB91_2: # %atomicrmw.start ; RV64I-NEXT: .LBB91_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB91_1 ; RV64I-NEXT: blt s2, a0, .LBB91_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB91_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB91_1 ; RV64I-NEXT: j .LBB91_1
; RV64I-NEXT: .LBB91_4: # %atomicrmw.end ; RV64I-NEXT: .LBB91_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_acquire: ; RV64IA-LABEL: atomicrmw_max_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 48 ; RV64IA-NEXT: li a5, 48
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB91_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6) ; RV64IA-NEXT: lr.w.aq a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a4, a1, .LBB91_3 ; RV64IA-NEXT: bge a7, a1, .LBB91_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB91_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB91_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB91_3: # in Loop: Header=BB91_1 Depth=1 ; RV64IA-NEXT: .LBB91_3: # in Loop: Header=BB91_1 Depth=1
; RV64IA-NEXT: sc.w a2, a2, (a6) ; RV64IA-NEXT: sc.w a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB91_1 ; RV64IA-NEXT: bnez a6, .LBB91_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b acquire %1 = atomicrmw max i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_release: ; RV32I-LABEL: atomicrmw_max_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s2, a0, 16
; RV32I-NEXT: j .LBB92_2 ; RV32I-NEXT: j .LBB92_2
; RV32I-NEXT: .LBB92_1: # %atomicrmw.start ; RV32I-NEXT: .LBB92_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a3, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB92_4 ; RV32I-NEXT: bnez a0, .LBB92_4
; RV32I-NEXT: .LBB92_2: # %atomicrmw.start ; RV32I-NEXT: .LBB92_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB92_1 ; RV32I-NEXT: blt s2, a0, .LBB92_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB92_1 ; RV32I-NEXT: j .LBB92_1
; RV32I-NEXT: .LBB92_4: # %atomicrmw.end ; RV32I-NEXT: .LBB92_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_release: ; RV32IA-LABEL: atomicrmw_max_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 16 ; RV32IA-NEXT: li a5, 16
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a6) ; RV32IA-NEXT: lr.w a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a4, a1, .LBB92_3 ; RV32IA-NEXT: bge a7, a1, .LBB92_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB92_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB92_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB92_3: # in Loop: Header=BB92_1 Depth=1 ; RV32IA-NEXT: .LBB92_3: # in Loop: Header=BB92_1 Depth=1
; RV32IA-NEXT: sc.w.rl a2, a2, (a6) ; RV32IA-NEXT: sc.w.rl a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB92_1 ; RV32IA-NEXT: bnez a6, .LBB92_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_release: ; RV64I-LABEL: atomicrmw_max_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s2, a0, 48
; RV64I-NEXT: j .LBB92_2 ; RV64I-NEXT: j .LBB92_2
; RV64I-NEXT: .LBB92_1: # %atomicrmw.start ; RV64I-NEXT: .LBB92_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB92_4 ; RV64I-NEXT: bnez a0, .LBB92_4
; RV64I-NEXT: .LBB92_2: # %atomicrmw.start ; RV64I-NEXT: .LBB92_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB92_1 ; RV64I-NEXT: blt s2, a0, .LBB92_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB92_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB92_1 ; RV64I-NEXT: j .LBB92_1
; RV64I-NEXT: .LBB92_4: # %atomicrmw.end ; RV64I-NEXT: .LBB92_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_release: ; RV64IA-LABEL: atomicrmw_max_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 48 ; RV64IA-NEXT: li a5, 48
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB92_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6) ; RV64IA-NEXT: lr.w a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a4, a1, .LBB92_3 ; RV64IA-NEXT: bge a7, a1, .LBB92_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB92_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB92_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB92_3: # in Loop: Header=BB92_1 Depth=1 ; RV64IA-NEXT: .LBB92_3: # in Loop: Header=BB92_1 Depth=1
; RV64IA-NEXT: sc.w.rl a2, a2, (a6) ; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB92_1 ; RV64IA-NEXT: bnez a6, .LBB92_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b release %1 = atomicrmw max i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_acq_rel: ; RV32I-LABEL: atomicrmw_max_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s2, a0, 16
; RV32I-NEXT: j .LBB93_2 ; RV32I-NEXT: j .LBB93_2
; RV32I-NEXT: .LBB93_1: # %atomicrmw.start ; RV32I-NEXT: .LBB93_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB93_4 ; RV32I-NEXT: bnez a0, .LBB93_4
; RV32I-NEXT: .LBB93_2: # %atomicrmw.start ; RV32I-NEXT: .LBB93_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB93_1 ; RV32I-NEXT: blt s2, a0, .LBB93_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB93_1 ; RV32I-NEXT: j .LBB93_1
; RV32I-NEXT: .LBB93_4: # %atomicrmw.end ; RV32I-NEXT: .LBB93_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_max_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 16 ; RV32IA-NEXT: li a5, 16
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a6) ; RV32IA-NEXT: lr.w.aq a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a4, a1, .LBB93_3 ; RV32IA-NEXT: bge a7, a1, .LBB93_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB93_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB93_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB93_3: # in Loop: Header=BB93_1 Depth=1 ; RV32IA-NEXT: .LBB93_3: # in Loop: Header=BB93_1 Depth=1
; RV32IA-NEXT: sc.w.rl a2, a2, (a6) ; RV32IA-NEXT: sc.w.rl a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB93_1 ; RV32IA-NEXT: bnez a6, .LBB93_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_acq_rel: ; RV64I-LABEL: atomicrmw_max_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s2, a0, 48
; RV64I-NEXT: j .LBB93_2 ; RV64I-NEXT: j .LBB93_2
; RV64I-NEXT: .LBB93_1: # %atomicrmw.start ; RV64I-NEXT: .LBB93_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB93_4 ; RV64I-NEXT: bnez a0, .LBB93_4
; RV64I-NEXT: .LBB93_2: # %atomicrmw.start ; RV64I-NEXT: .LBB93_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB93_1 ; RV64I-NEXT: blt s2, a0, .LBB93_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB93_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB93_1 ; RV64I-NEXT: j .LBB93_1
; RV64I-NEXT: .LBB93_4: # %atomicrmw.end ; RV64I-NEXT: .LBB93_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_max_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 48 ; RV64IA-NEXT: li a5, 48
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB93_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6) ; RV64IA-NEXT: lr.w.aq a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a4, a1, .LBB93_3 ; RV64IA-NEXT: bge a7, a1, .LBB93_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB93_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB93_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB93_3: # in Loop: Header=BB93_1 Depth=1 ; RV64IA-NEXT: .LBB93_3: # in Loop: Header=BB93_1 Depth=1
; RV64IA-NEXT: sc.w.rl a2, a2, (a6) ; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB93_1 ; RV64IA-NEXT: bnez a6, .LBB93_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b acq_rel %1 = atomicrmw max i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_seq_cst: ; RV32I-LABEL: atomicrmw_max_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s2, a0, 16
; RV32I-NEXT: j .LBB94_2 ; RV32I-NEXT: j .LBB94_2
; RV32I-NEXT: .LBB94_1: # %atomicrmw.start ; RV32I-NEXT: .LBB94_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a4, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB94_4 ; RV32I-NEXT: bnez a0, .LBB94_4
; RV32I-NEXT: .LBB94_2: # %atomicrmw.start ; RV32I-NEXT: .LBB94_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB94_1 ; RV32I-NEXT: blt s2, a0, .LBB94_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB94_1 ; RV32I-NEXT: j .LBB94_1
; RV32I-NEXT: .LBB94_4: # %atomicrmw.end ; RV32I-NEXT: .LBB94_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_max_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 16 ; RV32IA-NEXT: li a5, 16
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a5, (a6) ; RV32IA-NEXT: lr.w.aqrl a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a4, a1, .LBB94_3 ; RV32IA-NEXT: bge a7, a1, .LBB94_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB94_3: # in Loop: Header=BB94_1 Depth=1 ; RV32IA-NEXT: .LBB94_3: # in Loop: Header=BB94_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a2, a2, (a6) ; RV32IA-NEXT: sc.w.aqrl a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB94_1 ; RV32IA-NEXT: bnez a6, .LBB94_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_seq_cst: ; RV64I-LABEL: atomicrmw_max_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s2, a0, 48
; RV64I-NEXT: j .LBB94_2 ; RV64I-NEXT: j .LBB94_2
; RV64I-NEXT: .LBB94_1: # %atomicrmw.start ; RV64I-NEXT: .LBB94_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB94_4 ; RV64I-NEXT: bnez a0, .LBB94_4
; RV64I-NEXT: .LBB94_2: # %atomicrmw.start ; RV64I-NEXT: .LBB94_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB94_1 ; RV64I-NEXT: blt s2, a0, .LBB94_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB94_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB94_1 ; RV64I-NEXT: j .LBB94_1
; RV64I-NEXT: .LBB94_4: # %atomicrmw.end ; RV64I-NEXT: .LBB94_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_max_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 48 ; RV64IA-NEXT: li a5, 48
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB94_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a6) ; RV64IA-NEXT: lr.w.aqrl a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a4, a1, .LBB94_3 ; RV64IA-NEXT: bge a7, a1, .LBB94_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB94_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB94_3: # in Loop: Header=BB94_1 Depth=1 ; RV64IA-NEXT: .LBB94_3: # in Loop: Header=BB94_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a2, a2, (a6) ; RV64IA-NEXT: sc.w.aqrl a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB94_1 ; RV64IA-NEXT: bnez a6, .LBB94_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b seq_cst %1 = atomicrmw max i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_monotonic: ; RV32I-LABEL: atomicrmw_min_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s2, a0, 16
; RV32I-NEXT: j .LBB95_2 ; RV32I-NEXT: j .LBB95_2
; RV32I-NEXT: .LBB95_1: # %atomicrmw.start ; RV32I-NEXT: .LBB95_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB95_4 ; RV32I-NEXT: bnez a0, .LBB95_4
; RV32I-NEXT: .LBB95_2: # %atomicrmw.start ; RV32I-NEXT: .LBB95_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB95_1 ; RV32I-NEXT: bge s2, a0, .LBB95_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB95_1 ; RV32I-NEXT: j .LBB95_1
; RV32I-NEXT: .LBB95_4: # %atomicrmw.end ; RV32I-NEXT: .LBB95_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_monotonic: ; RV32IA-LABEL: atomicrmw_min_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 16 ; RV32IA-NEXT: li a5, 16
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a6) ; RV32IA-NEXT: lr.w a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a1, a4, .LBB95_3 ; RV32IA-NEXT: bge a1, a7, .LBB95_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB95_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB95_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB95_3: # in Loop: Header=BB95_1 Depth=1 ; RV32IA-NEXT: .LBB95_3: # in Loop: Header=BB95_1 Depth=1
; RV32IA-NEXT: sc.w a2, a2, (a6) ; RV32IA-NEXT: sc.w a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB95_1 ; RV32IA-NEXT: bnez a6, .LBB95_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_monotonic: ; RV64I-LABEL: atomicrmw_min_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s2, a0, 48
; RV64I-NEXT: j .LBB95_2 ; RV64I-NEXT: j .LBB95_2
; RV64I-NEXT: .LBB95_1: # %atomicrmw.start ; RV64I-NEXT: .LBB95_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB95_4 ; RV64I-NEXT: bnez a0, .LBB95_4
; RV64I-NEXT: .LBB95_2: # %atomicrmw.start ; RV64I-NEXT: .LBB95_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB95_1 ; RV64I-NEXT: bge s2, a0, .LBB95_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB95_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB95_1 ; RV64I-NEXT: j .LBB95_1
; RV64I-NEXT: .LBB95_4: # %atomicrmw.end ; RV64I-NEXT: .LBB95_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_monotonic: ; RV64IA-LABEL: atomicrmw_min_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 48 ; RV64IA-NEXT: li a5, 48
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB95_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6) ; RV64IA-NEXT: lr.w a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a1, a4, .LBB95_3 ; RV64IA-NEXT: bge a1, a7, .LBB95_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB95_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB95_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB95_3: # in Loop: Header=BB95_1 Depth=1 ; RV64IA-NEXT: .LBB95_3: # in Loop: Header=BB95_1 Depth=1
; RV64IA-NEXT: sc.w a2, a2, (a6) ; RV64IA-NEXT: sc.w a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB95_1 ; RV64IA-NEXT: bnez a6, .LBB95_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b monotonic %1 = atomicrmw min i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_acquire: ; RV32I-LABEL: atomicrmw_min_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s2, a0, 16
; RV32I-NEXT: j .LBB96_2 ; RV32I-NEXT: j .LBB96_2
; RV32I-NEXT: .LBB96_1: # %atomicrmw.start ; RV32I-NEXT: .LBB96_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB96_4 ; RV32I-NEXT: bnez a0, .LBB96_4
; RV32I-NEXT: .LBB96_2: # %atomicrmw.start ; RV32I-NEXT: .LBB96_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB96_1 ; RV32I-NEXT: bge s2, a0, .LBB96_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB96_1 ; RV32I-NEXT: j .LBB96_1
; RV32I-NEXT: .LBB96_4: # %atomicrmw.end ; RV32I-NEXT: .LBB96_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_acquire: ; RV32IA-LABEL: atomicrmw_min_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 16 ; RV32IA-NEXT: li a5, 16
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a6) ; RV32IA-NEXT: lr.w.aq a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a1, a4, .LBB96_3 ; RV32IA-NEXT: bge a1, a7, .LBB96_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB96_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB96_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB96_3: # in Loop: Header=BB96_1 Depth=1 ; RV32IA-NEXT: .LBB96_3: # in Loop: Header=BB96_1 Depth=1
; RV32IA-NEXT: sc.w a2, a2, (a6) ; RV32IA-NEXT: sc.w a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB96_1 ; RV32IA-NEXT: bnez a6, .LBB96_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_acquire: ; RV64I-LABEL: atomicrmw_min_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s2, a0, 48
; RV64I-NEXT: j .LBB96_2 ; RV64I-NEXT: j .LBB96_2
; RV64I-NEXT: .LBB96_1: # %atomicrmw.start ; RV64I-NEXT: .LBB96_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB96_4 ; RV64I-NEXT: bnez a0, .LBB96_4
; RV64I-NEXT: .LBB96_2: # %atomicrmw.start ; RV64I-NEXT: .LBB96_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB96_1 ; RV64I-NEXT: bge s2, a0, .LBB96_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB96_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB96_1 ; RV64I-NEXT: j .LBB96_1
; RV64I-NEXT: .LBB96_4: # %atomicrmw.end ; RV64I-NEXT: .LBB96_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_acquire: ; RV64IA-LABEL: atomicrmw_min_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 48 ; RV64IA-NEXT: li a5, 48
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB96_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6) ; RV64IA-NEXT: lr.w.aq a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a1, a4, .LBB96_3 ; RV64IA-NEXT: bge a1, a7, .LBB96_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB96_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB96_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB96_3: # in Loop: Header=BB96_1 Depth=1 ; RV64IA-NEXT: .LBB96_3: # in Loop: Header=BB96_1 Depth=1
; RV64IA-NEXT: sc.w a2, a2, (a6) ; RV64IA-NEXT: sc.w a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB96_1 ; RV64IA-NEXT: bnez a6, .LBB96_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b acquire %1 = atomicrmw min i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_release: ; RV32I-LABEL: atomicrmw_min_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s2, a0, 16
; RV32I-NEXT: j .LBB97_2 ; RV32I-NEXT: j .LBB97_2
; RV32I-NEXT: .LBB97_1: # %atomicrmw.start ; RV32I-NEXT: .LBB97_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a3, 3
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB97_4 ; RV32I-NEXT: bnez a0, .LBB97_4
; RV32I-NEXT: .LBB97_2: # %atomicrmw.start ; RV32I-NEXT: .LBB97_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB97_1 ; RV32I-NEXT: bge s2, a0, .LBB97_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB97_1 ; RV32I-NEXT: j .LBB97_1
; RV32I-NEXT: .LBB97_4: # %atomicrmw.end ; RV32I-NEXT: .LBB97_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_release: ; RV32IA-LABEL: atomicrmw_min_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 16 ; RV32IA-NEXT: li a5, 16
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a6) ; RV32IA-NEXT: lr.w a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a1, a4, .LBB97_3 ; RV32IA-NEXT: bge a1, a7, .LBB97_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB97_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB97_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB97_3: # in Loop: Header=BB97_1 Depth=1 ; RV32IA-NEXT: .LBB97_3: # in Loop: Header=BB97_1 Depth=1
; RV32IA-NEXT: sc.w.rl a2, a2, (a6) ; RV32IA-NEXT: sc.w.rl a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB97_1 ; RV32IA-NEXT: bnez a6, .LBB97_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_release: ; RV64I-LABEL: atomicrmw_min_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s2, a0, 48
; RV64I-NEXT: j .LBB97_2 ; RV64I-NEXT: j .LBB97_2
; RV64I-NEXT: .LBB97_1: # %atomicrmw.start ; RV64I-NEXT: .LBB97_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB97_4 ; RV64I-NEXT: bnez a0, .LBB97_4
; RV64I-NEXT: .LBB97_2: # %atomicrmw.start ; RV64I-NEXT: .LBB97_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB97_1 ; RV64I-NEXT: bge s2, a0, .LBB97_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB97_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB97_1 ; RV64I-NEXT: j .LBB97_1
; RV64I-NEXT: .LBB97_4: # %atomicrmw.end ; RV64I-NEXT: .LBB97_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_release: ; RV64IA-LABEL: atomicrmw_min_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 48 ; RV64IA-NEXT: li a5, 48
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB97_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6) ; RV64IA-NEXT: lr.w a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a1, a4, .LBB97_3 ; RV64IA-NEXT: bge a1, a7, .LBB97_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB97_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB97_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB97_3: # in Loop: Header=BB97_1 Depth=1 ; RV64IA-NEXT: .LBB97_3: # in Loop: Header=BB97_1 Depth=1
; RV64IA-NEXT: sc.w.rl a2, a2, (a6) ; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB97_1 ; RV64IA-NEXT: bnez a6, .LBB97_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b release %1 = atomicrmw min i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_acq_rel: ; RV32I-LABEL: atomicrmw_min_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s2, a0, 16
; RV32I-NEXT: j .LBB98_2 ; RV32I-NEXT: j .LBB98_2
; RV32I-NEXT: .LBB98_1: # %atomicrmw.start ; RV32I-NEXT: .LBB98_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB98_4 ; RV32I-NEXT: bnez a0, .LBB98_4
; RV32I-NEXT: .LBB98_2: # %atomicrmw.start ; RV32I-NEXT: .LBB98_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB98_1 ; RV32I-NEXT: bge s2, a0, .LBB98_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB98_1 ; RV32I-NEXT: j .LBB98_1
; RV32I-NEXT: .LBB98_4: # %atomicrmw.end ; RV32I-NEXT: .LBB98_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_min_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 16 ; RV32IA-NEXT: li a5, 16
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a5, (a6) ; RV32IA-NEXT: lr.w.aq a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a1, a4, .LBB98_3 ; RV32IA-NEXT: bge a1, a7, .LBB98_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB98_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB98_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB98_3: # in Loop: Header=BB98_1 Depth=1 ; RV32IA-NEXT: .LBB98_3: # in Loop: Header=BB98_1 Depth=1
; RV32IA-NEXT: sc.w.rl a2, a2, (a6) ; RV32IA-NEXT: sc.w.rl a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB98_1 ; RV32IA-NEXT: bnez a6, .LBB98_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_acq_rel: ; RV64I-LABEL: atomicrmw_min_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s2, a0, 48
; RV64I-NEXT: j .LBB98_2 ; RV64I-NEXT: j .LBB98_2
; RV64I-NEXT: .LBB98_1: # %atomicrmw.start ; RV64I-NEXT: .LBB98_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB98_4 ; RV64I-NEXT: bnez a0, .LBB98_4
; RV64I-NEXT: .LBB98_2: # %atomicrmw.start ; RV64I-NEXT: .LBB98_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB98_1 ; RV64I-NEXT: bge s2, a0, .LBB98_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB98_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB98_1 ; RV64I-NEXT: j .LBB98_1
; RV64I-NEXT: .LBB98_4: # %atomicrmw.end ; RV64I-NEXT: .LBB98_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_min_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 48 ; RV64IA-NEXT: li a5, 48
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB98_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a5, (a6) ; RV64IA-NEXT: lr.w.aq a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a1, a4, .LBB98_3 ; RV64IA-NEXT: bge a1, a7, .LBB98_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB98_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB98_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB98_3: # in Loop: Header=BB98_1 Depth=1 ; RV64IA-NEXT: .LBB98_3: # in Loop: Header=BB98_1 Depth=1
; RV64IA-NEXT: sc.w.rl a2, a2, (a6) ; RV64IA-NEXT: sc.w.rl a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB98_1 ; RV64IA-NEXT: bnez a6, .LBB98_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b acq_rel %1 = atomicrmw min i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_seq_cst: ; RV32I-LABEL: atomicrmw_min_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s2, a0, 16
; RV32I-NEXT: j .LBB99_2 ; RV32I-NEXT: j .LBB99_2
; RV32I-NEXT: .LBB99_1: # %atomicrmw.start ; RV32I-NEXT: .LBB99_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a4, 5
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB99_4 ; RV32I-NEXT: bnez a0, .LBB99_4
; RV32I-NEXT: .LBB99_2: # %atomicrmw.start ; RV32I-NEXT: .LBB99_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB99_1 ; RV32I-NEXT: bge s2, a0, .LBB99_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB99_1 ; RV32I-NEXT: j .LBB99_1
; RV32I-NEXT: .LBB99_4: # %atomicrmw.end ; RV32I-NEXT: .LBB99_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_min_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 16 ; RV32IA-NEXT: li a5, 16
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a5, (a6) ; RV32IA-NEXT: lr.w.aqrl a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a1, a4, .LBB99_3 ; RV32IA-NEXT: bge a1, a7, .LBB99_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB99_3: # in Loop: Header=BB99_1 Depth=1 ; RV32IA-NEXT: .LBB99_3: # in Loop: Header=BB99_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a2, a2, (a6) ; RV32IA-NEXT: sc.w.aqrl a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB99_1 ; RV32IA-NEXT: bnez a6, .LBB99_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_seq_cst: ; RV64I-LABEL: atomicrmw_min_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s2, a0, 48
; RV64I-NEXT: j .LBB99_2 ; RV64I-NEXT: j .LBB99_2
; RV64I-NEXT: .LBB99_1: # %atomicrmw.start ; RV64I-NEXT: .LBB99_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB99_4 ; RV64I-NEXT: bnez a0, .LBB99_4
; RV64I-NEXT: .LBB99_2: # %atomicrmw.start ; RV64I-NEXT: .LBB99_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB99_1 ; RV64I-NEXT: bge s2, a0, .LBB99_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB99_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB99_1 ; RV64I-NEXT: j .LBB99_1
; RV64I-NEXT: .LBB99_4: # %atomicrmw.end ; RV64I-NEXT: .LBB99_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_min_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 48 ; RV64IA-NEXT: li a5, 48
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB99_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a5, (a6) ; RV64IA-NEXT: lr.w.aqrl a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a1, a4, .LBB99_3 ; RV64IA-NEXT: bge a1, a7, .LBB99_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB99_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB99_3: # in Loop: Header=BB99_1 Depth=1 ; RV64IA-NEXT: .LBB99_3: # in Loop: Header=BB99_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a2, a2, (a6) ; RV64IA-NEXT: sc.w.aqrl a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB99_1 ; RV64IA-NEXT: bnez a6, .LBB99_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b seq_cst %1 = atomicrmw min i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_monotonic: ; RV32I-LABEL: atomicrmw_umax_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s2, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s3, s0, s2
; RV32I-NEXT: j .LBB100_2 ; RV32I-NEXT: j .LBB100_2
; RV32I-NEXT: .LBB100_1: # %atomicrmw.start ; RV32I-NEXT: .LBB100_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB100_4 ; RV32I-NEXT: bnez a0, .LBB100_4
; RV32I-NEXT: .LBB100_2: # %atomicrmw.start ; RV32I-NEXT: .LBB100_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB100_1 ; RV32I-NEXT: bltu s3, a0, .LBB100_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: j .LBB100_1 ; RV32I-NEXT: j .LBB100_1
; RV32I-NEXT: .LBB100_4: # %atomicrmw.end ; RV32I-NEXT: .LBB100_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_monotonic: ; RV32IA-LABEL: atomicrmw_umax_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB100_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB100_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a6) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: and a2, a3, a4 ; RV32IA-NEXT: and a6, a3, a4
; RV32IA-NEXT: mv a5, a3 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a2, a1, .LBB100_3 ; RV32IA-NEXT: bgeu a6, a1, .LBB100_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB100_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB100_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB100_3: # in Loop: Header=BB100_1 Depth=1 ; RV32IA-NEXT: .LBB100_3: # in Loop: Header=BB100_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a6) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB100_1 ; RV32IA-NEXT: bnez a5, .LBB100_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_monotonic: ; RV64I-LABEL: atomicrmw_umax_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s2, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB100_2 ; RV64I-NEXT: j .LBB100_2
; RV64I-NEXT: .LBB100_1: # %atomicrmw.start ; RV64I-NEXT: .LBB100_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB100_4 ; RV64I-NEXT: bnez a0, .LBB100_4
; RV64I-NEXT: .LBB100_2: # %atomicrmw.start ; RV64I-NEXT: .LBB100_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB100_1 ; RV64I-NEXT: bltu s3, a0, .LBB100_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB100_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: j .LBB100_1 ; RV64I-NEXT: j .LBB100_1
; RV64I-NEXT: .LBB100_4: # %atomicrmw.end ; RV64I-NEXT: .LBB100_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_monotonic: ; RV64IA-LABEL: atomicrmw_umax_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB100_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB100_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a6) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: and a2, a3, a4 ; RV64IA-NEXT: and a6, a3, a4
; RV64IA-NEXT: mv a5, a3 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a2, a1, .LBB100_3 ; RV64IA-NEXT: bgeu a6, a1, .LBB100_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB100_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB100_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB100_3: # in Loop: Header=BB100_1 Depth=1 ; RV64IA-NEXT: .LBB100_3: # in Loop: Header=BB100_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a6) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB100_1 ; RV64IA-NEXT: bnez a5, .LBB100_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b monotonic %1 = atomicrmw umax i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_acquire: ; RV32I-LABEL: atomicrmw_umax_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s2, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s3, s0, s2
; RV32I-NEXT: j .LBB101_2 ; RV32I-NEXT: j .LBB101_2
; RV32I-NEXT: .LBB101_1: # %atomicrmw.start ; RV32I-NEXT: .LBB101_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB101_4 ; RV32I-NEXT: bnez a0, .LBB101_4
; RV32I-NEXT: .LBB101_2: # %atomicrmw.start ; RV32I-NEXT: .LBB101_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB101_1 ; RV32I-NEXT: bltu s3, a0, .LBB101_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: j .LBB101_1 ; RV32I-NEXT: j .LBB101_1
; RV32I-NEXT: .LBB101_4: # %atomicrmw.end ; RV32I-NEXT: .LBB101_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_acquire: ; RV32IA-LABEL: atomicrmw_umax_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB101_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB101_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a6) ; RV32IA-NEXT: lr.w.aq a3, (a2)
; RV32IA-NEXT: and a2, a3, a4 ; RV32IA-NEXT: and a6, a3, a4
; RV32IA-NEXT: mv a5, a3 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a2, a1, .LBB101_3 ; RV32IA-NEXT: bgeu a6, a1, .LBB101_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB101_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB101_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB101_3: # in Loop: Header=BB101_1 Depth=1 ; RV32IA-NEXT: .LBB101_3: # in Loop: Header=BB101_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a6) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB101_1 ; RV32IA-NEXT: bnez a5, .LBB101_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_acquire: ; RV64I-LABEL: atomicrmw_umax_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s2, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB101_2 ; RV64I-NEXT: j .LBB101_2
; RV64I-NEXT: .LBB101_1: # %atomicrmw.start ; RV64I-NEXT: .LBB101_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB101_4 ; RV64I-NEXT: bnez a0, .LBB101_4
; RV64I-NEXT: .LBB101_2: # %atomicrmw.start ; RV64I-NEXT: .LBB101_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB101_1 ; RV64I-NEXT: bltu s3, a0, .LBB101_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB101_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: j .LBB101_1 ; RV64I-NEXT: j .LBB101_1
; RV64I-NEXT: .LBB101_4: # %atomicrmw.end ; RV64I-NEXT: .LBB101_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_acquire: ; RV64IA-LABEL: atomicrmw_umax_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB101_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB101_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a6) ; RV64IA-NEXT: lr.w.aq a3, (a2)
; RV64IA-NEXT: and a2, a3, a4 ; RV64IA-NEXT: and a6, a3, a4
; RV64IA-NEXT: mv a5, a3 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a2, a1, .LBB101_3 ; RV64IA-NEXT: bgeu a6, a1, .LBB101_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB101_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB101_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB101_3: # in Loop: Header=BB101_1 Depth=1 ; RV64IA-NEXT: .LBB101_3: # in Loop: Header=BB101_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a6) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB101_1 ; RV64IA-NEXT: bnez a5, .LBB101_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b acquire %1 = atomicrmw umax i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_release: ; RV32I-LABEL: atomicrmw_umax_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s2, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s3, s0, s2
; RV32I-NEXT: j .LBB102_2 ; RV32I-NEXT: j .LBB102_2
; RV32I-NEXT: .LBB102_1: # %atomicrmw.start ; RV32I-NEXT: .LBB102_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a3, 3
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB102_4 ; RV32I-NEXT: bnez a0, .LBB102_4
; RV32I-NEXT: .LBB102_2: # %atomicrmw.start ; RV32I-NEXT: .LBB102_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB102_1 ; RV32I-NEXT: bltu s3, a0, .LBB102_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: j .LBB102_1 ; RV32I-NEXT: j .LBB102_1
; RV32I-NEXT: .LBB102_4: # %atomicrmw.end ; RV32I-NEXT: .LBB102_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_release: ; RV32IA-LABEL: atomicrmw_umax_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB102_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB102_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a6) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: and a2, a3, a4 ; RV32IA-NEXT: and a6, a3, a4
; RV32IA-NEXT: mv a5, a3 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a2, a1, .LBB102_3 ; RV32IA-NEXT: bgeu a6, a1, .LBB102_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB102_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB102_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB102_3: # in Loop: Header=BB102_1 Depth=1 ; RV32IA-NEXT: .LBB102_3: # in Loop: Header=BB102_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a6) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB102_1 ; RV32IA-NEXT: bnez a5, .LBB102_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_release: ; RV64I-LABEL: atomicrmw_umax_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s2, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB102_2 ; RV64I-NEXT: j .LBB102_2
; RV64I-NEXT: .LBB102_1: # %atomicrmw.start ; RV64I-NEXT: .LBB102_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB102_4 ; RV64I-NEXT: bnez a0, .LBB102_4
; RV64I-NEXT: .LBB102_2: # %atomicrmw.start ; RV64I-NEXT: .LBB102_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB102_1 ; RV64I-NEXT: bltu s3, a0, .LBB102_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB102_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: j .LBB102_1 ; RV64I-NEXT: j .LBB102_1
; RV64I-NEXT: .LBB102_4: # %atomicrmw.end ; RV64I-NEXT: .LBB102_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_release: ; RV64IA-LABEL: atomicrmw_umax_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB102_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB102_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a6) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: and a2, a3, a4 ; RV64IA-NEXT: and a6, a3, a4
; RV64IA-NEXT: mv a5, a3 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a2, a1, .LBB102_3 ; RV64IA-NEXT: bgeu a6, a1, .LBB102_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB102_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB102_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB102_3: # in Loop: Header=BB102_1 Depth=1 ; RV64IA-NEXT: .LBB102_3: # in Loop: Header=BB102_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a6) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB102_1 ; RV64IA-NEXT: bnez a5, .LBB102_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b release %1 = atomicrmw umax i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_acq_rel: ; RV32I-LABEL: atomicrmw_umax_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s2, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s3, s0, s2
; RV32I-NEXT: j .LBB103_2 ; RV32I-NEXT: j .LBB103_2
; RV32I-NEXT: .LBB103_1: # %atomicrmw.start ; RV32I-NEXT: .LBB103_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB103_4 ; RV32I-NEXT: bnez a0, .LBB103_4
; RV32I-NEXT: .LBB103_2: # %atomicrmw.start ; RV32I-NEXT: .LBB103_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB103_1 ; RV32I-NEXT: bltu s3, a0, .LBB103_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: j .LBB103_1 ; RV32I-NEXT: j .LBB103_1
; RV32I-NEXT: .LBB103_4: # %atomicrmw.end ; RV32I-NEXT: .LBB103_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_umax_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB103_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB103_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a6) ; RV32IA-NEXT: lr.w.aq a3, (a2)
; RV32IA-NEXT: and a2, a3, a4 ; RV32IA-NEXT: and a6, a3, a4
; RV32IA-NEXT: mv a5, a3 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a2, a1, .LBB103_3 ; RV32IA-NEXT: bgeu a6, a1, .LBB103_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB103_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB103_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB103_3: # in Loop: Header=BB103_1 Depth=1 ; RV32IA-NEXT: .LBB103_3: # in Loop: Header=BB103_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a6) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB103_1 ; RV32IA-NEXT: bnez a5, .LBB103_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_acq_rel: ; RV64I-LABEL: atomicrmw_umax_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s2, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB103_2 ; RV64I-NEXT: j .LBB103_2
; RV64I-NEXT: .LBB103_1: # %atomicrmw.start ; RV64I-NEXT: .LBB103_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB103_4 ; RV64I-NEXT: bnez a0, .LBB103_4
; RV64I-NEXT: .LBB103_2: # %atomicrmw.start ; RV64I-NEXT: .LBB103_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB103_1 ; RV64I-NEXT: bltu s3, a0, .LBB103_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB103_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: j .LBB103_1 ; RV64I-NEXT: j .LBB103_1
; RV64I-NEXT: .LBB103_4: # %atomicrmw.end ; RV64I-NEXT: .LBB103_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_umax_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB103_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB103_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a6) ; RV64IA-NEXT: lr.w.aq a3, (a2)
; RV64IA-NEXT: and a2, a3, a4 ; RV64IA-NEXT: and a6, a3, a4
; RV64IA-NEXT: mv a5, a3 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a2, a1, .LBB103_3 ; RV64IA-NEXT: bgeu a6, a1, .LBB103_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB103_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB103_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB103_3: # in Loop: Header=BB103_1 Depth=1 ; RV64IA-NEXT: .LBB103_3: # in Loop: Header=BB103_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a6) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB103_1 ; RV64IA-NEXT: bnez a5, .LBB103_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b acq_rel %1 = atomicrmw umax i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_seq_cst: ; RV32I-LABEL: atomicrmw_umax_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s2, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s3, s0, s2
; RV32I-NEXT: j .LBB104_2 ; RV32I-NEXT: j .LBB104_2
; RV32I-NEXT: .LBB104_1: # %atomicrmw.start ; RV32I-NEXT: .LBB104_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a4, 5
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB104_4 ; RV32I-NEXT: bnez a0, .LBB104_4
; RV32I-NEXT: .LBB104_2: # %atomicrmw.start ; RV32I-NEXT: .LBB104_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB104_1 ; RV32I-NEXT: bltu s3, a0, .LBB104_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: j .LBB104_1 ; RV32I-NEXT: j .LBB104_1
; RV32I-NEXT: .LBB104_4: # %atomicrmw.end ; RV32I-NEXT: .LBB104_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_umax_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB104_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB104_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a6) ; RV32IA-NEXT: lr.w.aqrl a3, (a2)
; RV32IA-NEXT: and a2, a3, a4 ; RV32IA-NEXT: and a6, a3, a4
; RV32IA-NEXT: mv a5, a3 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a2, a1, .LBB104_3 ; RV32IA-NEXT: bgeu a6, a1, .LBB104_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB104_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB104_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB104_3: # in Loop: Header=BB104_1 Depth=1 ; RV32IA-NEXT: .LBB104_3: # in Loop: Header=BB104_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a6) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB104_1 ; RV32IA-NEXT: bnez a5, .LBB104_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_seq_cst: ; RV64I-LABEL: atomicrmw_umax_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s2, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB104_2 ; RV64I-NEXT: j .LBB104_2
; RV64I-NEXT: .LBB104_1: # %atomicrmw.start ; RV64I-NEXT: .LBB104_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB104_4 ; RV64I-NEXT: bnez a0, .LBB104_4
; RV64I-NEXT: .LBB104_2: # %atomicrmw.start ; RV64I-NEXT: .LBB104_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB104_1 ; RV64I-NEXT: bltu s3, a0, .LBB104_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB104_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: j .LBB104_1 ; RV64I-NEXT: j .LBB104_1
; RV64I-NEXT: .LBB104_4: # %atomicrmw.end ; RV64I-NEXT: .LBB104_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_umax_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB104_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB104_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a6) ; RV64IA-NEXT: lr.w.aqrl a3, (a2)
; RV64IA-NEXT: and a2, a3, a4 ; RV64IA-NEXT: and a6, a3, a4
; RV64IA-NEXT: mv a5, a3 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a2, a1, .LBB104_3 ; RV64IA-NEXT: bgeu a6, a1, .LBB104_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB104_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB104_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB104_3: # in Loop: Header=BB104_1 Depth=1 ; RV64IA-NEXT: .LBB104_3: # in Loop: Header=BB104_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a6) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB104_1 ; RV64IA-NEXT: bnez a5, .LBB104_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b seq_cst %1 = atomicrmw umax i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_monotonic: ; RV32I-LABEL: atomicrmw_umin_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s2, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s3, s0, s2
; RV32I-NEXT: j .LBB105_2 ; RV32I-NEXT: j .LBB105_2
; RV32I-NEXT: .LBB105_1: # %atomicrmw.start ; RV32I-NEXT: .LBB105_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB105_4 ; RV32I-NEXT: bnez a0, .LBB105_4
; RV32I-NEXT: .LBB105_2: # %atomicrmw.start ; RV32I-NEXT: .LBB105_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB105_1 ; RV32I-NEXT: bgeu s3, a0, .LBB105_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: j .LBB105_1 ; RV32I-NEXT: j .LBB105_1
; RV32I-NEXT: .LBB105_4: # %atomicrmw.end ; RV32I-NEXT: .LBB105_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_monotonic: ; RV32IA-LABEL: atomicrmw_umin_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB105_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB105_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a6) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: and a2, a3, a4 ; RV32IA-NEXT: and a6, a3, a4
; RV32IA-NEXT: mv a5, a3 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a1, a2, .LBB105_3 ; RV32IA-NEXT: bgeu a1, a6, .LBB105_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB105_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB105_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB105_3: # in Loop: Header=BB105_1 Depth=1 ; RV32IA-NEXT: .LBB105_3: # in Loop: Header=BB105_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a6) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB105_1 ; RV32IA-NEXT: bnez a5, .LBB105_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_monotonic: ; RV64I-LABEL: atomicrmw_umin_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s2, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB105_2 ; RV64I-NEXT: j .LBB105_2
; RV64I-NEXT: .LBB105_1: # %atomicrmw.start ; RV64I-NEXT: .LBB105_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB105_4 ; RV64I-NEXT: bnez a0, .LBB105_4
; RV64I-NEXT: .LBB105_2: # %atomicrmw.start ; RV64I-NEXT: .LBB105_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB105_1 ; RV64I-NEXT: bgeu s3, a0, .LBB105_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB105_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: j .LBB105_1 ; RV64I-NEXT: j .LBB105_1
; RV64I-NEXT: .LBB105_4: # %atomicrmw.end ; RV64I-NEXT: .LBB105_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_monotonic: ; RV64IA-LABEL: atomicrmw_umin_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB105_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB105_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a6) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: and a2, a3, a4 ; RV64IA-NEXT: and a6, a3, a4
; RV64IA-NEXT: mv a5, a3 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a1, a2, .LBB105_3 ; RV64IA-NEXT: bgeu a1, a6, .LBB105_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB105_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB105_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB105_3: # in Loop: Header=BB105_1 Depth=1 ; RV64IA-NEXT: .LBB105_3: # in Loop: Header=BB105_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a6) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB105_1 ; RV64IA-NEXT: bnez a5, .LBB105_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b monotonic %1 = atomicrmw umin i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_acquire: ; RV32I-LABEL: atomicrmw_umin_i16_acquire:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s2, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s3, s0, s2
; RV32I-NEXT: j .LBB106_2 ; RV32I-NEXT: j .LBB106_2
; RV32I-NEXT: .LBB106_1: # %atomicrmw.start ; RV32I-NEXT: .LBB106_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: li a3, 2 ; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB106_4 ; RV32I-NEXT: bnez a0, .LBB106_4
; RV32I-NEXT: .LBB106_2: # %atomicrmw.start ; RV32I-NEXT: .LBB106_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB106_1 ; RV32I-NEXT: bgeu s3, a0, .LBB106_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: j .LBB106_1 ; RV32I-NEXT: j .LBB106_1
; RV32I-NEXT: .LBB106_4: # %atomicrmw.end ; RV32I-NEXT: .LBB106_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_acquire: ; RV32IA-LABEL: atomicrmw_umin_i16_acquire:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB106_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB106_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a6) ; RV32IA-NEXT: lr.w.aq a3, (a2)
; RV32IA-NEXT: and a2, a3, a4 ; RV32IA-NEXT: and a6, a3, a4
; RV32IA-NEXT: mv a5, a3 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a1, a2, .LBB106_3 ; RV32IA-NEXT: bgeu a1, a6, .LBB106_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB106_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB106_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB106_3: # in Loop: Header=BB106_1 Depth=1 ; RV32IA-NEXT: .LBB106_3: # in Loop: Header=BB106_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a6) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB106_1 ; RV32IA-NEXT: bnez a5, .LBB106_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_acquire: ; RV64I-LABEL: atomicrmw_umin_i16_acquire:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s2, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB106_2 ; RV64I-NEXT: j .LBB106_2
; RV64I-NEXT: .LBB106_1: # %atomicrmw.start ; RV64I-NEXT: .LBB106_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB106_4 ; RV64I-NEXT: bnez a0, .LBB106_4
; RV64I-NEXT: .LBB106_2: # %atomicrmw.start ; RV64I-NEXT: .LBB106_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB106_1 ; RV64I-NEXT: bgeu s3, a0, .LBB106_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB106_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: j .LBB106_1 ; RV64I-NEXT: j .LBB106_1
; RV64I-NEXT: .LBB106_4: # %atomicrmw.end ; RV64I-NEXT: .LBB106_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_acquire: ; RV64IA-LABEL: atomicrmw_umin_i16_acquire:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB106_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB106_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a6) ; RV64IA-NEXT: lr.w.aq a3, (a2)
; RV64IA-NEXT: and a2, a3, a4 ; RV64IA-NEXT: and a6, a3, a4
; RV64IA-NEXT: mv a5, a3 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a1, a2, .LBB106_3 ; RV64IA-NEXT: bgeu a1, a6, .LBB106_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB106_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB106_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB106_3: # in Loop: Header=BB106_1 Depth=1 ; RV64IA-NEXT: .LBB106_3: # in Loop: Header=BB106_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a6) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB106_1 ; RV64IA-NEXT: bnez a5, .LBB106_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b acquire %1 = atomicrmw umin i16* %a, i16 %b acquire
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_release: ; RV32I-LABEL: atomicrmw_umin_i16_release:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s2, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s3, s0, s2
; RV32I-NEXT: j .LBB107_2 ; RV32I-NEXT: j .LBB107_2
; RV32I-NEXT: .LBB107_1: # %atomicrmw.start ; RV32I-NEXT: .LBB107_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: li a3, 3 ; RV32I-NEXT: li a3, 3
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB107_4 ; RV32I-NEXT: bnez a0, .LBB107_4
; RV32I-NEXT: .LBB107_2: # %atomicrmw.start ; RV32I-NEXT: .LBB107_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB107_1 ; RV32I-NEXT: bgeu s3, a0, .LBB107_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: j .LBB107_1 ; RV32I-NEXT: j .LBB107_1
; RV32I-NEXT: .LBB107_4: # %atomicrmw.end ; RV32I-NEXT: .LBB107_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_release: ; RV32IA-LABEL: atomicrmw_umin_i16_release:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB107_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB107_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a6) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: and a2, a3, a4 ; RV32IA-NEXT: and a6, a3, a4
; RV32IA-NEXT: mv a5, a3 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a1, a2, .LBB107_3 ; RV32IA-NEXT: bgeu a1, a6, .LBB107_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB107_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB107_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB107_3: # in Loop: Header=BB107_1 Depth=1 ; RV32IA-NEXT: .LBB107_3: # in Loop: Header=BB107_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a6) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB107_1 ; RV32IA-NEXT: bnez a5, .LBB107_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_release: ; RV64I-LABEL: atomicrmw_umin_i16_release:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s2, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB107_2 ; RV64I-NEXT: j .LBB107_2
; RV64I-NEXT: .LBB107_1: # %atomicrmw.start ; RV64I-NEXT: .LBB107_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB107_4 ; RV64I-NEXT: bnez a0, .LBB107_4
; RV64I-NEXT: .LBB107_2: # %atomicrmw.start ; RV64I-NEXT: .LBB107_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB107_1 ; RV64I-NEXT: bgeu s3, a0, .LBB107_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB107_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: j .LBB107_1 ; RV64I-NEXT: j .LBB107_1
; RV64I-NEXT: .LBB107_4: # %atomicrmw.end ; RV64I-NEXT: .LBB107_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_release: ; RV64IA-LABEL: atomicrmw_umin_i16_release:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB107_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB107_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a6) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: and a2, a3, a4 ; RV64IA-NEXT: and a6, a3, a4
; RV64IA-NEXT: mv a5, a3 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a1, a2, .LBB107_3 ; RV64IA-NEXT: bgeu a1, a6, .LBB107_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB107_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB107_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB107_3: # in Loop: Header=BB107_1 Depth=1 ; RV64IA-NEXT: .LBB107_3: # in Loop: Header=BB107_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a6) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB107_1 ; RV64IA-NEXT: bnez a5, .LBB107_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b release %1 = atomicrmw umin i16* %a, i16 %b release
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_acq_rel: ; RV32I-LABEL: atomicrmw_umin_i16_acq_rel:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s2, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s3, s0, s2
; RV32I-NEXT: j .LBB108_2 ; RV32I-NEXT: j .LBB108_2
; RV32I-NEXT: .LBB108_1: # %atomicrmw.start ; RV32I-NEXT: .LBB108_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: li a3, 4 ; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2 ; RV32I-NEXT: li a4, 2
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB108_4 ; RV32I-NEXT: bnez a0, .LBB108_4
; RV32I-NEXT: .LBB108_2: # %atomicrmw.start ; RV32I-NEXT: .LBB108_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB108_1 ; RV32I-NEXT: bgeu s3, a0, .LBB108_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: j .LBB108_1 ; RV32I-NEXT: j .LBB108_1
; RV32I-NEXT: .LBB108_4: # %atomicrmw.end ; RV32I-NEXT: .LBB108_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_acq_rel: ; RV32IA-LABEL: atomicrmw_umin_i16_acq_rel:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB108_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB108_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aq a3, (a6) ; RV32IA-NEXT: lr.w.aq a3, (a2)
; RV32IA-NEXT: and a2, a3, a4 ; RV32IA-NEXT: and a6, a3, a4
; RV32IA-NEXT: mv a5, a3 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a1, a2, .LBB108_3 ; RV32IA-NEXT: bgeu a1, a6, .LBB108_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB108_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB108_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB108_3: # in Loop: Header=BB108_1 Depth=1 ; RV32IA-NEXT: .LBB108_3: # in Loop: Header=BB108_1 Depth=1
; RV32IA-NEXT: sc.w.rl a5, a5, (a6) ; RV32IA-NEXT: sc.w.rl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB108_1 ; RV32IA-NEXT: bnez a5, .LBB108_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_acq_rel: ; RV64I-LABEL: atomicrmw_umin_i16_acq_rel:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s2, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB108_2 ; RV64I-NEXT: j .LBB108_2
; RV64I-NEXT: .LBB108_1: # %atomicrmw.start ; RV64I-NEXT: .LBB108_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB108_4 ; RV64I-NEXT: bnez a0, .LBB108_4
; RV64I-NEXT: .LBB108_2: # %atomicrmw.start ; RV64I-NEXT: .LBB108_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB108_1 ; RV64I-NEXT: bgeu s3, a0, .LBB108_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB108_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: j .LBB108_1 ; RV64I-NEXT: j .LBB108_1
; RV64I-NEXT: .LBB108_4: # %atomicrmw.end ; RV64I-NEXT: .LBB108_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_acq_rel: ; RV64IA-LABEL: atomicrmw_umin_i16_acq_rel:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB108_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB108_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aq a3, (a6) ; RV64IA-NEXT: lr.w.aq a3, (a2)
; RV64IA-NEXT: and a2, a3, a4 ; RV64IA-NEXT: and a6, a3, a4
; RV64IA-NEXT: mv a5, a3 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a1, a2, .LBB108_3 ; RV64IA-NEXT: bgeu a1, a6, .LBB108_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB108_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB108_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB108_3: # in Loop: Header=BB108_1 Depth=1 ; RV64IA-NEXT: .LBB108_3: # in Loop: Header=BB108_1 Depth=1
; RV64IA-NEXT: sc.w.rl a5, a5, (a6) ; RV64IA-NEXT: sc.w.rl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB108_1 ; RV64IA-NEXT: bnez a5, .LBB108_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b acq_rel %1 = atomicrmw umin i16* %a, i16 %b acq_rel
ret i16 %1 ret i16 %1
} }
define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind { define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_seq_cst: ; RV32I-LABEL: atomicrmw_umin_i16_seq_cst:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s2, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s3, s0, s2
; RV32I-NEXT: j .LBB109_2 ; RV32I-NEXT: j .LBB109_2
; RV32I-NEXT: .LBB109_1: # %atomicrmw.start ; RV32I-NEXT: .LBB109_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: li a3, 5 ; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5 ; RV32I-NEXT: li a4, 5
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB109_4 ; RV32I-NEXT: bnez a0, .LBB109_4
; RV32I-NEXT: .LBB109_2: # %atomicrmw.start ; RV32I-NEXT: .LBB109_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB109_1 ; RV32I-NEXT: bgeu s3, a0, .LBB109_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: j .LBB109_1 ; RV32I-NEXT: j .LBB109_1
; RV32I-NEXT: .LBB109_4: # %atomicrmw.end ; RV32I-NEXT: .LBB109_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_seq_cst: ; RV32IA-LABEL: atomicrmw_umin_i16_seq_cst:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB109_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB109_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w.aqrl a3, (a6) ; RV32IA-NEXT: lr.w.aqrl a3, (a2)
; RV32IA-NEXT: and a2, a3, a4 ; RV32IA-NEXT: and a6, a3, a4
; RV32IA-NEXT: mv a5, a3 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a1, a2, .LBB109_3 ; RV32IA-NEXT: bgeu a1, a6, .LBB109_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB109_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB109_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB109_3: # in Loop: Header=BB109_1 Depth=1 ; RV32IA-NEXT: .LBB109_3: # in Loop: Header=BB109_1 Depth=1
; RV32IA-NEXT: sc.w.aqrl a5, a5, (a6) ; RV32IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB109_1 ; RV32IA-NEXT: bnez a5, .LBB109_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_seq_cst: ; RV64I-LABEL: atomicrmw_umin_i16_seq_cst:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s2, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB109_2 ; RV64I-NEXT: j .LBB109_2
; RV64I-NEXT: .LBB109_1: # %atomicrmw.start ; RV64I-NEXT: .LBB109_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB109_4 ; RV64I-NEXT: bnez a0, .LBB109_4
; RV64I-NEXT: .LBB109_2: # %atomicrmw.start ; RV64I-NEXT: .LBB109_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB109_1 ; RV64I-NEXT: bgeu s3, a0, .LBB109_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB109_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: j .LBB109_1 ; RV64I-NEXT: j .LBB109_1
; RV64I-NEXT: .LBB109_4: # %atomicrmw.end ; RV64I-NEXT: .LBB109_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_seq_cst: ; RV64IA-LABEL: atomicrmw_umin_i16_seq_cst:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB109_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB109_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w.aqrl a3, (a6) ; RV64IA-NEXT: lr.w.aqrl a3, (a2)
; RV64IA-NEXT: and a2, a3, a4 ; RV64IA-NEXT: and a6, a3, a4
; RV64IA-NEXT: mv a5, a3 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a1, a2, .LBB109_3 ; RV64IA-NEXT: bgeu a1, a6, .LBB109_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB109_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB109_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB109_3: # in Loop: Header=BB109_1 Depth=1 ; RV64IA-NEXT: .LBB109_3: # in Loop: Header=BB109_1 Depth=1
; RV64IA-NEXT: sc.w.aqrl a5, a5, (a6) ; RV64IA-NEXT: sc.w.aqrl a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB109_1 ; RV64IA-NEXT: bnez a5, .LBB109_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b seq_cst %1 = atomicrmw umin i16* %a, i16 %b seq_cst
ret i16 %1 ret i16 %1
} }
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB145_2 ; RV64I-NEXT: j .LBB145_2
; RV64I-NEXT: .LBB145_1: # %atomicrmw.start ; RV64I-NEXT: .LBB145_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB145_4 ; RV64I-NEXT: bnez a0, .LBB145_4
; RV64I-NEXT: .LBB145_2: # %atomicrmw.start ; RV64I-NEXT: .LBB145_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a3, .LBB145_1 ; RV64I-NEXT: blt s2, a3, .LBB145_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB145_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB145_1 ; RV64I-NEXT: j .LBB145_1
; RV64I-NEXT: .LBB145_4: # %atomicrmw.end ; RV64I-NEXT: .LBB145_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB146_2 ; RV64I-NEXT: j .LBB146_2
; RV64I-NEXT: .LBB146_1: # %atomicrmw.start ; RV64I-NEXT: .LBB146_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB146_4 ; RV64I-NEXT: bnez a0, .LBB146_4
; RV64I-NEXT: .LBB146_2: # %atomicrmw.start ; RV64I-NEXT: .LBB146_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a3, .LBB146_1 ; RV64I-NEXT: blt s2, a3, .LBB146_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB146_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB146_1 ; RV64I-NEXT: j .LBB146_1
; RV64I-NEXT: .LBB146_4: # %atomicrmw.end ; RV64I-NEXT: .LBB146_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB147_2 ; RV64I-NEXT: j .LBB147_2
; RV64I-NEXT: .LBB147_1: # %atomicrmw.start ; RV64I-NEXT: .LBB147_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB147_4 ; RV64I-NEXT: bnez a0, .LBB147_4
; RV64I-NEXT: .LBB147_2: # %atomicrmw.start ; RV64I-NEXT: .LBB147_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a3, .LBB147_1 ; RV64I-NEXT: blt s2, a3, .LBB147_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB147_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB147_1 ; RV64I-NEXT: j .LBB147_1
; RV64I-NEXT: .LBB147_4: # %atomicrmw.end ; RV64I-NEXT: .LBB147_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB148_2 ; RV64I-NEXT: j .LBB148_2
; RV64I-NEXT: .LBB148_1: # %atomicrmw.start ; RV64I-NEXT: .LBB148_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB148_4 ; RV64I-NEXT: bnez a0, .LBB148_4
; RV64I-NEXT: .LBB148_2: # %atomicrmw.start ; RV64I-NEXT: .LBB148_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a3, .LBB148_1 ; RV64I-NEXT: blt s2, a3, .LBB148_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB148_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB148_1 ; RV64I-NEXT: j .LBB148_1
; RV64I-NEXT: .LBB148_4: # %atomicrmw.end ; RV64I-NEXT: .LBB148_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB149_2 ; RV64I-NEXT: j .LBB149_2
; RV64I-NEXT: .LBB149_1: # %atomicrmw.start ; RV64I-NEXT: .LBB149_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB149_4 ; RV64I-NEXT: bnez a0, .LBB149_4
; RV64I-NEXT: .LBB149_2: # %atomicrmw.start ; RV64I-NEXT: .LBB149_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a3, .LBB149_1 ; RV64I-NEXT: blt s2, a3, .LBB149_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB149_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB149_1 ; RV64I-NEXT: j .LBB149_1
; RV64I-NEXT: .LBB149_4: # %atomicrmw.end ; RV64I-NEXT: .LBB149_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB150_2 ; RV64I-NEXT: j .LBB150_2
; RV64I-NEXT: .LBB150_1: # %atomicrmw.start ; RV64I-NEXT: .LBB150_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB150_4 ; RV64I-NEXT: bnez a0, .LBB150_4
; RV64I-NEXT: .LBB150_2: # %atomicrmw.start ; RV64I-NEXT: .LBB150_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a3, .LBB150_1 ; RV64I-NEXT: bge s2, a3, .LBB150_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB150_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB150_1 ; RV64I-NEXT: j .LBB150_1
; RV64I-NEXT: .LBB150_4: # %atomicrmw.end ; RV64I-NEXT: .LBB150_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB151_2 ; RV64I-NEXT: j .LBB151_2
; RV64I-NEXT: .LBB151_1: # %atomicrmw.start ; RV64I-NEXT: .LBB151_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB151_4 ; RV64I-NEXT: bnez a0, .LBB151_4
; RV64I-NEXT: .LBB151_2: # %atomicrmw.start ; RV64I-NEXT: .LBB151_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a3, .LBB151_1 ; RV64I-NEXT: bge s2, a3, .LBB151_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB151_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB151_1 ; RV64I-NEXT: j .LBB151_1
; RV64I-NEXT: .LBB151_4: # %atomicrmw.end ; RV64I-NEXT: .LBB151_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB152_2 ; RV64I-NEXT: j .LBB152_2
; RV64I-NEXT: .LBB152_1: # %atomicrmw.start ; RV64I-NEXT: .LBB152_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB152_4 ; RV64I-NEXT: bnez a0, .LBB152_4
; RV64I-NEXT: .LBB152_2: # %atomicrmw.start ; RV64I-NEXT: .LBB152_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a3, .LBB152_1 ; RV64I-NEXT: bge s2, a3, .LBB152_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB152_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB152_1 ; RV64I-NEXT: j .LBB152_1
; RV64I-NEXT: .LBB152_4: # %atomicrmw.end ; RV64I-NEXT: .LBB152_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB153_2 ; RV64I-NEXT: j .LBB153_2
; RV64I-NEXT: .LBB153_1: # %atomicrmw.start ; RV64I-NEXT: .LBB153_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB153_4 ; RV64I-NEXT: bnez a0, .LBB153_4
; RV64I-NEXT: .LBB153_2: # %atomicrmw.start ; RV64I-NEXT: .LBB153_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a3, .LBB153_1 ; RV64I-NEXT: bge s2, a3, .LBB153_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB153_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB153_1 ; RV64I-NEXT: j .LBB153_1
; RV64I-NEXT: .LBB153_4: # %atomicrmw.end ; RV64I-NEXT: .LBB153_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB154_2 ; RV64I-NEXT: j .LBB154_2
; RV64I-NEXT: .LBB154_1: # %atomicrmw.start ; RV64I-NEXT: .LBB154_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB154_4 ; RV64I-NEXT: bnez a0, .LBB154_4
; RV64I-NEXT: .LBB154_2: # %atomicrmw.start ; RV64I-NEXT: .LBB154_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a3, .LBB154_1 ; RV64I-NEXT: bge s2, a3, .LBB154_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB154_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB154_1 ; RV64I-NEXT: j .LBB154_1
; RV64I-NEXT: .LBB154_4: # %atomicrmw.end ; RV64I-NEXT: .LBB154_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB155_2 ; RV64I-NEXT: j .LBB155_2
; RV64I-NEXT: .LBB155_1: # %atomicrmw.start ; RV64I-NEXT: .LBB155_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB155_4 ; RV64I-NEXT: bnez a0, .LBB155_4
; RV64I-NEXT: .LBB155_2: # %atomicrmw.start ; RV64I-NEXT: .LBB155_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a3, .LBB155_1 ; RV64I-NEXT: bltu s2, a3, .LBB155_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB155_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB155_1 ; RV64I-NEXT: j .LBB155_1
; RV64I-NEXT: .LBB155_4: # %atomicrmw.end ; RV64I-NEXT: .LBB155_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB156_2 ; RV64I-NEXT: j .LBB156_2
; RV64I-NEXT: .LBB156_1: # %atomicrmw.start ; RV64I-NEXT: .LBB156_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB156_4 ; RV64I-NEXT: bnez a0, .LBB156_4
; RV64I-NEXT: .LBB156_2: # %atomicrmw.start ; RV64I-NEXT: .LBB156_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a3, .LBB156_1 ; RV64I-NEXT: bltu s2, a3, .LBB156_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB156_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB156_1 ; RV64I-NEXT: j .LBB156_1
; RV64I-NEXT: .LBB156_4: # %atomicrmw.end ; RV64I-NEXT: .LBB156_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB157_2 ; RV64I-NEXT: j .LBB157_2
; RV64I-NEXT: .LBB157_1: # %atomicrmw.start ; RV64I-NEXT: .LBB157_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB157_4 ; RV64I-NEXT: bnez a0, .LBB157_4
; RV64I-NEXT: .LBB157_2: # %atomicrmw.start ; RV64I-NEXT: .LBB157_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a3, .LBB157_1 ; RV64I-NEXT: bltu s2, a3, .LBB157_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB157_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB157_1 ; RV64I-NEXT: j .LBB157_1
; RV64I-NEXT: .LBB157_4: # %atomicrmw.end ; RV64I-NEXT: .LBB157_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB158_2 ; RV64I-NEXT: j .LBB158_2
; RV64I-NEXT: .LBB158_1: # %atomicrmw.start ; RV64I-NEXT: .LBB158_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB158_4 ; RV64I-NEXT: bnez a0, .LBB158_4
; RV64I-NEXT: .LBB158_2: # %atomicrmw.start ; RV64I-NEXT: .LBB158_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a3, .LBB158_1 ; RV64I-NEXT: bltu s2, a3, .LBB158_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB158_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB158_1 ; RV64I-NEXT: j .LBB158_1
; RV64I-NEXT: .LBB158_4: # %atomicrmw.end ; RV64I-NEXT: .LBB158_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB159_2 ; RV64I-NEXT: j .LBB159_2
; RV64I-NEXT: .LBB159_1: # %atomicrmw.start ; RV64I-NEXT: .LBB159_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB159_4 ; RV64I-NEXT: bnez a0, .LBB159_4
; RV64I-NEXT: .LBB159_2: # %atomicrmw.start ; RV64I-NEXT: .LBB159_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a3, .LBB159_1 ; RV64I-NEXT: bltu s2, a3, .LBB159_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB159_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB159_1 ; RV64I-NEXT: j .LBB159_1
; RV64I-NEXT: .LBB159_4: # %atomicrmw.end ; RV64I-NEXT: .LBB159_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB160_2 ; RV64I-NEXT: j .LBB160_2
; RV64I-NEXT: .LBB160_1: # %atomicrmw.start ; RV64I-NEXT: .LBB160_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB160_4 ; RV64I-NEXT: bnez a0, .LBB160_4
; RV64I-NEXT: .LBB160_2: # %atomicrmw.start ; RV64I-NEXT: .LBB160_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a3, .LBB160_1 ; RV64I-NEXT: bgeu s2, a3, .LBB160_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB160_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB160_1 ; RV64I-NEXT: j .LBB160_1
; RV64I-NEXT: .LBB160_4: # %atomicrmw.end ; RV64I-NEXT: .LBB160_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB161_2 ; RV64I-NEXT: j .LBB161_2
; RV64I-NEXT: .LBB161_1: # %atomicrmw.start ; RV64I-NEXT: .LBB161_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 2 ; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB161_4 ; RV64I-NEXT: bnez a0, .LBB161_4
; RV64I-NEXT: .LBB161_2: # %atomicrmw.start ; RV64I-NEXT: .LBB161_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a3, .LBB161_1 ; RV64I-NEXT: bgeu s2, a3, .LBB161_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB161_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB161_1 ; RV64I-NEXT: j .LBB161_1
; RV64I-NEXT: .LBB161_4: # %atomicrmw.end ; RV64I-NEXT: .LBB161_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB162_2 ; RV64I-NEXT: j .LBB162_2
; RV64I-NEXT: .LBB162_1: # %atomicrmw.start ; RV64I-NEXT: .LBB162_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 3 ; RV64I-NEXT: li a3, 3
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB162_4 ; RV64I-NEXT: bnez a0, .LBB162_4
; RV64I-NEXT: .LBB162_2: # %atomicrmw.start ; RV64I-NEXT: .LBB162_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a3, .LBB162_1 ; RV64I-NEXT: bgeu s2, a3, .LBB162_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB162_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB162_1 ; RV64I-NEXT: j .LBB162_1
; RV64I-NEXT: .LBB162_4: # %atomicrmw.end ; RV64I-NEXT: .LBB162_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB163_2 ; RV64I-NEXT: j .LBB163_2
; RV64I-NEXT: .LBB163_1: # %atomicrmw.start ; RV64I-NEXT: .LBB163_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 4 ; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2 ; RV64I-NEXT: li a4, 2
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB163_4 ; RV64I-NEXT: bnez a0, .LBB163_4
; RV64I-NEXT: .LBB163_2: # %atomicrmw.start ; RV64I-NEXT: .LBB163_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a3, .LBB163_1 ; RV64I-NEXT: bgeu s2, a3, .LBB163_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB163_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB163_1 ; RV64I-NEXT: j .LBB163_1
; RV64I-NEXT: .LBB163_4: # %atomicrmw.end ; RV64I-NEXT: .LBB163_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB164_2 ; RV64I-NEXT: j .LBB164_2
; RV64I-NEXT: .LBB164_1: # %atomicrmw.start ; RV64I-NEXT: .LBB164_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: li a3, 5 ; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5 ; RV64I-NEXT: li a4, 5
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB164_4 ; RV64I-NEXT: bnez a0, .LBB164_4
; RV64I-NEXT: .LBB164_2: # %atomicrmw.start ; RV64I-NEXT: .LBB164_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a3, .LBB164_1 ; RV64I-NEXT: bgeu s2, a3, .LBB164_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB164_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB164_1 ; RV64I-NEXT: j .LBB164_1
; RV64I-NEXT: .LBB164_4: # %atomicrmw.end ; RV64I-NEXT: .LBB164_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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llvm/test/CodeGen/RISCV/atomic-signext.ll

Show First 20 Lines • Show All 578 Lines • ▼ Show 20 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s2, a0, 24
; RV32I-NEXT: j .LBB10_2 ; RV32I-NEXT: j .LBB10_2
; RV32I-NEXT: .LBB10_1: # %atomicrmw.start ; RV32I-NEXT: .LBB10_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB10_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB10_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB10_4 ; RV32I-NEXT: bnez a0, .LBB10_4
; RV32I-NEXT: .LBB10_2: # %atomicrmw.start ; RV32I-NEXT: .LBB10_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB10_1 ; RV32I-NEXT: blt s2, a0, .LBB10_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB10_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB10_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB10_1 ; RV32I-NEXT: j .LBB10_1
; RV32I-NEXT: .LBB10_4: # %atomicrmw.end ; RV32I-NEXT: .LBB10_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i8_monotonic: ; RV32IA-LABEL: atomicrmw_max_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: li a4, 255 ; RV32IA-NEXT: li a4, 255
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 24 ; RV32IA-NEXT: li a5, 24
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a6) ; RV32IA-NEXT: lr.w a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a4, a1, .LBB10_3 ; RV32IA-NEXT: bge a7, a1, .LBB10_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB10_3: # in Loop: Header=BB10_1 Depth=1 ; RV32IA-NEXT: .LBB10_3: # in Loop: Header=BB10_1 Depth=1
; RV32IA-NEXT: sc.w a2, a2, (a6) ; RV32IA-NEXT: sc.w a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB10_1 ; RV32IA-NEXT: bnez a6, .LBB10_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: slli a0, a0, 24 ; RV32IA-NEXT: slli a0, a0, 24
; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i8_monotonic: ; RV64I-LABEL: atomicrmw_max_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s2, a0, 56
; RV64I-NEXT: j .LBB10_2 ; RV64I-NEXT: j .LBB10_2
; RV64I-NEXT: .LBB10_1: # %atomicrmw.start ; RV64I-NEXT: .LBB10_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB10_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB10_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB10_4 ; RV64I-NEXT: bnez a0, .LBB10_4
; RV64I-NEXT: .LBB10_2: # %atomicrmw.start ; RV64I-NEXT: .LBB10_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB10_1 ; RV64I-NEXT: blt s2, a0, .LBB10_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB10_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB10_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB10_1 ; RV64I-NEXT: j .LBB10_1
; RV64I-NEXT: .LBB10_4: # %atomicrmw.end ; RV64I-NEXT: .LBB10_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i8_monotonic: ; RV64IA-LABEL: atomicrmw_max_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255 ; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 56 ; RV64IA-NEXT: li a5, 56
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6) ; RV64IA-NEXT: lr.w a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a4, a1, .LBB10_3 ; RV64IA-NEXT: bge a7, a1, .LBB10_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB10_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB10_3: # in Loop: Header=BB10_1 Depth=1 ; RV64IA-NEXT: .LBB10_3: # in Loop: Header=BB10_1 Depth=1
; RV64IA-NEXT: sc.w a2, a2, (a6) ; RV64IA-NEXT: sc.w a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB10_1 ; RV64IA-NEXT: bnez a6, .LBB10_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i8* %a, i8 %b monotonic %1 = atomicrmw max i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define signext i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind { define signext i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_monotonic: ; RV32I-LABEL: atomicrmw_min_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 24 ; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai s1, a0, 24 ; RV32I-NEXT: srai s2, a0, 24
; RV32I-NEXT: j .LBB11_2 ; RV32I-NEXT: j .LBB11_2
; RV32I-NEXT: .LBB11_1: # %atomicrmw.start ; RV32I-NEXT: .LBB11_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB11_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB11_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB11_4 ; RV32I-NEXT: bnez a0, .LBB11_4
; RV32I-NEXT: .LBB11_2: # %atomicrmw.start ; RV32I-NEXT: .LBB11_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB11_1 ; RV32I-NEXT: bge s2, a0, .LBB11_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB11_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB11_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB11_1 ; RV32I-NEXT: j .LBB11_1
; RV32I-NEXT: .LBB11_4: # %atomicrmw.end ; RV32I-NEXT: .LBB11_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i8_monotonic: ; RV32IA-LABEL: atomicrmw_min_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: li a4, 255 ; RV32IA-NEXT: li a4, 255
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 24 ; RV32IA-NEXT: slli a1, a1, 24
; RV32IA-NEXT: srai a1, a1, 24 ; RV32IA-NEXT: srai a1, a1, 24
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 24 ; RV32IA-NEXT: li a5, 24
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a6) ; RV32IA-NEXT: lr.w a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a1, a4, .LBB11_3 ; RV32IA-NEXT: bge a1, a7, .LBB11_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB11_3: # in Loop: Header=BB11_1 Depth=1 ; RV32IA-NEXT: .LBB11_3: # in Loop: Header=BB11_1 Depth=1
; RV32IA-NEXT: sc.w a2, a2, (a6) ; RV32IA-NEXT: sc.w a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB11_1 ; RV32IA-NEXT: bnez a6, .LBB11_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: slli a0, a0, 24 ; RV32IA-NEXT: slli a0, a0, 24
; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i8_monotonic: ; RV64I-LABEL: atomicrmw_min_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 56 ; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai s1, a0, 56 ; RV64I-NEXT: srai s2, a0, 56
; RV64I-NEXT: j .LBB11_2 ; RV64I-NEXT: j .LBB11_2
; RV64I-NEXT: .LBB11_1: # %atomicrmw.start ; RV64I-NEXT: .LBB11_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB11_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB11_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB11_4 ; RV64I-NEXT: bnez a0, .LBB11_4
; RV64I-NEXT: .LBB11_2: # %atomicrmw.start ; RV64I-NEXT: .LBB11_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB11_1 ; RV64I-NEXT: bge s2, a0, .LBB11_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB11_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB11_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB11_1 ; RV64I-NEXT: j .LBB11_1
; RV64I-NEXT: .LBB11_4: # %atomicrmw.end ; RV64I-NEXT: .LBB11_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i8_monotonic: ; RV64IA-LABEL: atomicrmw_min_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: li a4, 255 ; RV64IA-NEXT: li a4, 255
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 56 ; RV64IA-NEXT: slli a1, a1, 56
; RV64IA-NEXT: srai a1, a1, 56 ; RV64IA-NEXT: srai a1, a1, 56
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 56 ; RV64IA-NEXT: li a5, 56
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6) ; RV64IA-NEXT: lr.w a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a1, a4, .LBB11_3 ; RV64IA-NEXT: bge a1, a7, .LBB11_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB11_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB11_3: # in Loop: Header=BB11_1 Depth=1 ; RV64IA-NEXT: .LBB11_3: # in Loop: Header=BB11_1 Depth=1
; RV64IA-NEXT: sc.w a2, a2, (a6) ; RV64IA-NEXT: sc.w a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB11_1 ; RV64IA-NEXT: bnez a6, .LBB11_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i8* %a, i8 %b monotonic %1 = atomicrmw min i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define signext i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind { define signext i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_monotonic: ; RV32I-LABEL: atomicrmw_umax_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s2, a1, 255
; RV32I-NEXT: j .LBB12_2 ; RV32I-NEXT: j .LBB12_2
; RV32I-NEXT: .LBB12_1: # %atomicrmw.start ; RV32I-NEXT: .LBB12_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB12_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB12_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB12_4 ; RV32I-NEXT: bnez a0, .LBB12_4
; RV32I-NEXT: .LBB12_2: # %atomicrmw.start ; RV32I-NEXT: .LBB12_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bltu s1, a0, .LBB12_1 ; RV32I-NEXT: bltu s2, a0, .LBB12_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB12_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB12_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB12_1 ; RV32I-NEXT: j .LBB12_1
; RV32I-NEXT: .LBB12_4: # %atomicrmw.end ; RV32I-NEXT: .LBB12_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i8_monotonic: ; RV32IA-LABEL: atomicrmw_umax_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: li a3, 255 ; RV32IA-NEXT: li a3, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a6) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: and a2, a4, a3 ; RV32IA-NEXT: and a6, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a2, a1, .LBB12_3 ; RV32IA-NEXT: bgeu a6, a1, .LBB12_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB12_3: # in Loop: Header=BB12_1 Depth=1 ; RV32IA-NEXT: .LBB12_3: # in Loop: Header=BB12_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a6) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB12_1 ; RV32IA-NEXT: bnez a5, .LBB12_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: slli a0, a0, 24 ; RV32IA-NEXT: slli a0, a0, 24
; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i8_monotonic: ; RV64I-LABEL: atomicrmw_umax_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s2, a1, 255
; RV64I-NEXT: j .LBB12_2 ; RV64I-NEXT: j .LBB12_2
; RV64I-NEXT: .LBB12_1: # %atomicrmw.start ; RV64I-NEXT: .LBB12_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB12_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB12_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB12_4 ; RV64I-NEXT: bnez a0, .LBB12_4
; RV64I-NEXT: .LBB12_2: # %atomicrmw.start ; RV64I-NEXT: .LBB12_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a0, .LBB12_1 ; RV64I-NEXT: bltu s2, a0, .LBB12_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB12_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB12_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB12_1 ; RV64I-NEXT: j .LBB12_1
; RV64I-NEXT: .LBB12_4: # %atomicrmw.end ; RV64I-NEXT: .LBB12_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i8_monotonic: ; RV64IA-LABEL: atomicrmw_umax_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: li a3, 255 ; RV64IA-NEXT: li a3, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a6) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: and a2, a4, a3 ; RV64IA-NEXT: and a6, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a2, a1, .LBB12_3 ; RV64IA-NEXT: bgeu a6, a1, .LBB12_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB12_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB12_3: # in Loop: Header=BB12_1 Depth=1 ; RV64IA-NEXT: .LBB12_3: # in Loop: Header=BB12_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a6) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB12_1 ; RV64IA-NEXT: bnez a5, .LBB12_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i8* %a, i8 %b monotonic %1 = atomicrmw umax i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
} }
define signext i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind { define signext i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_monotonic: ; RV32I-LABEL: atomicrmw_umin_i8_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lbu a3, 0(a0) ; RV32I-NEXT: lbu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: andi s1, a1, 255 ; RV32I-NEXT: andi s2, a1, 255
; RV32I-NEXT: j .LBB13_2 ; RV32I-NEXT: j .LBB13_2
; RV32I-NEXT: .LBB13_1: # %atomicrmw.start ; RV32I-NEXT: .LBB13_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB13_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB13_2 Depth=1
; RV32I-NEXT: sb a3, 15(sp) ; RV32I-NEXT: sb a3, 15(sp)
; RV32I-NEXT: addi a1, sp, 15 ; RV32I-NEXT: addi a1, sp, 15
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1@plt ; RV32I-NEXT: call __atomic_compare_exchange_1@plt
; RV32I-NEXT: lb a3, 15(sp) ; RV32I-NEXT: lb a3, 15(sp)
; RV32I-NEXT: bnez a0, .LBB13_4 ; RV32I-NEXT: bnez a0, .LBB13_4
; RV32I-NEXT: .LBB13_2: # %atomicrmw.start ; RV32I-NEXT: .LBB13_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: andi a0, a3, 255 ; RV32I-NEXT: andi a0, a3, 255
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bgeu s1, a0, .LBB13_1 ; RV32I-NEXT: bgeu s2, a0, .LBB13_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB13_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB13_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB13_1 ; RV32I-NEXT: j .LBB13_1
; RV32I-NEXT: .LBB13_4: # %atomicrmw.end ; RV32I-NEXT: .LBB13_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a3, 24 ; RV32I-NEXT: slli a0, a3, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i8_monotonic: ; RV32IA-LABEL: atomicrmw_umin_i8_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: li a3, 255 ; RV32IA-NEXT: li a3, 255
; RV32IA-NEXT: sll a3, a3, a0 ; RV32IA-NEXT: sll a3, a3, a0
; RV32IA-NEXT: andi a1, a1, 255 ; RV32IA-NEXT: andi a1, a1, 255
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a4, (a6) ; RV32IA-NEXT: lr.w a4, (a2)
; RV32IA-NEXT: and a2, a4, a3 ; RV32IA-NEXT: and a6, a4, a3
; RV32IA-NEXT: mv a5, a4 ; RV32IA-NEXT: mv a5, a4
; RV32IA-NEXT: bgeu a1, a2, .LBB13_3 ; RV32IA-NEXT: bgeu a1, a6, .LBB13_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1
; RV32IA-NEXT: xor a5, a4, a1 ; RV32IA-NEXT: xor a5, a4, a1
; RV32IA-NEXT: and a5, a5, a3 ; RV32IA-NEXT: and a5, a5, a3
; RV32IA-NEXT: xor a5, a4, a5 ; RV32IA-NEXT: xor a5, a4, a5
; RV32IA-NEXT: .LBB13_3: # in Loop: Header=BB13_1 Depth=1 ; RV32IA-NEXT: .LBB13_3: # in Loop: Header=BB13_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a6) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB13_1 ; RV32IA-NEXT: bnez a5, .LBB13_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a4, a0 ; RV32IA-NEXT: srl a0, a4, a0
; RV32IA-NEXT: slli a0, a0, 24 ; RV32IA-NEXT: slli a0, a0, 24
; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: srai a0, a0, 24
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i8_monotonic: ; RV64I-LABEL: atomicrmw_umin_i8_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lbu a3, 0(a0) ; RV64I-NEXT: lbu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: andi s1, a1, 255 ; RV64I-NEXT: andi s2, a1, 255
; RV64I-NEXT: j .LBB13_2 ; RV64I-NEXT: j .LBB13_2
; RV64I-NEXT: .LBB13_1: # %atomicrmw.start ; RV64I-NEXT: .LBB13_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB13_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB13_2 Depth=1
; RV64I-NEXT: sb a3, 15(sp) ; RV64I-NEXT: sb a3, 15(sp)
; RV64I-NEXT: addi a1, sp, 15 ; RV64I-NEXT: addi a1, sp, 15
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1@plt ; RV64I-NEXT: call __atomic_compare_exchange_1@plt
; RV64I-NEXT: lb a3, 15(sp) ; RV64I-NEXT: lb a3, 15(sp)
; RV64I-NEXT: bnez a0, .LBB13_4 ; RV64I-NEXT: bnez a0, .LBB13_4
; RV64I-NEXT: .LBB13_2: # %atomicrmw.start ; RV64I-NEXT: .LBB13_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: andi a0, a3, 255 ; RV64I-NEXT: andi a0, a3, 255
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a0, .LBB13_1 ; RV64I-NEXT: bgeu s2, a0, .LBB13_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB13_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB13_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB13_1 ; RV64I-NEXT: j .LBB13_1
; RV64I-NEXT: .LBB13_4: # %atomicrmw.end ; RV64I-NEXT: .LBB13_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a3, 56 ; RV64I-NEXT: slli a0, a3, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i8_monotonic: ; RV64IA-LABEL: atomicrmw_umin_i8_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: li a3, 255 ; RV64IA-NEXT: li a3, 255
; RV64IA-NEXT: sllw a3, a3, a0 ; RV64IA-NEXT: sllw a3, a3, a0
; RV64IA-NEXT: andi a1, a1, 255 ; RV64IA-NEXT: andi a1, a1, 255
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB13_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a4, (a6) ; RV64IA-NEXT: lr.w a4, (a2)
; RV64IA-NEXT: and a2, a4, a3 ; RV64IA-NEXT: and a6, a4, a3
; RV64IA-NEXT: mv a5, a4 ; RV64IA-NEXT: mv a5, a4
; RV64IA-NEXT: bgeu a1, a2, .LBB13_3 ; RV64IA-NEXT: bgeu a1, a6, .LBB13_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB13_1 Depth=1
; RV64IA-NEXT: xor a5, a4, a1 ; RV64IA-NEXT: xor a5, a4, a1
; RV64IA-NEXT: and a5, a5, a3 ; RV64IA-NEXT: and a5, a5, a3
; RV64IA-NEXT: xor a5, a4, a5 ; RV64IA-NEXT: xor a5, a4, a5
; RV64IA-NEXT: .LBB13_3: # in Loop: Header=BB13_1 Depth=1 ; RV64IA-NEXT: .LBB13_3: # in Loop: Header=BB13_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a6) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB13_1 ; RV64IA-NEXT: bnez a5, .LBB13_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a4, a0 ; RV64IA-NEXT: srlw a0, a4, a0
; RV64IA-NEXT: slli a0, a0, 56 ; RV64IA-NEXT: slli a0, a0, 56
; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: srai a0, a0, 56
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i8* %a, i8 %b monotonic %1 = atomicrmw umin i8* %a, i8 %b monotonic
ret i8 %1 ret i8 %1
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; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s2, a0, 16
; RV32I-NEXT: j .LBB21_2 ; RV32I-NEXT: j .LBB21_2
; RV32I-NEXT: .LBB21_1: # %atomicrmw.start ; RV32I-NEXT: .LBB21_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB21_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB21_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB21_4 ; RV32I-NEXT: bnez a0, .LBB21_4
; RV32I-NEXT: .LBB21_2: # %atomicrmw.start ; RV32I-NEXT: .LBB21_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: blt s1, a0, .LBB21_1 ; RV32I-NEXT: blt s2, a0, .LBB21_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB21_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB21_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB21_1 ; RV32I-NEXT: j .LBB21_1
; RV32I-NEXT: .LBB21_4: # %atomicrmw.end ; RV32I-NEXT: .LBB21_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_max_i16_monotonic: ; RV32IA-LABEL: atomicrmw_max_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 16 ; RV32IA-NEXT: li a5, 16
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a6) ; RV32IA-NEXT: lr.w a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a4, a1, .LBB21_3 ; RV32IA-NEXT: bge a7, a1, .LBB21_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB21_3: # in Loop: Header=BB21_1 Depth=1 ; RV32IA-NEXT: .LBB21_3: # in Loop: Header=BB21_1 Depth=1
; RV32IA-NEXT: sc.w a2, a2, (a6) ; RV32IA-NEXT: sc.w a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB21_1 ; RV32IA-NEXT: bnez a6, .LBB21_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: slli a0, a0, 16 ; RV32IA-NEXT: slli a0, a0, 16
; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_max_i16_monotonic: ; RV64I-LABEL: atomicrmw_max_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s2, a0, 48
; RV64I-NEXT: j .LBB21_2 ; RV64I-NEXT: j .LBB21_2
; RV64I-NEXT: .LBB21_1: # %atomicrmw.start ; RV64I-NEXT: .LBB21_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB21_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB21_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB21_4 ; RV64I-NEXT: bnez a0, .LBB21_4
; RV64I-NEXT: .LBB21_2: # %atomicrmw.start ; RV64I-NEXT: .LBB21_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a0, .LBB21_1 ; RV64I-NEXT: blt s2, a0, .LBB21_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB21_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB21_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB21_1 ; RV64I-NEXT: j .LBB21_1
; RV64I-NEXT: .LBB21_4: # %atomicrmw.end ; RV64I-NEXT: .LBB21_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_max_i16_monotonic: ; RV64IA-LABEL: atomicrmw_max_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 48 ; RV64IA-NEXT: li a5, 48
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6) ; RV64IA-NEXT: lr.w a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a4, a1, .LBB21_3 ; RV64IA-NEXT: bge a7, a1, .LBB21_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB21_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB21_3: # in Loop: Header=BB21_1 Depth=1 ; RV64IA-NEXT: .LBB21_3: # in Loop: Header=BB21_1 Depth=1
; RV64IA-NEXT: sc.w a2, a2, (a6) ; RV64IA-NEXT: sc.w a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB21_1 ; RV64IA-NEXT: bnez a6, .LBB21_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw max i16* %a, i16 %b monotonic %1 = atomicrmw max i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define signext i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind { define signext i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_monotonic: ; RV32I-LABEL: atomicrmw_min_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lhu a3, 0(a0) ; RV32I-NEXT: lhu a3, 0(a0)
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai s1, a0, 16 ; RV32I-NEXT: srai s2, a0, 16
; RV32I-NEXT: j .LBB22_2 ; RV32I-NEXT: j .LBB22_2
; RV32I-NEXT: .LBB22_1: # %atomicrmw.start ; RV32I-NEXT: .LBB22_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB22_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB22_2 Depth=1
; RV32I-NEXT: sh a3, 14(sp) ; RV32I-NEXT: sh a3, 14(sp)
; RV32I-NEXT: addi a1, sp, 14 ; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a3, 14(sp) ; RV32I-NEXT: lh a3, 14(sp)
; RV32I-NEXT: bnez a0, .LBB22_4 ; RV32I-NEXT: bnez a0, .LBB22_4
; RV32I-NEXT: .LBB22_2: # %atomicrmw.start ; RV32I-NEXT: .LBB22_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bge s1, a0, .LBB22_1 ; RV32I-NEXT: bge s2, a0, .LBB22_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB22_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB22_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB22_1 ; RV32I-NEXT: j .LBB22_1
; RV32I-NEXT: .LBB22_4: # %atomicrmw.end ; RV32I-NEXT: .LBB22_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a3, 16 ; RV32I-NEXT: slli a0, a3, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_min_i16_monotonic: ; RV32IA-LABEL: atomicrmw_min_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: andi a3, a0, 24 ; RV32IA-NEXT: andi a3, a0, 24
; RV32IA-NEXT: lui a4, 16 ; RV32IA-NEXT: lui a4, 16
; RV32IA-NEXT: addi a4, a4, -1 ; RV32IA-NEXT: addi a4, a4, -1
; RV32IA-NEXT: sll a7, a4, a0 ; RV32IA-NEXT: sll a4, a4, a0
; RV32IA-NEXT: slli a1, a1, 16 ; RV32IA-NEXT: slli a1, a1, 16
; RV32IA-NEXT: srai a1, a1, 16 ; RV32IA-NEXT: srai a1, a1, 16
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: li a5, 16 ; RV32IA-NEXT: li a5, 16
; RV32IA-NEXT: sub a3, a5, a3 ; RV32IA-NEXT: sub a3, a5, a3
; RV32IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a5, (a6) ; RV32IA-NEXT: lr.w a5, (a2)
; RV32IA-NEXT: and a4, a5, a7 ; RV32IA-NEXT: and a7, a5, a4
; RV32IA-NEXT: mv a2, a5 ; RV32IA-NEXT: mv a6, a5
; RV32IA-NEXT: sll a4, a4, a3 ; RV32IA-NEXT: sll a7, a7, a3
; RV32IA-NEXT: sra a4, a4, a3 ; RV32IA-NEXT: sra a7, a7, a3
; RV32IA-NEXT: bge a1, a4, .LBB22_3 ; RV32IA-NEXT: bge a1, a7, .LBB22_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1
; RV32IA-NEXT: xor a2, a5, a1 ; RV32IA-NEXT: xor a6, a5, a1
; RV32IA-NEXT: and a2, a2, a7 ; RV32IA-NEXT: and a6, a6, a4
; RV32IA-NEXT: xor a2, a5, a2 ; RV32IA-NEXT: xor a6, a5, a6
; RV32IA-NEXT: .LBB22_3: # in Loop: Header=BB22_1 Depth=1 ; RV32IA-NEXT: .LBB22_3: # in Loop: Header=BB22_1 Depth=1
; RV32IA-NEXT: sc.w a2, a2, (a6) ; RV32IA-NEXT: sc.w a6, a6, (a2)
; RV32IA-NEXT: bnez a2, .LBB22_1 ; RV32IA-NEXT: bnez a6, .LBB22_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a5, a0 ; RV32IA-NEXT: srl a0, a5, a0
; RV32IA-NEXT: slli a0, a0, 16 ; RV32IA-NEXT: slli a0, a0, 16
; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_min_i16_monotonic: ; RV64I-LABEL: atomicrmw_min_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lhu a3, 0(a0) ; RV64I-NEXT: lhu a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai s1, a0, 48 ; RV64I-NEXT: srai s2, a0, 48
; RV64I-NEXT: j .LBB22_2 ; RV64I-NEXT: j .LBB22_2
; RV64I-NEXT: .LBB22_1: # %atomicrmw.start ; RV64I-NEXT: .LBB22_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB22_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB22_2 Depth=1
; RV64I-NEXT: sh a3, 14(sp) ; RV64I-NEXT: sh a3, 14(sp)
; RV64I-NEXT: addi a1, sp, 14 ; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a3, 14(sp) ; RV64I-NEXT: lh a3, 14(sp)
; RV64I-NEXT: bnez a0, .LBB22_4 ; RV64I-NEXT: bnez a0, .LBB22_4
; RV64I-NEXT: .LBB22_2: # %atomicrmw.start ; RV64I-NEXT: .LBB22_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a0, .LBB22_1 ; RV64I-NEXT: bge s2, a0, .LBB22_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB22_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB22_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB22_1 ; RV64I-NEXT: j .LBB22_1
; RV64I-NEXT: .LBB22_4: # %atomicrmw.end ; RV64I-NEXT: .LBB22_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a3, 48 ; RV64I-NEXT: slli a0, a3, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_min_i16_monotonic: ; RV64IA-LABEL: atomicrmw_min_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: andi a3, a0, 24 ; RV64IA-NEXT: andi a3, a0, 24
; RV64IA-NEXT: lui a4, 16 ; RV64IA-NEXT: lui a4, 16
; RV64IA-NEXT: addiw a4, a4, -1 ; RV64IA-NEXT: addiw a4, a4, -1
; RV64IA-NEXT: sllw a7, a4, a0 ; RV64IA-NEXT: sllw a4, a4, a0
; RV64IA-NEXT: slli a1, a1, 48 ; RV64IA-NEXT: slli a1, a1, 48
; RV64IA-NEXT: srai a1, a1, 48 ; RV64IA-NEXT: srai a1, a1, 48
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: li a5, 48 ; RV64IA-NEXT: li a5, 48
; RV64IA-NEXT: sub a3, a5, a3 ; RV64IA-NEXT: sub a3, a5, a3
; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a5, (a6) ; RV64IA-NEXT: lr.w a5, (a2)
; RV64IA-NEXT: and a4, a5, a7 ; RV64IA-NEXT: and a7, a5, a4
; RV64IA-NEXT: mv a2, a5 ; RV64IA-NEXT: mv a6, a5
; RV64IA-NEXT: sll a4, a4, a3 ; RV64IA-NEXT: sll a7, a7, a3
; RV64IA-NEXT: sra a4, a4, a3 ; RV64IA-NEXT: sra a7, a7, a3
; RV64IA-NEXT: bge a1, a4, .LBB22_3 ; RV64IA-NEXT: bge a1, a7, .LBB22_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB22_1 Depth=1
; RV64IA-NEXT: xor a2, a5, a1 ; RV64IA-NEXT: xor a6, a5, a1
; RV64IA-NEXT: and a2, a2, a7 ; RV64IA-NEXT: and a6, a6, a4
; RV64IA-NEXT: xor a2, a5, a2 ; RV64IA-NEXT: xor a6, a5, a6
; RV64IA-NEXT: .LBB22_3: # in Loop: Header=BB22_1 Depth=1 ; RV64IA-NEXT: .LBB22_3: # in Loop: Header=BB22_1 Depth=1
; RV64IA-NEXT: sc.w a2, a2, (a6) ; RV64IA-NEXT: sc.w a6, a6, (a2)
; RV64IA-NEXT: bnez a2, .LBB22_1 ; RV64IA-NEXT: bnez a6, .LBB22_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a5, a0 ; RV64IA-NEXT: srlw a0, a5, a0
; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw min i16* %a, i16 %b monotonic %1 = atomicrmw min i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define signext i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind { define signext i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i16_monotonic: ; RV32I-LABEL: atomicrmw_umax_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s2, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s3, s0, s2
; RV32I-NEXT: j .LBB23_2 ; RV32I-NEXT: j .LBB23_2
; RV32I-NEXT: .LBB23_1: # %atomicrmw.start ; RV32I-NEXT: .LBB23_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB23_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB23_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB23_4 ; RV32I-NEXT: bnez a0, .LBB23_4
; RV32I-NEXT: .LBB23_2: # %atomicrmw.start ; RV32I-NEXT: .LBB23_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bltu s1, a0, .LBB23_1 ; RV32I-NEXT: bltu s3, a0, .LBB23_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB23_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB23_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: j .LBB23_1 ; RV32I-NEXT: j .LBB23_1
; RV32I-NEXT: .LBB23_4: # %atomicrmw.end ; RV32I-NEXT: .LBB23_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umax_i16_monotonic: ; RV32IA-LABEL: atomicrmw_umax_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a6) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: and a2, a3, a4 ; RV32IA-NEXT: and a6, a3, a4
; RV32IA-NEXT: mv a5, a3 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a2, a1, .LBB23_3 ; RV32IA-NEXT: bgeu a6, a1, .LBB23_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB23_3: # in Loop: Header=BB23_1 Depth=1 ; RV32IA-NEXT: .LBB23_3: # in Loop: Header=BB23_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a6) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB23_1 ; RV32IA-NEXT: bnez a5, .LBB23_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: slli a0, a0, 16 ; RV32IA-NEXT: slli a0, a0, 16
; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umax_i16_monotonic: ; RV64I-LABEL: atomicrmw_umax_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s2, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB23_2 ; RV64I-NEXT: j .LBB23_2
; RV64I-NEXT: .LBB23_1: # %atomicrmw.start ; RV64I-NEXT: .LBB23_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB23_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB23_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB23_4 ; RV64I-NEXT: bnez a0, .LBB23_4
; RV64I-NEXT: .LBB23_2: # %atomicrmw.start ; RV64I-NEXT: .LBB23_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bltu s1, a0, .LBB23_1 ; RV64I-NEXT: bltu s3, a0, .LBB23_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB23_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB23_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: j .LBB23_1 ; RV64I-NEXT: j .LBB23_1
; RV64I-NEXT: .LBB23_4: # %atomicrmw.end ; RV64I-NEXT: .LBB23_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umax_i16_monotonic: ; RV64IA-LABEL: atomicrmw_umax_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB23_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a6) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: and a2, a3, a4 ; RV64IA-NEXT: and a6, a3, a4
; RV64IA-NEXT: mv a5, a3 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a2, a1, .LBB23_3 ; RV64IA-NEXT: bgeu a6, a1, .LBB23_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB23_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB23_3: # in Loop: Header=BB23_1 Depth=1 ; RV64IA-NEXT: .LBB23_3: # in Loop: Header=BB23_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a6) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB23_1 ; RV64IA-NEXT: bnez a5, .LBB23_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umax i16* %a, i16 %b monotonic %1 = atomicrmw umax i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
} }
define signext i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind { define signext i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i16_monotonic: ; RV32I-LABEL: atomicrmw_umin_i16_monotonic:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lhu a1, 0(a0) ; RV32I-NEXT: lhu a1, 0(a0)
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s2, a0, -1
; RV32I-NEXT: and s1, s2, s0 ; RV32I-NEXT: and s3, s0, s2
; RV32I-NEXT: j .LBB24_2 ; RV32I-NEXT: j .LBB24_2
; RV32I-NEXT: .LBB24_1: # %atomicrmw.start ; RV32I-NEXT: .LBB24_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB24_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB24_2 Depth=1
; RV32I-NEXT: sh a1, 10(sp) ; RV32I-NEXT: sh a1, 10(sp)
; RV32I-NEXT: addi a1, sp, 10 ; RV32I-NEXT: addi a1, sp, 10
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2@plt ; RV32I-NEXT: call __atomic_compare_exchange_2@plt
; RV32I-NEXT: lh a1, 10(sp) ; RV32I-NEXT: lh a1, 10(sp)
; RV32I-NEXT: bnez a0, .LBB24_4 ; RV32I-NEXT: bnez a0, .LBB24_4
; RV32I-NEXT: .LBB24_2: # %atomicrmw.start ; RV32I-NEXT: .LBB24_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s2
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: bgeu s1, a0, .LBB24_1 ; RV32I-NEXT: bgeu s3, a0, .LBB24_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start ; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB24_2 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB24_2 Depth=1
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: j .LBB24_1 ; RV32I-NEXT: j .LBB24_1
; RV32I-NEXT: .LBB24_4: # %atomicrmw.end ; RV32I-NEXT: .LBB24_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a1, 16 ; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IA-LABEL: atomicrmw_umin_i16_monotonic: ; RV32IA-LABEL: atomicrmw_umin_i16_monotonic:
; RV32IA: # %bb.0: ; RV32IA: # %bb.0:
; RV32IA-NEXT: andi a6, a0, -4 ; RV32IA-NEXT: andi a2, a0, -4
; RV32IA-NEXT: slli a0, a0, 3 ; RV32IA-NEXT: slli a0, a0, 3
; RV32IA-NEXT: lui a3, 16 ; RV32IA-NEXT: lui a3, 16
; RV32IA-NEXT: addi a3, a3, -1 ; RV32IA-NEXT: addi a3, a3, -1
; RV32IA-NEXT: sll a4, a3, a0 ; RV32IA-NEXT: sll a4, a3, a0
; RV32IA-NEXT: and a1, a1, a3 ; RV32IA-NEXT: and a1, a1, a3
; RV32IA-NEXT: sll a1, a1, a0 ; RV32IA-NEXT: sll a1, a1, a0
; RV32IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 ; RV32IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
; RV32IA-NEXT: lr.w a3, (a6) ; RV32IA-NEXT: lr.w a3, (a2)
; RV32IA-NEXT: and a2, a3, a4 ; RV32IA-NEXT: and a6, a3, a4
; RV32IA-NEXT: mv a5, a3 ; RV32IA-NEXT: mv a5, a3
; RV32IA-NEXT: bgeu a1, a2, .LBB24_3 ; RV32IA-NEXT: bgeu a1, a6, .LBB24_3
; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1 ; RV32IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1
; RV32IA-NEXT: xor a5, a3, a1 ; RV32IA-NEXT: xor a5, a3, a1
; RV32IA-NEXT: and a5, a5, a4 ; RV32IA-NEXT: and a5, a5, a4
; RV32IA-NEXT: xor a5, a3, a5 ; RV32IA-NEXT: xor a5, a3, a5
; RV32IA-NEXT: .LBB24_3: # in Loop: Header=BB24_1 Depth=1 ; RV32IA-NEXT: .LBB24_3: # in Loop: Header=BB24_1 Depth=1
; RV32IA-NEXT: sc.w a5, a5, (a6) ; RV32IA-NEXT: sc.w a5, a5, (a2)
; RV32IA-NEXT: bnez a5, .LBB24_1 ; RV32IA-NEXT: bnez a5, .LBB24_1
; RV32IA-NEXT: # %bb.4: ; RV32IA-NEXT: # %bb.4:
; RV32IA-NEXT: srl a0, a3, a0 ; RV32IA-NEXT: srl a0, a3, a0
; RV32IA-NEXT: slli a0, a0, 16 ; RV32IA-NEXT: slli a0, a0, 16
; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: srai a0, a0, 16
; RV32IA-NEXT: ret ; RV32IA-NEXT: ret
; ;
; RV64I-LABEL: atomicrmw_umin_i16_monotonic: ; RV64I-LABEL: atomicrmw_umin_i16_monotonic:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lhu a1, 0(a0) ; RV64I-NEXT: lhu a1, 0(a0)
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s2, a0, -1
; RV64I-NEXT: and s1, s2, s0 ; RV64I-NEXT: and s3, s0, s2
; RV64I-NEXT: j .LBB24_2 ; RV64I-NEXT: j .LBB24_2
; RV64I-NEXT: .LBB24_1: # %atomicrmw.start ; RV64I-NEXT: .LBB24_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB24_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB24_2 Depth=1
; RV64I-NEXT: sh a1, 6(sp) ; RV64I-NEXT: sh a1, 6(sp)
; RV64I-NEXT: addi a1, sp, 6 ; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2@plt ; RV64I-NEXT: call __atomic_compare_exchange_2@plt
; RV64I-NEXT: lh a1, 6(sp) ; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB24_4 ; RV64I-NEXT: bnez a0, .LBB24_4
; RV64I-NEXT: .LBB24_2: # %atomicrmw.start ; RV64I-NEXT: .LBB24_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s2
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: bgeu s1, a0, .LBB24_1 ; RV64I-NEXT: bgeu s3, a0, .LBB24_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB24_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB24_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: j .LBB24_1 ; RV64I-NEXT: j .LBB24_1
; RV64I-NEXT: .LBB24_4: # %atomicrmw.end ; RV64I-NEXT: .LBB24_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a1, 48 ; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IA-LABEL: atomicrmw_umin_i16_monotonic: ; RV64IA-LABEL: atomicrmw_umin_i16_monotonic:
; RV64IA: # %bb.0: ; RV64IA: # %bb.0:
; RV64IA-NEXT: andi a6, a0, -4 ; RV64IA-NEXT: andi a2, a0, -4
; RV64IA-NEXT: slliw a0, a0, 3 ; RV64IA-NEXT: slliw a0, a0, 3
; RV64IA-NEXT: lui a3, 16 ; RV64IA-NEXT: lui a3, 16
; RV64IA-NEXT: addiw a3, a3, -1 ; RV64IA-NEXT: addiw a3, a3, -1
; RV64IA-NEXT: sllw a4, a3, a0 ; RV64IA-NEXT: sllw a4, a3, a0
; RV64IA-NEXT: and a1, a1, a3 ; RV64IA-NEXT: and a1, a1, a3
; RV64IA-NEXT: sllw a1, a1, a0 ; RV64IA-NEXT: sllw a1, a1, a0
; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 ; RV64IA-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1
; RV64IA-NEXT: lr.w a3, (a6) ; RV64IA-NEXT: lr.w a3, (a2)
; RV64IA-NEXT: and a2, a3, a4 ; RV64IA-NEXT: and a6, a3, a4
; RV64IA-NEXT: mv a5, a3 ; RV64IA-NEXT: mv a5, a3
; RV64IA-NEXT: bgeu a1, a2, .LBB24_3 ; RV64IA-NEXT: bgeu a1, a6, .LBB24_3
; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1 ; RV64IA-NEXT: # %bb.2: # in Loop: Header=BB24_1 Depth=1
; RV64IA-NEXT: xor a5, a3, a1 ; RV64IA-NEXT: xor a5, a3, a1
; RV64IA-NEXT: and a5, a5, a4 ; RV64IA-NEXT: and a5, a5, a4
; RV64IA-NEXT: xor a5, a3, a5 ; RV64IA-NEXT: xor a5, a3, a5
; RV64IA-NEXT: .LBB24_3: # in Loop: Header=BB24_1 Depth=1 ; RV64IA-NEXT: .LBB24_3: # in Loop: Header=BB24_1 Depth=1
; RV64IA-NEXT: sc.w a5, a5, (a6) ; RV64IA-NEXT: sc.w a5, a5, (a2)
; RV64IA-NEXT: bnez a5, .LBB24_1 ; RV64IA-NEXT: bnez a5, .LBB24_1
; RV64IA-NEXT: # %bb.4: ; RV64IA-NEXT: # %bb.4:
; RV64IA-NEXT: srlw a0, a3, a0 ; RV64IA-NEXT: srlw a0, a3, a0
; RV64IA-NEXT: slli a0, a0, 48 ; RV64IA-NEXT: slli a0, a0, 48
; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: srai a0, a0, 48
; RV64IA-NEXT: ret ; RV64IA-NEXT: ret
%1 = atomicrmw umin i16* %a, i16 %b monotonic %1 = atomicrmw umin i16* %a, i16 %b monotonic
ret i16 %1 ret i16 %1
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB32_2 ; RV64I-NEXT: j .LBB32_2
; RV64I-NEXT: .LBB32_1: # %atomicrmw.start ; RV64I-NEXT: .LBB32_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB32_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB32_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB32_4 ; RV64I-NEXT: bnez a0, .LBB32_4
; RV64I-NEXT: .LBB32_2: # %atomicrmw.start ; RV64I-NEXT: .LBB32_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: blt s1, a3, .LBB32_1 ; RV64I-NEXT: blt s2, a3, .LBB32_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB32_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB32_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB32_1 ; RV64I-NEXT: j .LBB32_1
; RV64I-NEXT: .LBB32_4: # %atomicrmw.end ; RV64I-NEXT: .LBB32_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB33_2 ; RV64I-NEXT: j .LBB33_2
; RV64I-NEXT: .LBB33_1: # %atomicrmw.start ; RV64I-NEXT: .LBB33_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB33_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB33_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB33_4 ; RV64I-NEXT: bnez a0, .LBB33_4
; RV64I-NEXT: .LBB33_2: # %atomicrmw.start ; RV64I-NEXT: .LBB33_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bge s1, a3, .LBB33_1 ; RV64I-NEXT: bge s2, a3, .LBB33_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB33_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB33_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB33_1 ; RV64I-NEXT: j .LBB33_1
; RV64I-NEXT: .LBB33_4: # %atomicrmw.end ; RV64I-NEXT: .LBB33_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB34_2 ; RV64I-NEXT: j .LBB34_2
; RV64I-NEXT: .LBB34_1: # %atomicrmw.start ; RV64I-NEXT: .LBB34_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB34_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB34_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB34_4 ; RV64I-NEXT: bnez a0, .LBB34_4
; RV64I-NEXT: .LBB34_2: # %atomicrmw.start ; RV64I-NEXT: .LBB34_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bltu s1, a3, .LBB34_1 ; RV64I-NEXT: bltu s2, a3, .LBB34_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB34_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB34_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB34_1 ; RV64I-NEXT: j .LBB34_1
; RV64I-NEXT: .LBB34_4: # %atomicrmw.end ; RV64I-NEXT: .LBB34_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lw a3, 0(a0) ; RV64I-NEXT: lw a3, 0(a0)
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: sext.w s1, a1 ; RV64I-NEXT: sext.w s2, a1
; RV64I-NEXT: j .LBB35_2 ; RV64I-NEXT: j .LBB35_2
; RV64I-NEXT: .LBB35_1: # %atomicrmw.start ; RV64I-NEXT: .LBB35_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV64I-NEXT: sw a3, 12(sp) ; RV64I-NEXT: sw a3, 12(sp)
; RV64I-NEXT: addi a1, sp, 12 ; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0 ; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0 ; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4@plt ; RV64I-NEXT: call __atomic_compare_exchange_4@plt
; RV64I-NEXT: lw a3, 12(sp) ; RV64I-NEXT: lw a3, 12(sp)
; RV64I-NEXT: bnez a0, .LBB35_4 ; RV64I-NEXT: bnez a0, .LBB35_4
; RV64I-NEXT: .LBB35_2: # %atomicrmw.start ; RV64I-NEXT: .LBB35_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bgeu s1, a3, .LBB35_1 ; RV64I-NEXT: bgeu s2, a3, .LBB35_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start ; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1 ; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV64I-NEXT: mv a2, s2 ; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB35_1 ; RV64I-NEXT: j .LBB35_1
; RV64I-NEXT: .LBB35_4: # %atomicrmw.end ; RV64I-NEXT: .LBB35_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll

Show First 20 Lines • Show All 431 Lines • ▼ Show 20 Lines
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: not a1, s4 ; RV32I-NEXT: not a1, s2
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s5, a2, 1365 ; RV32I-NEXT: addi s4, a2, 1365
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819 ; RV32I-NEXT: addi s5, a1, 819
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s6, a1, -241 ; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257 ; RV32I-NEXT: addi s3, a1, 257
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a0, s3, -1 ; RV32I-NEXT: addi a0, s1, -1
; RV32I-NEXT: not a1, s3 ; RV32I-NEXT: not a1, s1
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: bnez s4, .LBB7_2 ; RV32I-NEXT: bnez s2, .LBB7_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32 ; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB7_3 ; RV32I-NEXT: j .LBB7_3
; RV32I-NEXT: .LBB7_2: ; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: srli a0, s2, 24 ; RV32I-NEXT: srli a0, s0, 24
; RV32I-NEXT: .LBB7_3: ; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
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; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: not a1, s4 ; RV32I-NEXT: not a1, s2
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s5, a2, 1365 ; RV32I-NEXT: addi s4, a2, 1365
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819 ; RV32I-NEXT: addi s5, a1, 819
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s6, a1, -241 ; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257 ; RV32I-NEXT: addi s3, a1, 257
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a0, s3, -1 ; RV32I-NEXT: addi a0, s1, -1
; RV32I-NEXT: not a1, s3 ; RV32I-NEXT: not a1, s1
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: bnez s4, .LBB11_2 ; RV32I-NEXT: bnez s2, .LBB11_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32 ; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB11_3 ; RV32I-NEXT: j .LBB11_3
; RV32I-NEXT: .LBB11_2: ; RV32I-NEXT: .LBB11_2:
; RV32I-NEXT: srli a0, s2, 24 ; RV32I-NEXT: srli a0, s0, 24
; RV32I-NEXT: .LBB11_3: ; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: srli a0, a1, 1 ; RV32I-NEXT: srli a0, a1, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s3, a2, 1365 ; RV32I-NEXT: addi s2, a2, 1365
; RV32I-NEXT: and a0, a0, s3 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: sub a0, a1, a0 ; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819 ; RV32I-NEXT: addi s3, a1, 819
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s3
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s4, a1, -241 ; RV32I-NEXT: addi s4, a1, -241
; RV32I-NEXT: and a0, a0, s4 ; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257 ; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli s5, a0, 24 ; RV32I-NEXT: srli s5, a0, 24
; RV32I-NEXT: srli a0, s2, 1 ; RV32I-NEXT: srli a0, s0, 1
; RV32I-NEXT: and a0, a0, s3 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: sub a0, s2, a0 ; RV32I-NEXT: sub a0, s0, a0
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s3
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s4 ; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: add a0, a0, s5 ; RV32I-NEXT: add a0, a0, s5
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llvm/test/CodeGen/RISCV/callee-saved-gprs.ll

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, %lo(var+12)(a7) ; RV32I-NEXT: lw a0, %lo(var+12)(a7)
; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a5, a7, %lo(var) ; RV32I-NEXT: addi a5, a7, %lo(var)
; RV32I-NEXT: lw a0, 16(a5) ; RV32I-NEXT: lw a0, 16(a5)
; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 20(a5) ; RV32I-NEXT: lw a0, 20(a5)
; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw t4, 24(a5) ; RV32I-NEXT: lw t0, 24(a5)
; RV32I-NEXT: lw t5, 28(a5) ; RV32I-NEXT: lw t1, 28(a5)
; RV32I-NEXT: lw t6, 32(a5) ; RV32I-NEXT: lw t2, 32(a5)
; RV32I-NEXT: lw s2, 36(a5) ; RV32I-NEXT: lw t3, 36(a5)
; RV32I-NEXT: lw s3, 40(a5) ; RV32I-NEXT: lw t4, 40(a5)
; RV32I-NEXT: lw s4, 44(a5) ; RV32I-NEXT: lw t5, 44(a5)
; RV32I-NEXT: lw s5, 48(a5) ; RV32I-NEXT: lw t6, 48(a5)
; RV32I-NEXT: lw s6, 52(a5) ; RV32I-NEXT: lw s0, 52(a5)
; RV32I-NEXT: lw s7, 56(a5) ; RV32I-NEXT: lw s1, 56(a5)
; RV32I-NEXT: lw s8, 60(a5) ; RV32I-NEXT: lw s2, 60(a5)
; RV32I-NEXT: lw s9, 64(a5) ; RV32I-NEXT: lw s3, 64(a5)
; RV32I-NEXT: lw s10, 68(a5) ; RV32I-NEXT: lw s4, 68(a5)
; RV32I-NEXT: lw s11, 72(a5) ; RV32I-NEXT: lw s5, 72(a5)
; RV32I-NEXT: lw ra, 76(a5) ; RV32I-NEXT: lw s6, 76(a5)
; RV32I-NEXT: lw s1, 80(a5) ; RV32I-NEXT: lw s7, 80(a5)
; RV32I-NEXT: lw t3, 84(a5) ; RV32I-NEXT: lw s8, 84(a5)
; RV32I-NEXT: lw t2, 88(a5) ; RV32I-NEXT: lw s9, 88(a5)
; RV32I-NEXT: lw t1, 92(a5) ; RV32I-NEXT: lw s10, 92(a5)
; RV32I-NEXT: lw t0, 96(a5) ; RV32I-NEXT: lw s11, 96(a5)
; RV32I-NEXT: lw s0, 100(a5) ; RV32I-NEXT: lw ra, 100(a5)
; RV32I-NEXT: lw a6, 104(a5) ; RV32I-NEXT: lw a6, 104(a5)
; RV32I-NEXT: lw a4, 108(a5) ; RV32I-NEXT: lw a4, 108(a5)
; RV32I-NEXT: lw a0, 124(a5) ; RV32I-NEXT: lw a0, 124(a5)
; RV32I-NEXT: lw a1, 120(a5) ; RV32I-NEXT: lw a1, 120(a5)
; RV32I-NEXT: lw a2, 116(a5) ; RV32I-NEXT: lw a2, 116(a5)
; RV32I-NEXT: lw a3, 112(a5) ; RV32I-NEXT: lw a3, 112(a5)
; RV32I-NEXT: sw a0, 124(a5) ; RV32I-NEXT: sw a0, 124(a5)
; RV32I-NEXT: sw a1, 120(a5) ; RV32I-NEXT: sw a1, 120(a5)
; RV32I-NEXT: sw a2, 116(a5) ; RV32I-NEXT: sw a2, 116(a5)
; RV32I-NEXT: sw a3, 112(a5) ; RV32I-NEXT: sw a3, 112(a5)
; RV32I-NEXT: sw a4, 108(a5) ; RV32I-NEXT: sw a4, 108(a5)
; RV32I-NEXT: sw a6, 104(a5) ; RV32I-NEXT: sw a6, 104(a5)
; RV32I-NEXT: sw s0, 100(a5) ; RV32I-NEXT: sw ra, 100(a5)
; RV32I-NEXT: sw t0, 96(a5) ; RV32I-NEXT: sw s11, 96(a5)
; RV32I-NEXT: sw t1, 92(a5) ; RV32I-NEXT: sw s10, 92(a5)
; RV32I-NEXT: sw t2, 88(a5) ; RV32I-NEXT: sw s9, 88(a5)
; RV32I-NEXT: sw t3, 84(a5) ; RV32I-NEXT: sw s8, 84(a5)
; RV32I-NEXT: sw s1, 80(a5) ; RV32I-NEXT: sw s7, 80(a5)
; RV32I-NEXT: sw ra, 76(a5) ; RV32I-NEXT: sw s6, 76(a5)
; RV32I-NEXT: sw s11, 72(a5) ; RV32I-NEXT: sw s5, 72(a5)
; RV32I-NEXT: sw s10, 68(a5) ; RV32I-NEXT: sw s4, 68(a5)
; RV32I-NEXT: sw s9, 64(a5) ; RV32I-NEXT: sw s3, 64(a5)
; RV32I-NEXT: sw s8, 60(a5) ; RV32I-NEXT: sw s2, 60(a5)
; RV32I-NEXT: sw s7, 56(a5) ; RV32I-NEXT: sw s1, 56(a5)
; RV32I-NEXT: sw s6, 52(a5) ; RV32I-NEXT: sw s0, 52(a5)
; RV32I-NEXT: sw s5, 48(a5) ; RV32I-NEXT: sw t6, 48(a5)
; RV32I-NEXT: sw s4, 44(a5) ; RV32I-NEXT: sw t5, 44(a5)
; RV32I-NEXT: sw s3, 40(a5) ; RV32I-NEXT: sw t4, 40(a5)
; RV32I-NEXT: sw s2, 36(a5) ; RV32I-NEXT: sw t3, 36(a5)
; RV32I-NEXT: sw t6, 32(a5) ; RV32I-NEXT: sw t2, 32(a5)
; RV32I-NEXT: sw t5, 28(a5) ; RV32I-NEXT: sw t1, 28(a5)
; RV32I-NEXT: sw t4, 24(a5) ; RV32I-NEXT: sw t0, 24(a5)
; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 20(a5) ; RV32I-NEXT: sw a0, 20(a5)
; RV32I-NEXT: lw a0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 16(a5) ; RV32I-NEXT: sw a0, 16(a5)
; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, %lo(var+12)(a7) ; RV32I-NEXT: sw a0, %lo(var+12)(a7)
; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, %lo(var+8)(a7) ; RV32I-NEXT: sw a0, %lo(var+8)(a7)
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; RV32I-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: addi a5, a7, %lo(var) ; RV32I-WITH-FP-NEXT: addi a5, a7, %lo(var)
; RV32I-WITH-FP-NEXT: lw a0, 16(a5) ; RV32I-WITH-FP-NEXT: lw a0, 16(a5)
; RV32I-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 20(a5) ; RV32I-WITH-FP-NEXT: lw a0, 20(a5)
; RV32I-WITH-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 24(a5) ; RV32I-WITH-FP-NEXT: lw a0, 24(a5)
; RV32I-WITH-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw t5, 28(a5) ; RV32I-WITH-FP-NEXT: lw t1, 28(a5)
; RV32I-WITH-FP-NEXT: lw t6, 32(a5) ; RV32I-WITH-FP-NEXT: lw t2, 32(a5)
; RV32I-WITH-FP-NEXT: lw s2, 36(a5) ; RV32I-WITH-FP-NEXT: lw t3, 36(a5)
; RV32I-WITH-FP-NEXT: lw s3, 40(a5) ; RV32I-WITH-FP-NEXT: lw t4, 40(a5)
; RV32I-WITH-FP-NEXT: lw s4, 44(a5) ; RV32I-WITH-FP-NEXT: lw t5, 44(a5)
; RV32I-WITH-FP-NEXT: lw s5, 48(a5) ; RV32I-WITH-FP-NEXT: lw t6, 48(a5)
; RV32I-WITH-FP-NEXT: lw s6, 52(a5) ; RV32I-WITH-FP-NEXT: lw s1, 52(a5)
; RV32I-WITH-FP-NEXT: lw s7, 56(a5) ; RV32I-WITH-FP-NEXT: lw s2, 56(a5)
; RV32I-WITH-FP-NEXT: lw s8, 60(a5) ; RV32I-WITH-FP-NEXT: lw s3, 60(a5)
; RV32I-WITH-FP-NEXT: lw s9, 64(a5) ; RV32I-WITH-FP-NEXT: lw s4, 64(a5)
; RV32I-WITH-FP-NEXT: lw s10, 68(a5) ; RV32I-WITH-FP-NEXT: lw s5, 68(a5)
; RV32I-WITH-FP-NEXT: lw s11, 72(a5) ; RV32I-WITH-FP-NEXT: lw s6, 72(a5)
; RV32I-WITH-FP-NEXT: lw ra, 76(a5) ; RV32I-WITH-FP-NEXT: lw s7, 76(a5)
; RV32I-WITH-FP-NEXT: lw t4, 80(a5) ; RV32I-WITH-FP-NEXT: lw s8, 80(a5)
; RV32I-WITH-FP-NEXT: lw t3, 84(a5) ; RV32I-WITH-FP-NEXT: lw s9, 84(a5)
; RV32I-WITH-FP-NEXT: lw t2, 88(a5) ; RV32I-WITH-FP-NEXT: lw s10, 88(a5)
; RV32I-WITH-FP-NEXT: lw s1, 92(a5) ; RV32I-WITH-FP-NEXT: lw s11, 92(a5)
; RV32I-WITH-FP-NEXT: lw t1, 96(a5) ; RV32I-WITH-FP-NEXT: lw ra, 96(a5)
; RV32I-WITH-FP-NEXT: lw t0, 100(a5) ; RV32I-WITH-FP-NEXT: lw t0, 100(a5)
; RV32I-WITH-FP-NEXT: lw a6, 104(a5) ; RV32I-WITH-FP-NEXT: lw a6, 104(a5)
; RV32I-WITH-FP-NEXT: lw a4, 108(a5) ; RV32I-WITH-FP-NEXT: lw a4, 108(a5)
; RV32I-WITH-FP-NEXT: lw a0, 124(a5) ; RV32I-WITH-FP-NEXT: lw a0, 124(a5)
; RV32I-WITH-FP-NEXT: lw a1, 120(a5) ; RV32I-WITH-FP-NEXT: lw a1, 120(a5)
; RV32I-WITH-FP-NEXT: lw a2, 116(a5) ; RV32I-WITH-FP-NEXT: lw a2, 116(a5)
; RV32I-WITH-FP-NEXT: lw a3, 112(a5) ; RV32I-WITH-FP-NEXT: lw a3, 112(a5)
; RV32I-WITH-FP-NEXT: sw a0, 124(a5) ; RV32I-WITH-FP-NEXT: sw a0, 124(a5)
; RV32I-WITH-FP-NEXT: sw a1, 120(a5) ; RV32I-WITH-FP-NEXT: sw a1, 120(a5)
; RV32I-WITH-FP-NEXT: sw a2, 116(a5) ; RV32I-WITH-FP-NEXT: sw a2, 116(a5)
; RV32I-WITH-FP-NEXT: sw a3, 112(a5) ; RV32I-WITH-FP-NEXT: sw a3, 112(a5)
; RV32I-WITH-FP-NEXT: sw a4, 108(a5) ; RV32I-WITH-FP-NEXT: sw a4, 108(a5)
; RV32I-WITH-FP-NEXT: sw a6, 104(a5) ; RV32I-WITH-FP-NEXT: sw a6, 104(a5)
; RV32I-WITH-FP-NEXT: sw t0, 100(a5) ; RV32I-WITH-FP-NEXT: sw t0, 100(a5)
; RV32I-WITH-FP-NEXT: sw t1, 96(a5) ; RV32I-WITH-FP-NEXT: sw ra, 96(a5)
; RV32I-WITH-FP-NEXT: sw s1, 92(a5) ; RV32I-WITH-FP-NEXT: sw s11, 92(a5)
; RV32I-WITH-FP-NEXT: sw t2, 88(a5) ; RV32I-WITH-FP-NEXT: sw s10, 88(a5)
; RV32I-WITH-FP-NEXT: sw t3, 84(a5) ; RV32I-WITH-FP-NEXT: sw s9, 84(a5)
; RV32I-WITH-FP-NEXT: sw t4, 80(a5) ; RV32I-WITH-FP-NEXT: sw s8, 80(a5)
; RV32I-WITH-FP-NEXT: sw ra, 76(a5) ; RV32I-WITH-FP-NEXT: sw s7, 76(a5)
; RV32I-WITH-FP-NEXT: sw s11, 72(a5) ; RV32I-WITH-FP-NEXT: sw s6, 72(a5)
; RV32I-WITH-FP-NEXT: sw s10, 68(a5) ; RV32I-WITH-FP-NEXT: sw s5, 68(a5)
; RV32I-WITH-FP-NEXT: sw s9, 64(a5) ; RV32I-WITH-FP-NEXT: sw s4, 64(a5)
; RV32I-WITH-FP-NEXT: sw s8, 60(a5) ; RV32I-WITH-FP-NEXT: sw s3, 60(a5)
; RV32I-WITH-FP-NEXT: sw s7, 56(a5) ; RV32I-WITH-FP-NEXT: sw s2, 56(a5)
; RV32I-WITH-FP-NEXT: sw s6, 52(a5) ; RV32I-WITH-FP-NEXT: sw s1, 52(a5)
; RV32I-WITH-FP-NEXT: sw s5, 48(a5) ; RV32I-WITH-FP-NEXT: sw t6, 48(a5)
; RV32I-WITH-FP-NEXT: sw s4, 44(a5) ; RV32I-WITH-FP-NEXT: sw t5, 44(a5)
; RV32I-WITH-FP-NEXT: sw s3, 40(a5) ; RV32I-WITH-FP-NEXT: sw t4, 40(a5)
; RV32I-WITH-FP-NEXT: sw s2, 36(a5) ; RV32I-WITH-FP-NEXT: sw t3, 36(a5)
; RV32I-WITH-FP-NEXT: sw t6, 32(a5) ; RV32I-WITH-FP-NEXT: sw t2, 32(a5)
; RV32I-WITH-FP-NEXT: sw t5, 28(a5) ; RV32I-WITH-FP-NEXT: sw t1, 28(a5)
; RV32I-WITH-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 24(a5) ; RV32I-WITH-FP-NEXT: sw a0, 24(a5)
; RV32I-WITH-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 20(a5) ; RV32I-WITH-FP-NEXT: sw a0, 20(a5)
; RV32I-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 16(a5) ; RV32I-WITH-FP-NEXT: sw a0, 16(a5)
; RV32I-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, %lo(var+12)(a7) ; RV32I-WITH-FP-NEXT: sw a0, %lo(var+12)(a7)
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, %lo(var+12)(a7) ; RV64I-NEXT: lw a0, %lo(var+12)(a7)
; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a5, a7, %lo(var) ; RV64I-NEXT: addi a5, a7, %lo(var)
; RV64I-NEXT: lw a0, 16(a5) ; RV64I-NEXT: lw a0, 16(a5)
; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 20(a5) ; RV64I-NEXT: lw a0, 20(a5)
; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw t4, 24(a5) ; RV64I-NEXT: lw t0, 24(a5)
; RV64I-NEXT: lw t5, 28(a5) ; RV64I-NEXT: lw t1, 28(a5)
; RV64I-NEXT: lw t6, 32(a5) ; RV64I-NEXT: lw t2, 32(a5)
; RV64I-NEXT: lw s2, 36(a5) ; RV64I-NEXT: lw t3, 36(a5)
; RV64I-NEXT: lw s3, 40(a5) ; RV64I-NEXT: lw t4, 40(a5)
; RV64I-NEXT: lw s4, 44(a5) ; RV64I-NEXT: lw t5, 44(a5)
; RV64I-NEXT: lw s5, 48(a5) ; RV64I-NEXT: lw t6, 48(a5)
; RV64I-NEXT: lw s6, 52(a5) ; RV64I-NEXT: lw s0, 52(a5)
; RV64I-NEXT: lw s7, 56(a5) ; RV64I-NEXT: lw s1, 56(a5)
; RV64I-NEXT: lw s8, 60(a5) ; RV64I-NEXT: lw s2, 60(a5)
; RV64I-NEXT: lw s9, 64(a5) ; RV64I-NEXT: lw s3, 64(a5)
; RV64I-NEXT: lw s10, 68(a5) ; RV64I-NEXT: lw s4, 68(a5)
; RV64I-NEXT: lw s11, 72(a5) ; RV64I-NEXT: lw s5, 72(a5)
; RV64I-NEXT: lw ra, 76(a5) ; RV64I-NEXT: lw s6, 76(a5)
; RV64I-NEXT: lw s1, 80(a5) ; RV64I-NEXT: lw s7, 80(a5)
; RV64I-NEXT: lw t3, 84(a5) ; RV64I-NEXT: lw s8, 84(a5)
; RV64I-NEXT: lw t2, 88(a5) ; RV64I-NEXT: lw s9, 88(a5)
; RV64I-NEXT: lw t1, 92(a5) ; RV64I-NEXT: lw s10, 92(a5)
; RV64I-NEXT: lw t0, 96(a5) ; RV64I-NEXT: lw s11, 96(a5)
; RV64I-NEXT: lw s0, 100(a5) ; RV64I-NEXT: lw ra, 100(a5)
; RV64I-NEXT: lw a6, 104(a5) ; RV64I-NEXT: lw a6, 104(a5)
; RV64I-NEXT: lw a4, 108(a5) ; RV64I-NEXT: lw a4, 108(a5)
; RV64I-NEXT: lw a0, 124(a5) ; RV64I-NEXT: lw a0, 124(a5)
; RV64I-NEXT: lw a1, 120(a5) ; RV64I-NEXT: lw a1, 120(a5)
; RV64I-NEXT: lw a2, 116(a5) ; RV64I-NEXT: lw a2, 116(a5)
; RV64I-NEXT: lw a3, 112(a5) ; RV64I-NEXT: lw a3, 112(a5)
; RV64I-NEXT: sw a0, 124(a5) ; RV64I-NEXT: sw a0, 124(a5)
; RV64I-NEXT: sw a1, 120(a5) ; RV64I-NEXT: sw a1, 120(a5)
; RV64I-NEXT: sw a2, 116(a5) ; RV64I-NEXT: sw a2, 116(a5)
; RV64I-NEXT: sw a3, 112(a5) ; RV64I-NEXT: sw a3, 112(a5)
; RV64I-NEXT: sw a4, 108(a5) ; RV64I-NEXT: sw a4, 108(a5)
; RV64I-NEXT: sw a6, 104(a5) ; RV64I-NEXT: sw a6, 104(a5)
; RV64I-NEXT: sw s0, 100(a5) ; RV64I-NEXT: sw ra, 100(a5)
; RV64I-NEXT: sw t0, 96(a5) ; RV64I-NEXT: sw s11, 96(a5)
; RV64I-NEXT: sw t1, 92(a5) ; RV64I-NEXT: sw s10, 92(a5)
; RV64I-NEXT: sw t2, 88(a5) ; RV64I-NEXT: sw s9, 88(a5)
; RV64I-NEXT: sw t3, 84(a5) ; RV64I-NEXT: sw s8, 84(a5)
; RV64I-NEXT: sw s1, 80(a5) ; RV64I-NEXT: sw s7, 80(a5)
; RV64I-NEXT: sw ra, 76(a5) ; RV64I-NEXT: sw s6, 76(a5)
; RV64I-NEXT: sw s11, 72(a5) ; RV64I-NEXT: sw s5, 72(a5)
; RV64I-NEXT: sw s10, 68(a5) ; RV64I-NEXT: sw s4, 68(a5)
; RV64I-NEXT: sw s9, 64(a5) ; RV64I-NEXT: sw s3, 64(a5)
; RV64I-NEXT: sw s8, 60(a5) ; RV64I-NEXT: sw s2, 60(a5)
; RV64I-NEXT: sw s7, 56(a5) ; RV64I-NEXT: sw s1, 56(a5)
; RV64I-NEXT: sw s6, 52(a5) ; RV64I-NEXT: sw s0, 52(a5)
; RV64I-NEXT: sw s5, 48(a5) ; RV64I-NEXT: sw t6, 48(a5)
; RV64I-NEXT: sw s4, 44(a5) ; RV64I-NEXT: sw t5, 44(a5)
; RV64I-NEXT: sw s3, 40(a5) ; RV64I-NEXT: sw t4, 40(a5)
; RV64I-NEXT: sw s2, 36(a5) ; RV64I-NEXT: sw t3, 36(a5)
; RV64I-NEXT: sw t6, 32(a5) ; RV64I-NEXT: sw t2, 32(a5)
; RV64I-NEXT: sw t5, 28(a5) ; RV64I-NEXT: sw t1, 28(a5)
; RV64I-NEXT: sw t4, 24(a5) ; RV64I-NEXT: sw t0, 24(a5)
; RV64I-NEXT: ld a0, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 20(a5) ; RV64I-NEXT: sw a0, 20(a5)
; RV64I-NEXT: ld a0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 16(a5) ; RV64I-NEXT: sw a0, 16(a5)
; RV64I-NEXT: ld a0, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, %lo(var+12)(a7) ; RV64I-NEXT: sw a0, %lo(var+12)(a7)
; RV64I-NEXT: ld a0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, %lo(var+8)(a7) ; RV64I-NEXT: sw a0, %lo(var+8)(a7)
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; RV64I-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: addi a5, a7, %lo(var) ; RV64I-WITH-FP-NEXT: addi a5, a7, %lo(var)
; RV64I-WITH-FP-NEXT: lw a0, 16(a5) ; RV64I-WITH-FP-NEXT: lw a0, 16(a5)
; RV64I-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 20(a5) ; RV64I-WITH-FP-NEXT: lw a0, 20(a5)
; RV64I-WITH-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 24(a5) ; RV64I-WITH-FP-NEXT: lw a0, 24(a5)
; RV64I-WITH-FP-NEXT: sd a0, -160(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -160(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw t5, 28(a5) ; RV64I-WITH-FP-NEXT: lw t1, 28(a5)
; RV64I-WITH-FP-NEXT: lw t6, 32(a5) ; RV64I-WITH-FP-NEXT: lw t2, 32(a5)
; RV64I-WITH-FP-NEXT: lw s2, 36(a5) ; RV64I-WITH-FP-NEXT: lw t3, 36(a5)
; RV64I-WITH-FP-NEXT: lw s3, 40(a5) ; RV64I-WITH-FP-NEXT: lw t4, 40(a5)
; RV64I-WITH-FP-NEXT: lw s4, 44(a5) ; RV64I-WITH-FP-NEXT: lw t5, 44(a5)
; RV64I-WITH-FP-NEXT: lw s5, 48(a5) ; RV64I-WITH-FP-NEXT: lw t6, 48(a5)
; RV64I-WITH-FP-NEXT: lw s6, 52(a5) ; RV64I-WITH-FP-NEXT: lw s1, 52(a5)
; RV64I-WITH-FP-NEXT: lw s7, 56(a5) ; RV64I-WITH-FP-NEXT: lw s2, 56(a5)
; RV64I-WITH-FP-NEXT: lw s8, 60(a5) ; RV64I-WITH-FP-NEXT: lw s3, 60(a5)
; RV64I-WITH-FP-NEXT: lw s9, 64(a5) ; RV64I-WITH-FP-NEXT: lw s4, 64(a5)
; RV64I-WITH-FP-NEXT: lw s10, 68(a5) ; RV64I-WITH-FP-NEXT: lw s5, 68(a5)
; RV64I-WITH-FP-NEXT: lw s11, 72(a5) ; RV64I-WITH-FP-NEXT: lw s6, 72(a5)
; RV64I-WITH-FP-NEXT: lw ra, 76(a5) ; RV64I-WITH-FP-NEXT: lw s7, 76(a5)
; RV64I-WITH-FP-NEXT: lw t4, 80(a5) ; RV64I-WITH-FP-NEXT: lw s8, 80(a5)
; RV64I-WITH-FP-NEXT: lw t3, 84(a5) ; RV64I-WITH-FP-NEXT: lw s9, 84(a5)
; RV64I-WITH-FP-NEXT: lw t2, 88(a5) ; RV64I-WITH-FP-NEXT: lw s10, 88(a5)
; RV64I-WITH-FP-NEXT: lw s1, 92(a5) ; RV64I-WITH-FP-NEXT: lw s11, 92(a5)
; RV64I-WITH-FP-NEXT: lw t1, 96(a5) ; RV64I-WITH-FP-NEXT: lw ra, 96(a5)
; RV64I-WITH-FP-NEXT: lw t0, 100(a5) ; RV64I-WITH-FP-NEXT: lw t0, 100(a5)
; RV64I-WITH-FP-NEXT: lw a6, 104(a5) ; RV64I-WITH-FP-NEXT: lw a6, 104(a5)
; RV64I-WITH-FP-NEXT: lw a4, 108(a5) ; RV64I-WITH-FP-NEXT: lw a4, 108(a5)
; RV64I-WITH-FP-NEXT: lw a0, 124(a5) ; RV64I-WITH-FP-NEXT: lw a0, 124(a5)
; RV64I-WITH-FP-NEXT: lw a1, 120(a5) ; RV64I-WITH-FP-NEXT: lw a1, 120(a5)
; RV64I-WITH-FP-NEXT: lw a2, 116(a5) ; RV64I-WITH-FP-NEXT: lw a2, 116(a5)
; RV64I-WITH-FP-NEXT: lw a3, 112(a5) ; RV64I-WITH-FP-NEXT: lw a3, 112(a5)
; RV64I-WITH-FP-NEXT: sw a0, 124(a5) ; RV64I-WITH-FP-NEXT: sw a0, 124(a5)
; RV64I-WITH-FP-NEXT: sw a1, 120(a5) ; RV64I-WITH-FP-NEXT: sw a1, 120(a5)
; RV64I-WITH-FP-NEXT: sw a2, 116(a5) ; RV64I-WITH-FP-NEXT: sw a2, 116(a5)
; RV64I-WITH-FP-NEXT: sw a3, 112(a5) ; RV64I-WITH-FP-NEXT: sw a3, 112(a5)
; RV64I-WITH-FP-NEXT: sw a4, 108(a5) ; RV64I-WITH-FP-NEXT: sw a4, 108(a5)
; RV64I-WITH-FP-NEXT: sw a6, 104(a5) ; RV64I-WITH-FP-NEXT: sw a6, 104(a5)
; RV64I-WITH-FP-NEXT: sw t0, 100(a5) ; RV64I-WITH-FP-NEXT: sw t0, 100(a5)
; RV64I-WITH-FP-NEXT: sw t1, 96(a5) ; RV64I-WITH-FP-NEXT: sw ra, 96(a5)
; RV64I-WITH-FP-NEXT: sw s1, 92(a5) ; RV64I-WITH-FP-NEXT: sw s11, 92(a5)
; RV64I-WITH-FP-NEXT: sw t2, 88(a5) ; RV64I-WITH-FP-NEXT: sw s10, 88(a5)
; RV64I-WITH-FP-NEXT: sw t3, 84(a5) ; RV64I-WITH-FP-NEXT: sw s9, 84(a5)
; RV64I-WITH-FP-NEXT: sw t4, 80(a5) ; RV64I-WITH-FP-NEXT: sw s8, 80(a5)
; RV64I-WITH-FP-NEXT: sw ra, 76(a5) ; RV64I-WITH-FP-NEXT: sw s7, 76(a5)
; RV64I-WITH-FP-NEXT: sw s11, 72(a5) ; RV64I-WITH-FP-NEXT: sw s6, 72(a5)
; RV64I-WITH-FP-NEXT: sw s10, 68(a5) ; RV64I-WITH-FP-NEXT: sw s5, 68(a5)
; RV64I-WITH-FP-NEXT: sw s9, 64(a5) ; RV64I-WITH-FP-NEXT: sw s4, 64(a5)
; RV64I-WITH-FP-NEXT: sw s8, 60(a5) ; RV64I-WITH-FP-NEXT: sw s3, 60(a5)
; RV64I-WITH-FP-NEXT: sw s7, 56(a5) ; RV64I-WITH-FP-NEXT: sw s2, 56(a5)
; RV64I-WITH-FP-NEXT: sw s6, 52(a5) ; RV64I-WITH-FP-NEXT: sw s1, 52(a5)
; RV64I-WITH-FP-NEXT: sw s5, 48(a5) ; RV64I-WITH-FP-NEXT: sw t6, 48(a5)
; RV64I-WITH-FP-NEXT: sw s4, 44(a5) ; RV64I-WITH-FP-NEXT: sw t5, 44(a5)
; RV64I-WITH-FP-NEXT: sw s3, 40(a5) ; RV64I-WITH-FP-NEXT: sw t4, 40(a5)
; RV64I-WITH-FP-NEXT: sw s2, 36(a5) ; RV64I-WITH-FP-NEXT: sw t3, 36(a5)
; RV64I-WITH-FP-NEXT: sw t6, 32(a5) ; RV64I-WITH-FP-NEXT: sw t2, 32(a5)
; RV64I-WITH-FP-NEXT: sw t5, 28(a5) ; RV64I-WITH-FP-NEXT: sw t1, 28(a5)
; RV64I-WITH-FP-NEXT: ld a0, -160(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -160(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 24(a5) ; RV64I-WITH-FP-NEXT: sw a0, 24(a5)
; RV64I-WITH-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 20(a5) ; RV64I-WITH-FP-NEXT: sw a0, 20(a5)
; RV64I-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 16(a5) ; RV64I-WITH-FP-NEXT: sw a0, 16(a5)
; RV64I-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, %lo(var+12)(a7) ; RV64I-WITH-FP-NEXT: sw a0, %lo(var+12)(a7)
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; RV32I-NEXT: lw a0, %lo(var)(s0) ; RV32I-NEXT: lw a0, %lo(var)(s0)
; RV32I-NEXT: sw a0, 88(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 88(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, %lo(var+4)(s0) ; RV32I-NEXT: lw a0, %lo(var+4)(s0)
; RV32I-NEXT: sw a0, 84(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 84(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, %lo(var+8)(s0) ; RV32I-NEXT: lw a0, %lo(var+8)(s0)
; RV32I-NEXT: sw a0, 80(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 80(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, %lo(var+12)(s0) ; RV32I-NEXT: lw a0, %lo(var+12)(s0)
; RV32I-NEXT: sw a0, 76(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s1, s0, %lo(var) ; RV32I-NEXT: addi s5, s0, %lo(var)
; RV32I-NEXT: lw a0, 16(s1) ; RV32I-NEXT: lw a0, 16(s5)
; RV32I-NEXT: sw a0, 72(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 72(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 20(s1) ; RV32I-NEXT: lw a0, 20(s5)
; RV32I-NEXT: sw a0, 68(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 68(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 24(s1) ; RV32I-NEXT: lw a0, 24(s5)
; RV32I-NEXT: sw a0, 64(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 64(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 28(s1) ; RV32I-NEXT: lw a0, 28(s5)
; RV32I-NEXT: sw a0, 60(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 32(s1) ; RV32I-NEXT: lw a0, 32(s5)
; RV32I-NEXT: sw a0, 56(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 56(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 36(s1) ; RV32I-NEXT: lw a0, 36(s5)
; RV32I-NEXT: sw a0, 52(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 52(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 40(s1) ; RV32I-NEXT: lw a0, 40(s5)
; RV32I-NEXT: sw a0, 48(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 44(s1) ; RV32I-NEXT: lw a0, 44(s5)
; RV32I-NEXT: sw a0, 44(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 48(s1) ; RV32I-NEXT: lw a0, 48(s5)
; RV32I-NEXT: sw a0, 40(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 52(s1) ; RV32I-NEXT: lw a0, 52(s5)
; RV32I-NEXT: sw a0, 36(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 56(s1) ; RV32I-NEXT: lw a0, 56(s5)
; RV32I-NEXT: sw a0, 32(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 60(s1) ; RV32I-NEXT: lw a0, 60(s5)
; RV32I-NEXT: sw a0, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 64(s1) ; RV32I-NEXT: lw a0, 64(s5)
; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 68(s1) ; RV32I-NEXT: lw a0, 68(s5)
; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 72(s1) ; RV32I-NEXT: lw a0, 72(s5)
; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 76(s1) ; RV32I-NEXT: lw a0, 76(s5)
; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 80(s1) ; RV32I-NEXT: lw a0, 80(s5)
; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a0, 84(s1) ; RV32I-NEXT: lw a0, 84(s5)
; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw s4, 88(s1) ; RV32I-NEXT: lw s3, 88(s5)
; RV32I-NEXT: lw s5, 92(s1) ; RV32I-NEXT: lw s4, 92(s5)
; RV32I-NEXT: lw s6, 96(s1) ; RV32I-NEXT: lw s6, 96(s5)
; RV32I-NEXT: lw s7, 100(s1) ; RV32I-NEXT: lw s7, 100(s5)
; RV32I-NEXT: lw s8, 104(s1) ; RV32I-NEXT: lw s8, 104(s5)
; RV32I-NEXT: lw s9, 108(s1) ; RV32I-NEXT: lw s9, 108(s5)
; RV32I-NEXT: lw s10, 112(s1) ; RV32I-NEXT: lw s10, 112(s5)
; RV32I-NEXT: lw s11, 116(s1) ; RV32I-NEXT: lw s11, 116(s5)
; RV32I-NEXT: lw s2, 120(s1) ; RV32I-NEXT: lw s1, 120(s5)
; RV32I-NEXT: lw s3, 124(s1) ; RV32I-NEXT: lw s2, 124(s5)
; RV32I-NEXT: call callee@plt ; RV32I-NEXT: call callee@plt
; RV32I-NEXT: sw s3, 124(s1) ; RV32I-NEXT: sw s2, 124(s5)
; RV32I-NEXT: sw s2, 120(s1) ; RV32I-NEXT: sw s1, 120(s5)
; RV32I-NEXT: sw s11, 116(s1) ; RV32I-NEXT: sw s11, 116(s5)
; RV32I-NEXT: sw s10, 112(s1) ; RV32I-NEXT: sw s10, 112(s5)
; RV32I-NEXT: sw s9, 108(s1) ; RV32I-NEXT: sw s9, 108(s5)
; RV32I-NEXT: sw s8, 104(s1) ; RV32I-NEXT: sw s8, 104(s5)
; RV32I-NEXT: sw s7, 100(s1) ; RV32I-NEXT: sw s7, 100(s5)
; RV32I-NEXT: sw s6, 96(s1) ; RV32I-NEXT: sw s6, 96(s5)
; RV32I-NEXT: sw s5, 92(s1) ; RV32I-NEXT: sw s4, 92(s5)
; RV32I-NEXT: sw s4, 88(s1) ; RV32I-NEXT: sw s3, 88(s5)
; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 84(s1) ; RV32I-NEXT: sw a0, 84(s5)
; RV32I-NEXT: lw a0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 80(s1) ; RV32I-NEXT: sw a0, 80(s5)
; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 76(s1) ; RV32I-NEXT: sw a0, 76(s5)
; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 72(s1) ; RV32I-NEXT: sw a0, 72(s5)
; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 68(s1) ; RV32I-NEXT: sw a0, 68(s5)
; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 64(s1) ; RV32I-NEXT: sw a0, 64(s5)
; RV32I-NEXT: lw a0, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 60(s1) ; RV32I-NEXT: sw a0, 60(s5)
; RV32I-NEXT: lw a0, 32(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 56(s1) ; RV32I-NEXT: sw a0, 56(s5)
; RV32I-NEXT: lw a0, 36(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 52(s1) ; RV32I-NEXT: sw a0, 52(s5)
; RV32I-NEXT: lw a0, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 48(s1) ; RV32I-NEXT: sw a0, 48(s5)
; RV32I-NEXT: lw a0, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 44(s1) ; RV32I-NEXT: sw a0, 44(s5)
; RV32I-NEXT: lw a0, 48(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 40(s1) ; RV32I-NEXT: sw a0, 40(s5)
; RV32I-NEXT: lw a0, 52(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 36(s1) ; RV32I-NEXT: sw a0, 36(s5)
; RV32I-NEXT: lw a0, 56(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 32(s1) ; RV32I-NEXT: sw a0, 32(s5)
; RV32I-NEXT: lw a0, 60(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 28(s1) ; RV32I-NEXT: sw a0, 28(s5)
; RV32I-NEXT: lw a0, 64(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 64(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 24(s1) ; RV32I-NEXT: sw a0, 24(s5)
; RV32I-NEXT: lw a0, 68(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 68(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 20(s1) ; RV32I-NEXT: sw a0, 20(s5)
; RV32I-NEXT: lw a0, 72(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 72(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, 16(s1) ; RV32I-NEXT: sw a0, 16(s5)
; RV32I-NEXT: lw a0, 76(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 76(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, %lo(var+12)(s0) ; RV32I-NEXT: sw a0, %lo(var+12)(s0)
; RV32I-NEXT: lw a0, 80(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 80(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, %lo(var+8)(s0) ; RV32I-NEXT: sw a0, %lo(var+8)(s0)
; RV32I-NEXT: lw a0, 84(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 84(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, %lo(var+4)(s0) ; RV32I-NEXT: sw a0, %lo(var+4)(s0)
; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload
; RV32I-NEXT: sw a0, %lo(var)(s0) ; RV32I-NEXT: sw a0, %lo(var)(s0)
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; RV32I-WITH-FP-NEXT: sw s5, 116(sp) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw s5, 116(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s6, 112(sp) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw s6, 112(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s7, 108(sp) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw s7, 108(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s8, 104(sp) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw s8, 104(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s9, 100(sp) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw s9, 100(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s10, 96(sp) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw s10, 96(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: sw s11, 92(sp) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw s11, 92(sp) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: addi s0, sp, 144 ; RV32I-WITH-FP-NEXT: addi s0, sp, 144
; RV32I-WITH-FP-NEXT: lui s6, %hi(var) ; RV32I-WITH-FP-NEXT: lui s1, %hi(var)
; RV32I-WITH-FP-NEXT: lw a0, %lo(var)(s6) ; RV32I-WITH-FP-NEXT: lw a0, %lo(var)(s1)
; RV32I-WITH-FP-NEXT: sw a0, -56(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -56(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, %lo(var+4)(s6) ; RV32I-WITH-FP-NEXT: lw a0, %lo(var+4)(s1)
; RV32I-WITH-FP-NEXT: sw a0, -60(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -60(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, %lo(var+8)(s6) ; RV32I-WITH-FP-NEXT: lw a0, %lo(var+8)(s1)
; RV32I-WITH-FP-NEXT: sw a0, -64(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -64(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, %lo(var+12)(s6) ; RV32I-WITH-FP-NEXT: lw a0, %lo(var+12)(s1)
; RV32I-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: addi s1, s6, %lo(var) ; RV32I-WITH-FP-NEXT: addi s6, s1, %lo(var)
; RV32I-WITH-FP-NEXT: lw a0, 16(s1) ; RV32I-WITH-FP-NEXT: lw a0, 16(s6)
; RV32I-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 20(s1) ; RV32I-WITH-FP-NEXT: lw a0, 20(s6)
; RV32I-WITH-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 24(s1) ; RV32I-WITH-FP-NEXT: lw a0, 24(s6)
; RV32I-WITH-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 28(s1) ; RV32I-WITH-FP-NEXT: lw a0, 28(s6)
; RV32I-WITH-FP-NEXT: sw a0, -84(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -84(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 32(s1) ; RV32I-WITH-FP-NEXT: lw a0, 32(s6)
; RV32I-WITH-FP-NEXT: sw a0, -88(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -88(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 36(s1) ; RV32I-WITH-FP-NEXT: lw a0, 36(s6)
; RV32I-WITH-FP-NEXT: sw a0, -92(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -92(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 40(s1) ; RV32I-WITH-FP-NEXT: lw a0, 40(s6)
; RV32I-WITH-FP-NEXT: sw a0, -96(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -96(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 44(s1) ; RV32I-WITH-FP-NEXT: lw a0, 44(s6)
; RV32I-WITH-FP-NEXT: sw a0, -100(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -100(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 48(s1) ; RV32I-WITH-FP-NEXT: lw a0, 48(s6)
; RV32I-WITH-FP-NEXT: sw a0, -104(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -104(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 52(s1) ; RV32I-WITH-FP-NEXT: lw a0, 52(s6)
; RV32I-WITH-FP-NEXT: sw a0, -108(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -108(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 56(s1) ; RV32I-WITH-FP-NEXT: lw a0, 56(s6)
; RV32I-WITH-FP-NEXT: sw a0, -112(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -112(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 60(s1) ; RV32I-WITH-FP-NEXT: lw a0, 60(s6)
; RV32I-WITH-FP-NEXT: sw a0, -116(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -116(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 64(s1) ; RV32I-WITH-FP-NEXT: lw a0, 64(s6)
; RV32I-WITH-FP-NEXT: sw a0, -120(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -120(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 68(s1) ; RV32I-WITH-FP-NEXT: lw a0, 68(s6)
; RV32I-WITH-FP-NEXT: sw a0, -124(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -124(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 72(s1) ; RV32I-WITH-FP-NEXT: lw a0, 72(s6)
; RV32I-WITH-FP-NEXT: sw a0, -128(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -128(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 76(s1) ; RV32I-WITH-FP-NEXT: lw a0, 76(s6)
; RV32I-WITH-FP-NEXT: sw a0, -132(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -132(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 80(s1) ; RV32I-WITH-FP-NEXT: lw a0, 80(s6)
; RV32I-WITH-FP-NEXT: sw a0, -136(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -136(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 84(s1) ; RV32I-WITH-FP-NEXT: lw a0, 84(s6)
; RV32I-WITH-FP-NEXT: sw a0, -140(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -140(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw a0, 88(s1) ; RV32I-WITH-FP-NEXT: lw a0, 88(s6)
; RV32I-WITH-FP-NEXT: sw a0, -144(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw a0, -144(s0) # 4-byte Folded Spill
; RV32I-WITH-FP-NEXT: lw s8, 92(s1) ; RV32I-WITH-FP-NEXT: lw s8, 92(s6)
; RV32I-WITH-FP-NEXT: lw s9, 96(s1) ; RV32I-WITH-FP-NEXT: lw s9, 96(s6)
; RV32I-WITH-FP-NEXT: lw s10, 100(s1) ; RV32I-WITH-FP-NEXT: lw s10, 100(s6)
; RV32I-WITH-FP-NEXT: lw s11, 104(s1) ; RV32I-WITH-FP-NEXT: lw s11, 104(s6)
; RV32I-WITH-FP-NEXT: lw s2, 108(s1) ; RV32I-WITH-FP-NEXT: lw s2, 108(s6)
; RV32I-WITH-FP-NEXT: lw s3, 112(s1) ; RV32I-WITH-FP-NEXT: lw s3, 112(s6)
; RV32I-WITH-FP-NEXT: lw s4, 116(s1) ; RV32I-WITH-FP-NEXT: lw s4, 116(s6)
; RV32I-WITH-FP-NEXT: lw s5, 120(s1) ; RV32I-WITH-FP-NEXT: lw s5, 120(s6)
; RV32I-WITH-FP-NEXT: lw s7, 124(s1) ; RV32I-WITH-FP-NEXT: lw s7, 124(s6)
; RV32I-WITH-FP-NEXT: call callee@plt ; RV32I-WITH-FP-NEXT: call callee@plt
; RV32I-WITH-FP-NEXT: sw s7, 124(s1) ; RV32I-WITH-FP-NEXT: sw s7, 124(s6)
; RV32I-WITH-FP-NEXT: sw s5, 120(s1) ; RV32I-WITH-FP-NEXT: sw s5, 120(s6)
; RV32I-WITH-FP-NEXT: sw s4, 116(s1) ; RV32I-WITH-FP-NEXT: sw s4, 116(s6)
; RV32I-WITH-FP-NEXT: sw s3, 112(s1) ; RV32I-WITH-FP-NEXT: sw s3, 112(s6)
; RV32I-WITH-FP-NEXT: sw s2, 108(s1) ; RV32I-WITH-FP-NEXT: sw s2, 108(s6)
; RV32I-WITH-FP-NEXT: sw s11, 104(s1) ; RV32I-WITH-FP-NEXT: sw s11, 104(s6)
; RV32I-WITH-FP-NEXT: sw s10, 100(s1) ; RV32I-WITH-FP-NEXT: sw s10, 100(s6)
; RV32I-WITH-FP-NEXT: sw s9, 96(s1) ; RV32I-WITH-FP-NEXT: sw s9, 96(s6)
; RV32I-WITH-FP-NEXT: sw s8, 92(s1) ; RV32I-WITH-FP-NEXT: sw s8, 92(s6)
; RV32I-WITH-FP-NEXT: lw a0, -144(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -144(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 88(s1) ; RV32I-WITH-FP-NEXT: sw a0, 88(s6)
; RV32I-WITH-FP-NEXT: lw a0, -140(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -140(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 84(s1) ; RV32I-WITH-FP-NEXT: sw a0, 84(s6)
; RV32I-WITH-FP-NEXT: lw a0, -136(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -136(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 80(s1) ; RV32I-WITH-FP-NEXT: sw a0, 80(s6)
; RV32I-WITH-FP-NEXT: lw a0, -132(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -132(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 76(s1) ; RV32I-WITH-FP-NEXT: sw a0, 76(s6)
; RV32I-WITH-FP-NEXT: lw a0, -128(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -128(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 72(s1) ; RV32I-WITH-FP-NEXT: sw a0, 72(s6)
; RV32I-WITH-FP-NEXT: lw a0, -124(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -124(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 68(s1) ; RV32I-WITH-FP-NEXT: sw a0, 68(s6)
; RV32I-WITH-FP-NEXT: lw a0, -120(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -120(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 64(s1) ; RV32I-WITH-FP-NEXT: sw a0, 64(s6)
; RV32I-WITH-FP-NEXT: lw a0, -116(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -116(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 60(s1) ; RV32I-WITH-FP-NEXT: sw a0, 60(s6)
; RV32I-WITH-FP-NEXT: lw a0, -112(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -112(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 56(s1) ; RV32I-WITH-FP-NEXT: sw a0, 56(s6)
; RV32I-WITH-FP-NEXT: lw a0, -108(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -108(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 52(s1) ; RV32I-WITH-FP-NEXT: sw a0, 52(s6)
; RV32I-WITH-FP-NEXT: lw a0, -104(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -104(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 48(s1) ; RV32I-WITH-FP-NEXT: sw a0, 48(s6)
; RV32I-WITH-FP-NEXT: lw a0, -100(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -100(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 44(s1) ; RV32I-WITH-FP-NEXT: sw a0, 44(s6)
; RV32I-WITH-FP-NEXT: lw a0, -96(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -96(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 40(s1) ; RV32I-WITH-FP-NEXT: sw a0, 40(s6)
; RV32I-WITH-FP-NEXT: lw a0, -92(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -92(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 36(s1) ; RV32I-WITH-FP-NEXT: sw a0, 36(s6)
; RV32I-WITH-FP-NEXT: lw a0, -88(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -88(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 32(s1) ; RV32I-WITH-FP-NEXT: sw a0, 32(s6)
; RV32I-WITH-FP-NEXT: lw a0, -84(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -84(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 28(s1) ; RV32I-WITH-FP-NEXT: sw a0, 28(s6)
; RV32I-WITH-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 24(s1) ; RV32I-WITH-FP-NEXT: sw a0, 24(s6)
; RV32I-WITH-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 20(s1) ; RV32I-WITH-FP-NEXT: sw a0, 20(s6)
; RV32I-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, 16(s1) ; RV32I-WITH-FP-NEXT: sw a0, 16(s6)
; RV32I-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, %lo(var+12)(s6) ; RV32I-WITH-FP-NEXT: sw a0, %lo(var+12)(s1)
; RV32I-WITH-FP-NEXT: lw a0, -64(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -64(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, %lo(var+8)(s6) ; RV32I-WITH-FP-NEXT: sw a0, %lo(var+8)(s1)
; RV32I-WITH-FP-NEXT: lw a0, -60(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -60(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, %lo(var+4)(s6) ; RV32I-WITH-FP-NEXT: sw a0, %lo(var+4)(s1)
; RV32I-WITH-FP-NEXT: lw a0, -56(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw a0, -56(s0) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: sw a0, %lo(var)(s6) ; RV32I-WITH-FP-NEXT: sw a0, %lo(var)(s1)
; RV32I-WITH-FP-NEXT: lw ra, 140(sp) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw ra, 140(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s0, 136(sp) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw s0, 136(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s1, 132(sp) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw s1, 132(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s2, 128(sp) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw s2, 128(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s3, 124(sp) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw s3, 124(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s4, 120(sp) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw s4, 120(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s5, 116(sp) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw s5, 116(sp) # 4-byte Folded Reload
; RV32I-WITH-FP-NEXT: lw s6, 112(sp) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw s6, 112(sp) # 4-byte Folded Reload
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; RV64I-NEXT: lw a0, %lo(var)(s0) ; RV64I-NEXT: lw a0, %lo(var)(s0)
; RV64I-NEXT: sd a0, 176(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 176(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, %lo(var+4)(s0) ; RV64I-NEXT: lw a0, %lo(var+4)(s0)
; RV64I-NEXT: sd a0, 168(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 168(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, %lo(var+8)(s0) ; RV64I-NEXT: lw a0, %lo(var+8)(s0)
; RV64I-NEXT: sd a0, 160(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 160(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, %lo(var+12)(s0) ; RV64I-NEXT: lw a0, %lo(var+12)(s0)
; RV64I-NEXT: sd a0, 152(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 152(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s1, s0, %lo(var) ; RV64I-NEXT: addi s5, s0, %lo(var)
; RV64I-NEXT: lw a0, 16(s1) ; RV64I-NEXT: lw a0, 16(s5)
; RV64I-NEXT: sd a0, 144(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 144(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 20(s1) ; RV64I-NEXT: lw a0, 20(s5)
; RV64I-NEXT: sd a0, 136(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 136(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 24(s1) ; RV64I-NEXT: lw a0, 24(s5)
; RV64I-NEXT: sd a0, 128(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 128(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 28(s1) ; RV64I-NEXT: lw a0, 28(s5)
; RV64I-NEXT: sd a0, 120(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 120(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 32(s1) ; RV64I-NEXT: lw a0, 32(s5)
; RV64I-NEXT: sd a0, 112(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 112(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 36(s1) ; RV64I-NEXT: lw a0, 36(s5)
; RV64I-NEXT: sd a0, 104(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 104(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 40(s1) ; RV64I-NEXT: lw a0, 40(s5)
; RV64I-NEXT: sd a0, 96(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 96(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 44(s1) ; RV64I-NEXT: lw a0, 44(s5)
; RV64I-NEXT: sd a0, 88(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 88(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 48(s1) ; RV64I-NEXT: lw a0, 48(s5)
; RV64I-NEXT: sd a0, 80(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 80(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 52(s1) ; RV64I-NEXT: lw a0, 52(s5)
; RV64I-NEXT: sd a0, 72(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 72(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 56(s1) ; RV64I-NEXT: lw a0, 56(s5)
; RV64I-NEXT: sd a0, 64(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 64(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 60(s1) ; RV64I-NEXT: lw a0, 60(s5)
; RV64I-NEXT: sd a0, 56(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 64(s1) ; RV64I-NEXT: lw a0, 64(s5)
; RV64I-NEXT: sd a0, 48(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 68(s1) ; RV64I-NEXT: lw a0, 68(s5)
; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 72(s1) ; RV64I-NEXT: lw a0, 72(s5)
; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 76(s1) ; RV64I-NEXT: lw a0, 76(s5)
; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 80(s1) ; RV64I-NEXT: lw a0, 80(s5)
; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw a0, 84(s1) ; RV64I-NEXT: lw a0, 84(s5)
; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw s4, 88(s1) ; RV64I-NEXT: lw s3, 88(s5)
; RV64I-NEXT: lw s5, 92(s1) ; RV64I-NEXT: lw s4, 92(s5)
; RV64I-NEXT: lw s6, 96(s1) ; RV64I-NEXT: lw s6, 96(s5)
; RV64I-NEXT: lw s7, 100(s1) ; RV64I-NEXT: lw s7, 100(s5)
; RV64I-NEXT: lw s8, 104(s1) ; RV64I-NEXT: lw s8, 104(s5)
; RV64I-NEXT: lw s9, 108(s1) ; RV64I-NEXT: lw s9, 108(s5)
; RV64I-NEXT: lw s10, 112(s1) ; RV64I-NEXT: lw s10, 112(s5)
; RV64I-NEXT: lw s11, 116(s1) ; RV64I-NEXT: lw s11, 116(s5)
; RV64I-NEXT: lw s2, 120(s1) ; RV64I-NEXT: lw s1, 120(s5)
; RV64I-NEXT: lw s3, 124(s1) ; RV64I-NEXT: lw s2, 124(s5)
; RV64I-NEXT: call callee@plt ; RV64I-NEXT: call callee@plt
; RV64I-NEXT: sw s3, 124(s1) ; RV64I-NEXT: sw s2, 124(s5)
; RV64I-NEXT: sw s2, 120(s1) ; RV64I-NEXT: sw s1, 120(s5)
; RV64I-NEXT: sw s11, 116(s1) ; RV64I-NEXT: sw s11, 116(s5)
; RV64I-NEXT: sw s10, 112(s1) ; RV64I-NEXT: sw s10, 112(s5)
; RV64I-NEXT: sw s9, 108(s1) ; RV64I-NEXT: sw s9, 108(s5)
; RV64I-NEXT: sw s8, 104(s1) ; RV64I-NEXT: sw s8, 104(s5)
; RV64I-NEXT: sw s7, 100(s1) ; RV64I-NEXT: sw s7, 100(s5)
; RV64I-NEXT: sw s6, 96(s1) ; RV64I-NEXT: sw s6, 96(s5)
; RV64I-NEXT: sw s5, 92(s1) ; RV64I-NEXT: sw s4, 92(s5)
; RV64I-NEXT: sw s4, 88(s1) ; RV64I-NEXT: sw s3, 88(s5)
; RV64I-NEXT: ld a0, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 84(s1) ; RV64I-NEXT: sw a0, 84(s5)
; RV64I-NEXT: ld a0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 80(s1) ; RV64I-NEXT: sw a0, 80(s5)
; RV64I-NEXT: ld a0, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 76(s1) ; RV64I-NEXT: sw a0, 76(s5)
; RV64I-NEXT: ld a0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 72(s1) ; RV64I-NEXT: sw a0, 72(s5)
; RV64I-NEXT: ld a0, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 68(s1) ; RV64I-NEXT: sw a0, 68(s5)
; RV64I-NEXT: ld a0, 48(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 48(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 64(s1) ; RV64I-NEXT: sw a0, 64(s5)
; RV64I-NEXT: ld a0, 56(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 60(s1) ; RV64I-NEXT: sw a0, 60(s5)
; RV64I-NEXT: ld a0, 64(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 64(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 56(s1) ; RV64I-NEXT: sw a0, 56(s5)
; RV64I-NEXT: ld a0, 72(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 52(s1) ; RV64I-NEXT: sw a0, 52(s5)
; RV64I-NEXT: ld a0, 80(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 80(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 48(s1) ; RV64I-NEXT: sw a0, 48(s5)
; RV64I-NEXT: ld a0, 88(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 88(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 44(s1) ; RV64I-NEXT: sw a0, 44(s5)
; RV64I-NEXT: ld a0, 96(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 96(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 40(s1) ; RV64I-NEXT: sw a0, 40(s5)
; RV64I-NEXT: ld a0, 104(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 104(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 36(s1) ; RV64I-NEXT: sw a0, 36(s5)
; RV64I-NEXT: ld a0, 112(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 112(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 32(s1) ; RV64I-NEXT: sw a0, 32(s5)
; RV64I-NEXT: ld a0, 120(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 120(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 28(s1) ; RV64I-NEXT: sw a0, 28(s5)
; RV64I-NEXT: ld a0, 128(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 128(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 24(s1) ; RV64I-NEXT: sw a0, 24(s5)
; RV64I-NEXT: ld a0, 136(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 136(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 20(s1) ; RV64I-NEXT: sw a0, 20(s5)
; RV64I-NEXT: ld a0, 144(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 144(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, 16(s1) ; RV64I-NEXT: sw a0, 16(s5)
; RV64I-NEXT: ld a0, 152(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 152(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, %lo(var+12)(s0) ; RV64I-NEXT: sw a0, %lo(var+12)(s0)
; RV64I-NEXT: ld a0, 160(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 160(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, %lo(var+8)(s0) ; RV64I-NEXT: sw a0, %lo(var+8)(s0)
; RV64I-NEXT: ld a0, 168(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 168(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, %lo(var+4)(s0) ; RV64I-NEXT: sw a0, %lo(var+4)(s0)
; RV64I-NEXT: ld a0, 176(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld a0, 176(sp) # 8-byte Folded Reload
; RV64I-NEXT: sw a0, %lo(var)(s0) ; RV64I-NEXT: sw a0, %lo(var)(s0)
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; RV64I-WITH-FP-NEXT: sd s5, 232(sp) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd s5, 232(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s6, 224(sp) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd s6, 224(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s7, 216(sp) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd s7, 216(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s8, 208(sp) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd s8, 208(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s9, 200(sp) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd s9, 200(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s10, 192(sp) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd s10, 192(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: sd s11, 184(sp) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd s11, 184(sp) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: addi s0, sp, 288 ; RV64I-WITH-FP-NEXT: addi s0, sp, 288
; RV64I-WITH-FP-NEXT: lui s6, %hi(var) ; RV64I-WITH-FP-NEXT: lui s1, %hi(var)
; RV64I-WITH-FP-NEXT: lw a0, %lo(var)(s6) ; RV64I-WITH-FP-NEXT: lw a0, %lo(var)(s1)
; RV64I-WITH-FP-NEXT: sd a0, -112(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -112(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, %lo(var+4)(s6) ; RV64I-WITH-FP-NEXT: lw a0, %lo(var+4)(s1)
; RV64I-WITH-FP-NEXT: sd a0, -120(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -120(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, %lo(var+8)(s6) ; RV64I-WITH-FP-NEXT: lw a0, %lo(var+8)(s1)
; RV64I-WITH-FP-NEXT: sd a0, -128(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -128(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, %lo(var+12)(s6) ; RV64I-WITH-FP-NEXT: lw a0, %lo(var+12)(s1)
; RV64I-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: addi s1, s6, %lo(var) ; RV64I-WITH-FP-NEXT: addi s6, s1, %lo(var)
; RV64I-WITH-FP-NEXT: lw a0, 16(s1) ; RV64I-WITH-FP-NEXT: lw a0, 16(s6)
; RV64I-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 20(s1) ; RV64I-WITH-FP-NEXT: lw a0, 20(s6)
; RV64I-WITH-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 24(s1) ; RV64I-WITH-FP-NEXT: lw a0, 24(s6)
; RV64I-WITH-FP-NEXT: sd a0, -160(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -160(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 28(s1) ; RV64I-WITH-FP-NEXT: lw a0, 28(s6)
; RV64I-WITH-FP-NEXT: sd a0, -168(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -168(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 32(s1) ; RV64I-WITH-FP-NEXT: lw a0, 32(s6)
; RV64I-WITH-FP-NEXT: sd a0, -176(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -176(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 36(s1) ; RV64I-WITH-FP-NEXT: lw a0, 36(s6)
; RV64I-WITH-FP-NEXT: sd a0, -184(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -184(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 40(s1) ; RV64I-WITH-FP-NEXT: lw a0, 40(s6)
; RV64I-WITH-FP-NEXT: sd a0, -192(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -192(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 44(s1) ; RV64I-WITH-FP-NEXT: lw a0, 44(s6)
; RV64I-WITH-FP-NEXT: sd a0, -200(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -200(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 48(s1) ; RV64I-WITH-FP-NEXT: lw a0, 48(s6)
; RV64I-WITH-FP-NEXT: sd a0, -208(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -208(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 52(s1) ; RV64I-WITH-FP-NEXT: lw a0, 52(s6)
; RV64I-WITH-FP-NEXT: sd a0, -216(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -216(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 56(s1) ; RV64I-WITH-FP-NEXT: lw a0, 56(s6)
; RV64I-WITH-FP-NEXT: sd a0, -224(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -224(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 60(s1) ; RV64I-WITH-FP-NEXT: lw a0, 60(s6)
; RV64I-WITH-FP-NEXT: sd a0, -232(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -232(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 64(s1) ; RV64I-WITH-FP-NEXT: lw a0, 64(s6)
; RV64I-WITH-FP-NEXT: sd a0, -240(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -240(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 68(s1) ; RV64I-WITH-FP-NEXT: lw a0, 68(s6)
; RV64I-WITH-FP-NEXT: sd a0, -248(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -248(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 72(s1) ; RV64I-WITH-FP-NEXT: lw a0, 72(s6)
; RV64I-WITH-FP-NEXT: sd a0, -256(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -256(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 76(s1) ; RV64I-WITH-FP-NEXT: lw a0, 76(s6)
; RV64I-WITH-FP-NEXT: sd a0, -264(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -264(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 80(s1) ; RV64I-WITH-FP-NEXT: lw a0, 80(s6)
; RV64I-WITH-FP-NEXT: sd a0, -272(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -272(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 84(s1) ; RV64I-WITH-FP-NEXT: lw a0, 84(s6)
; RV64I-WITH-FP-NEXT: sd a0, -280(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -280(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw a0, 88(s1) ; RV64I-WITH-FP-NEXT: lw a0, 88(s6)
; RV64I-WITH-FP-NEXT: sd a0, -288(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd a0, -288(s0) # 8-byte Folded Spill
; RV64I-WITH-FP-NEXT: lw s8, 92(s1) ; RV64I-WITH-FP-NEXT: lw s8, 92(s6)
; RV64I-WITH-FP-NEXT: lw s9, 96(s1) ; RV64I-WITH-FP-NEXT: lw s9, 96(s6)
; RV64I-WITH-FP-NEXT: lw s10, 100(s1) ; RV64I-WITH-FP-NEXT: lw s10, 100(s6)
; RV64I-WITH-FP-NEXT: lw s11, 104(s1) ; RV64I-WITH-FP-NEXT: lw s11, 104(s6)
; RV64I-WITH-FP-NEXT: lw s2, 108(s1) ; RV64I-WITH-FP-NEXT: lw s2, 108(s6)
; RV64I-WITH-FP-NEXT: lw s3, 112(s1) ; RV64I-WITH-FP-NEXT: lw s3, 112(s6)
; RV64I-WITH-FP-NEXT: lw s4, 116(s1) ; RV64I-WITH-FP-NEXT: lw s4, 116(s6)
; RV64I-WITH-FP-NEXT: lw s5, 120(s1) ; RV64I-WITH-FP-NEXT: lw s5, 120(s6)
; RV64I-WITH-FP-NEXT: lw s7, 124(s1) ; RV64I-WITH-FP-NEXT: lw s7, 124(s6)
; RV64I-WITH-FP-NEXT: call callee@plt ; RV64I-WITH-FP-NEXT: call callee@plt
; RV64I-WITH-FP-NEXT: sw s7, 124(s1) ; RV64I-WITH-FP-NEXT: sw s7, 124(s6)
; RV64I-WITH-FP-NEXT: sw s5, 120(s1) ; RV64I-WITH-FP-NEXT: sw s5, 120(s6)
; RV64I-WITH-FP-NEXT: sw s4, 116(s1) ; RV64I-WITH-FP-NEXT: sw s4, 116(s6)
; RV64I-WITH-FP-NEXT: sw s3, 112(s1) ; RV64I-WITH-FP-NEXT: sw s3, 112(s6)
; RV64I-WITH-FP-NEXT: sw s2, 108(s1) ; RV64I-WITH-FP-NEXT: sw s2, 108(s6)
; RV64I-WITH-FP-NEXT: sw s11, 104(s1) ; RV64I-WITH-FP-NEXT: sw s11, 104(s6)
; RV64I-WITH-FP-NEXT: sw s10, 100(s1) ; RV64I-WITH-FP-NEXT: sw s10, 100(s6)
; RV64I-WITH-FP-NEXT: sw s9, 96(s1) ; RV64I-WITH-FP-NEXT: sw s9, 96(s6)
; RV64I-WITH-FP-NEXT: sw s8, 92(s1) ; RV64I-WITH-FP-NEXT: sw s8, 92(s6)
; RV64I-WITH-FP-NEXT: ld a0, -288(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -288(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 88(s1) ; RV64I-WITH-FP-NEXT: sw a0, 88(s6)
; RV64I-WITH-FP-NEXT: ld a0, -280(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -280(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 84(s1) ; RV64I-WITH-FP-NEXT: sw a0, 84(s6)
; RV64I-WITH-FP-NEXT: ld a0, -272(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -272(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 80(s1) ; RV64I-WITH-FP-NEXT: sw a0, 80(s6)
; RV64I-WITH-FP-NEXT: ld a0, -264(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -264(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 76(s1) ; RV64I-WITH-FP-NEXT: sw a0, 76(s6)
; RV64I-WITH-FP-NEXT: ld a0, -256(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -256(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 72(s1) ; RV64I-WITH-FP-NEXT: sw a0, 72(s6)
; RV64I-WITH-FP-NEXT: ld a0, -248(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -248(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 68(s1) ; RV64I-WITH-FP-NEXT: sw a0, 68(s6)
; RV64I-WITH-FP-NEXT: ld a0, -240(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -240(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 64(s1) ; RV64I-WITH-FP-NEXT: sw a0, 64(s6)
; RV64I-WITH-FP-NEXT: ld a0, -232(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -232(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 60(s1) ; RV64I-WITH-FP-NEXT: sw a0, 60(s6)
; RV64I-WITH-FP-NEXT: ld a0, -224(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -224(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 56(s1) ; RV64I-WITH-FP-NEXT: sw a0, 56(s6)
; RV64I-WITH-FP-NEXT: ld a0, -216(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -216(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 52(s1) ; RV64I-WITH-FP-NEXT: sw a0, 52(s6)
; RV64I-WITH-FP-NEXT: ld a0, -208(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -208(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 48(s1) ; RV64I-WITH-FP-NEXT: sw a0, 48(s6)
; RV64I-WITH-FP-NEXT: ld a0, -200(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -200(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 44(s1) ; RV64I-WITH-FP-NEXT: sw a0, 44(s6)
; RV64I-WITH-FP-NEXT: ld a0, -192(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -192(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 40(s1) ; RV64I-WITH-FP-NEXT: sw a0, 40(s6)
; RV64I-WITH-FP-NEXT: ld a0, -184(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -184(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 36(s1) ; RV64I-WITH-FP-NEXT: sw a0, 36(s6)
; RV64I-WITH-FP-NEXT: ld a0, -176(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -176(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 32(s1) ; RV64I-WITH-FP-NEXT: sw a0, 32(s6)
; RV64I-WITH-FP-NEXT: ld a0, -168(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -168(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 28(s1) ; RV64I-WITH-FP-NEXT: sw a0, 28(s6)
; RV64I-WITH-FP-NEXT: ld a0, -160(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -160(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 24(s1) ; RV64I-WITH-FP-NEXT: sw a0, 24(s6)
; RV64I-WITH-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 20(s1) ; RV64I-WITH-FP-NEXT: sw a0, 20(s6)
; RV64I-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, 16(s1) ; RV64I-WITH-FP-NEXT: sw a0, 16(s6)
; RV64I-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, %lo(var+12)(s6) ; RV64I-WITH-FP-NEXT: sw a0, %lo(var+12)(s1)
; RV64I-WITH-FP-NEXT: ld a0, -128(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -128(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, %lo(var+8)(s6) ; RV64I-WITH-FP-NEXT: sw a0, %lo(var+8)(s1)
; RV64I-WITH-FP-NEXT: ld a0, -120(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -120(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, %lo(var+4)(s6) ; RV64I-WITH-FP-NEXT: sw a0, %lo(var+4)(s1)
; RV64I-WITH-FP-NEXT: ld a0, -112(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld a0, -112(s0) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: sw a0, %lo(var)(s6) ; RV64I-WITH-FP-NEXT: sw a0, %lo(var)(s1)
; RV64I-WITH-FP-NEXT: ld ra, 280(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld ra, 280(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s0, 272(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld s0, 272(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s1, 264(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld s1, 264(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s2, 256(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld s2, 256(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s3, 248(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld s3, 248(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s4, 240(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld s4, 240(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s5, 232(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld s5, 232(sp) # 8-byte Folded Reload
; RV64I-WITH-FP-NEXT: ld s6, 224(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld s6, 224(sp) # 8-byte Folded Reload
Show All 13 Lines

llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll

Show First 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
} }
; Check that i128 and fp128 are passed indirectly ; Check that i128 and fp128 are passed indirectly
define i32 @callee_large_scalars(i128 %a, fp128 %b) nounwind { define i32 @callee_large_scalars(i128 %a, fp128 %b) nounwind {
; RV32I-FPELIM-LABEL: callee_large_scalars: ; RV32I-FPELIM-LABEL: callee_large_scalars:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw a6, 0(a1) ; RV32I-FPELIM-NEXT: lw a2, 0(a1)
; RV32I-FPELIM-NEXT: lw a7, 0(a0) ; RV32I-FPELIM-NEXT: lw a3, 0(a0)
; RV32I-FPELIM-NEXT: lw a4, 4(a1) ; RV32I-FPELIM-NEXT: lw a4, 4(a1)
; RV32I-FPELIM-NEXT: lw a5, 12(a1) ; RV32I-FPELIM-NEXT: lw a5, 12(a1)
; RV32I-FPELIM-NEXT: lw a2, 12(a0) ; RV32I-FPELIM-NEXT: lw a6, 12(a0)
; RV32I-FPELIM-NEXT: lw a3, 4(a0) ; RV32I-FPELIM-NEXT: lw a7, 4(a0)
; RV32I-FPELIM-NEXT: lw a1, 8(a1) ; RV32I-FPELIM-NEXT: lw a1, 8(a1)
; RV32I-FPELIM-NEXT: lw a0, 8(a0) ; RV32I-FPELIM-NEXT: lw a0, 8(a0)
; RV32I-FPELIM-NEXT: xor a2, a2, a5 ; RV32I-FPELIM-NEXT: xor a5, a6, a5
; RV32I-FPELIM-NEXT: xor a3, a3, a4 ; RV32I-FPELIM-NEXT: xor a4, a7, a4
; RV32I-FPELIM-NEXT: or a2, a3, a2 ; RV32I-FPELIM-NEXT: or a4, a4, a5
; RV32I-FPELIM-NEXT: xor a0, a0, a1 ; RV32I-FPELIM-NEXT: xor a0, a0, a1
; RV32I-FPELIM-NEXT: xor a1, a7, a6 ; RV32I-FPELIM-NEXT: xor a1, a3, a2
; RV32I-FPELIM-NEXT: or a0, a1, a0 ; RV32I-FPELIM-NEXT: or a0, a1, a0
; RV32I-FPELIM-NEXT: or a0, a0, a2 ; RV32I-FPELIM-NEXT: or a0, a0, a4
; RV32I-FPELIM-NEXT: seqz a0, a0 ; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_large_scalars: ; RV32I-WITHFP-LABEL: callee_large_scalars:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a6, 0(a1) ; RV32I-WITHFP-NEXT: lw a2, 0(a1)
; RV32I-WITHFP-NEXT: lw a7, 0(a0) ; RV32I-WITHFP-NEXT: lw a3, 0(a0)
; RV32I-WITHFP-NEXT: lw a4, 4(a1) ; RV32I-WITHFP-NEXT: lw a4, 4(a1)
; RV32I-WITHFP-NEXT: lw a5, 12(a1) ; RV32I-WITHFP-NEXT: lw a5, 12(a1)
; RV32I-WITHFP-NEXT: lw a2, 12(a0) ; RV32I-WITHFP-NEXT: lw a6, 12(a0)
; RV32I-WITHFP-NEXT: lw a3, 4(a0) ; RV32I-WITHFP-NEXT: lw a7, 4(a0)
; RV32I-WITHFP-NEXT: lw a1, 8(a1) ; RV32I-WITHFP-NEXT: lw a1, 8(a1)
; RV32I-WITHFP-NEXT: lw a0, 8(a0) ; RV32I-WITHFP-NEXT: lw a0, 8(a0)
; RV32I-WITHFP-NEXT: xor a2, a2, a5 ; RV32I-WITHFP-NEXT: xor a5, a6, a5
; RV32I-WITHFP-NEXT: xor a3, a3, a4 ; RV32I-WITHFP-NEXT: xor a4, a7, a4
; RV32I-WITHFP-NEXT: or a2, a3, a2 ; RV32I-WITHFP-NEXT: or a4, a4, a5
; RV32I-WITHFP-NEXT: xor a0, a0, a1 ; RV32I-WITHFP-NEXT: xor a0, a0, a1
; RV32I-WITHFP-NEXT: xor a1, a7, a6 ; RV32I-WITHFP-NEXT: xor a1, a3, a2
; RV32I-WITHFP-NEXT: or a0, a1, a0 ; RV32I-WITHFP-NEXT: or a0, a1, a0
; RV32I-WITHFP-NEXT: or a0, a0, a2 ; RV32I-WITHFP-NEXT: or a0, a0, a4
; RV32I-WITHFP-NEXT: seqz a0, a0 ; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%b_bitcast = bitcast fp128 %b to i128 %b_bitcast = bitcast fp128 %b to i128
%1 = icmp eq i128 %a, %b_bitcast %1 = icmp eq i128 %a, %b_bitcast
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; Check that arguments larger than 2*xlen are handled correctly when their ; Check that arguments larger than 2*xlen are handled correctly when their
; address is passed on the stack rather than in memory ; address is passed on the stack rather than in memory
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_large_scalars_exhausted_regs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i128 %h, i32 %i, fp128 %j) nounwind { define i32 @callee_large_scalars_exhausted_regs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i128 %h, i32 %i, fp128 %j) nounwind {
; RV32I-FPELIM-LABEL: callee_large_scalars_exhausted_regs: ; RV32I-FPELIM-LABEL: callee_large_scalars_exhausted_regs:
; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw a0, 4(sp) ; RV32I-FPELIM-NEXT: lw a0, 4(sp)
; RV32I-FPELIM-NEXT: lw a6, 0(a0) ; RV32I-FPELIM-NEXT: lw a1, 0(a0)
; RV32I-FPELIM-NEXT: lw t0, 0(a7) ; RV32I-FPELIM-NEXT: lw a2, 0(a7)
; RV32I-FPELIM-NEXT: lw a3, 4(a0) ; RV32I-FPELIM-NEXT: lw a3, 4(a0)
; RV32I-FPELIM-NEXT: lw a4, 12(a0) ; RV32I-FPELIM-NEXT: lw a4, 12(a0)
; RV32I-FPELIM-NEXT: lw a5, 12(a7) ; RV32I-FPELIM-NEXT: lw a5, 12(a7)
; RV32I-FPELIM-NEXT: lw a1, 4(a7) ; RV32I-FPELIM-NEXT: lw a6, 4(a7)
; RV32I-FPELIM-NEXT: lw a0, 8(a0) ; RV32I-FPELIM-NEXT: lw a0, 8(a0)
; RV32I-FPELIM-NEXT: lw a2, 8(a7) ; RV32I-FPELIM-NEXT: lw a7, 8(a7)
; RV32I-FPELIM-NEXT: xor a4, a5, a4 ; RV32I-FPELIM-NEXT: xor a4, a5, a4
; RV32I-FPELIM-NEXT: xor a1, a1, a3 ; RV32I-FPELIM-NEXT: xor a3, a6, a3
; RV32I-FPELIM-NEXT: or a1, a1, a4 ; RV32I-FPELIM-NEXT: or a3, a3, a4
; RV32I-FPELIM-NEXT: xor a0, a2, a0 ; RV32I-FPELIM-NEXT: xor a0, a7, a0
; RV32I-FPELIM-NEXT: xor a2, t0, a6 ; RV32I-FPELIM-NEXT: xor a1, a2, a1
; RV32I-FPELIM-NEXT: or a0, a2, a0 ; RV32I-FPELIM-NEXT: or a0, a1, a0
; RV32I-FPELIM-NEXT: or a0, a0, a1 ; RV32I-FPELIM-NEXT: or a0, a0, a3
; RV32I-FPELIM-NEXT: seqz a0, a0 ; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: ret ; RV32I-FPELIM-NEXT: ret
; ;
; RV32I-WITHFP-LABEL: callee_large_scalars_exhausted_regs: ; RV32I-WITHFP-LABEL: callee_large_scalars_exhausted_regs:
; RV32I-WITHFP: # %bb.0: ; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a0, 4(s0) ; RV32I-WITHFP-NEXT: lw a0, 4(s0)
; RV32I-WITHFP-NEXT: lw a6, 0(a0) ; RV32I-WITHFP-NEXT: lw a1, 0(a0)
; RV32I-WITHFP-NEXT: lw t0, 0(a7) ; RV32I-WITHFP-NEXT: lw a2, 0(a7)
; RV32I-WITHFP-NEXT: lw a3, 4(a0) ; RV32I-WITHFP-NEXT: lw a3, 4(a0)
; RV32I-WITHFP-NEXT: lw a4, 12(a0) ; RV32I-WITHFP-NEXT: lw a4, 12(a0)
; RV32I-WITHFP-NEXT: lw a5, 12(a7) ; RV32I-WITHFP-NEXT: lw a5, 12(a7)
; RV32I-WITHFP-NEXT: lw a1, 4(a7) ; RV32I-WITHFP-NEXT: lw a6, 4(a7)
; RV32I-WITHFP-NEXT: lw a0, 8(a0) ; RV32I-WITHFP-NEXT: lw a0, 8(a0)
; RV32I-WITHFP-NEXT: lw a2, 8(a7) ; RV32I-WITHFP-NEXT: lw a7, 8(a7)
; RV32I-WITHFP-NEXT: xor a4, a5, a4 ; RV32I-WITHFP-NEXT: xor a4, a5, a4
; RV32I-WITHFP-NEXT: xor a1, a1, a3 ; RV32I-WITHFP-NEXT: xor a3, a6, a3
; RV32I-WITHFP-NEXT: or a1, a1, a4 ; RV32I-WITHFP-NEXT: or a3, a3, a4
; RV32I-WITHFP-NEXT: xor a0, a2, a0 ; RV32I-WITHFP-NEXT: xor a0, a7, a0
; RV32I-WITHFP-NEXT: xor a2, t0, a6 ; RV32I-WITHFP-NEXT: xor a1, a2, a1
; RV32I-WITHFP-NEXT: or a0, a2, a0 ; RV32I-WITHFP-NEXT: or a0, a1, a0
; RV32I-WITHFP-NEXT: or a0, a0, a1 ; RV32I-WITHFP-NEXT: or a0, a0, a3
; RV32I-WITHFP-NEXT: seqz a0, a0 ; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16 ; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret ; RV32I-WITHFP-NEXT: ret
%j_bitcast = bitcast fp128 %j to i128 %j_bitcast = bitcast fp128 %j to i128
%1 = icmp eq i128 %h, %j_bitcast %1 = icmp eq i128 %h, %j_bitcast
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
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llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines; RV64I-NEXT: ret
ret i32 %1 ret i32 %1
} }
; Check that i256 is passed indirectly. ; Check that i256 is passed indirectly.
define i64 @callee_large_scalars(i256 %a, i256 %b) nounwind { define i64 @callee_large_scalars(i256 %a, i256 %b) nounwind {
; RV64I-LABEL: callee_large_scalars: ; RV64I-LABEL: callee_large_scalars:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: ld a6, 0(a1) ; RV64I-NEXT: ld a2, 0(a1)
; RV64I-NEXT: ld a7, 0(a0) ; RV64I-NEXT: ld a3, 0(a0)
; RV64I-NEXT: ld a4, 8(a1) ; RV64I-NEXT: ld a4, 8(a1)
; RV64I-NEXT: ld a5, 24(a1) ; RV64I-NEXT: ld a5, 24(a1)
; RV64I-NEXT: ld a2, 24(a0) ; RV64I-NEXT: ld a6, 24(a0)
; RV64I-NEXT: ld a3, 8(a0) ; RV64I-NEXT: ld a7, 8(a0)
; RV64I-NEXT: ld a1, 16(a1) ; RV64I-NEXT: ld a1, 16(a1)
; RV64I-NEXT: ld a0, 16(a0) ; RV64I-NEXT: ld a0, 16(a0)
; RV64I-NEXT: xor a2, a2, a5 ; RV64I-NEXT: xor a5, a6, a5
; RV64I-NEXT: xor a3, a3, a4 ; RV64I-NEXT: xor a4, a7, a4
; RV64I-NEXT: or a2, a3, a2 ; RV64I-NEXT: or a4, a4, a5
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: xor a1, a7, a6 ; RV64I-NEXT: xor a1, a3, a2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a4
; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = icmp eq i256 %a, %b %1 = icmp eq i256 %a, %b
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @caller_large_scalars() nounwind { define i64 @caller_large_scalars() nounwind {
Show All 24 Lines
; Check that arguments larger than 2*xlen are handled correctly when their ; Check that arguments larger than 2*xlen are handled correctly when their
; address is passed on the stack rather than in memory ; address is passed on the stack rather than in memory
; Must keep define on a single line due to an update_llc_test_checks.py limitation ; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i64 @callee_large_scalars_exhausted_regs(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i256 %h, i64 %i, i256 %j) nounwind { define i64 @callee_large_scalars_exhausted_regs(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i256 %h, i64 %i, i256 %j) nounwind {
; RV64I-LABEL: callee_large_scalars_exhausted_regs: ; RV64I-LABEL: callee_large_scalars_exhausted_regs:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: ld a0, 8(sp) ; RV64I-NEXT: ld a0, 8(sp)
; RV64I-NEXT: ld a6, 0(a0) ; RV64I-NEXT: ld a1, 0(a0)
; RV64I-NEXT: ld t0, 0(a7) ; RV64I-NEXT: ld a2, 0(a7)
; RV64I-NEXT: ld a3, 8(a0) ; RV64I-NEXT: ld a3, 8(a0)
; RV64I-NEXT: ld a4, 24(a0) ; RV64I-NEXT: ld a4, 24(a0)
; RV64I-NEXT: ld a5, 24(a7) ; RV64I-NEXT: ld a5, 24(a7)
; RV64I-NEXT: ld a1, 8(a7) ; RV64I-NEXT: ld a6, 8(a7)
; RV64I-NEXT: ld a0, 16(a0) ; RV64I-NEXT: ld a0, 16(a0)
; RV64I-NEXT: ld a2, 16(a7) ; RV64I-NEXT: ld a7, 16(a7)
; RV64I-NEXT: xor a4, a5, a4 ; RV64I-NEXT: xor a4, a5, a4
; RV64I-NEXT: xor a1, a1, a3 ; RV64I-NEXT: xor a3, a6, a3
; RV64I-NEXT: or a1, a1, a4 ; RV64I-NEXT: or a3, a3, a4
; RV64I-NEXT: xor a0, a2, a0 ; RV64I-NEXT: xor a0, a7, a0
; RV64I-NEXT: xor a2, t0, a6 ; RV64I-NEXT: xor a1, a2, a1
; RV64I-NEXT: or a0, a2, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = icmp eq i256 %h, %j %1 = icmp eq i256 %h, %j
%2 = zext i1 %1 to i64 %2 = zext i1 %1 to i64
ret i64 %2 ret i64 %2
} }
define i64 @caller_large_scalars_exhausted_regs() nounwind { define i64 @caller_large_scalars_exhausted_regs() nounwind {
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llvm/test/CodeGen/RISCV/double-arith-strict.ll

Show First 20 Lines • Show All 307 Lines • ▼ Show 20 Lines
; RV32I-LABEL: fmsub_d: ; RV32I-LABEL: fmsub_d:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3 ; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: lui a0, 524288 ; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a5, a1, a0 ; RV32I-NEXT: xor a5, a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call fma@plt ; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s4, a5 ; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s5, a4 ; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s2, a3 ; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s5 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s4 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: lui a0, 524288 ; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a2, s1, a0 ; RV32I-NEXT: xor a2, s5, a0
; RV32I-NEXT: xor a5, a1, a0 ; RV32I-NEXT: xor a5, a1, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: call fma@plt ; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmadd_d: ; RV64I-LABEL: fnmadd_d:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt ; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt ; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a2, a1, 63 ; RV64I-NEXT: slli a2, a1, 63
; RV64I-NEXT: xor a1, s1, a2 ; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call fma@plt ; RV64I-NEXT: call fma@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a_ = fadd double 0.0, %a %a_ = fadd double 0.0, %a
Show All 26 Lines
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s4, a5 ; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s1, a4 ; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s4 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: lui a0, 524288 ; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a3, s0, a0 ; RV32I-NEXT: xor a3, s5, a0
; RV32I-NEXT: xor a5, a1, a0 ; RV32I-NEXT: xor a5, a1, a0
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s5 ; RV32I-NEXT: mv a2, s4
; RV32I-NEXT: call fma@plt ; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmadd_d_2: ; RV64I-LABEL: fnmadd_d_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt ; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt ; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a2, a1, 63 ; RV64I-NEXT: slli a2, a1, 63
; RV64I-NEXT: xor a1, s1, a2 ; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call fma@plt ; RV64I-NEXT: call fma@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%b_ = fadd double 0.0, %b %b_ = fadd double 0.0, %b
Show All 22 Lines
; RV32I-LABEL: fnmsub_d: ; RV32I-LABEL: fnmsub_d:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a5 ; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s3, a4 ; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s0, a3 ; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, a1, a2 ; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a4, s3 ; RV32I-NEXT: mv a4, s1
; RV32I-NEXT: mv a5, s2 ; RV32I-NEXT: mv a5, s0
; RV32I-NEXT: call fma@plt ; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; RV32I-LABEL: fnmsub_d_2: ; RV32I-LABEL: fnmsub_d_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a5 ; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s3, a4 ; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: lui a0, 524288 ; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a3, a1, a0 ; RV32I-NEXT: xor a3, a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, s3 ; RV32I-NEXT: mv a4, s1
; RV32I-NEXT: mv a5, s2 ; RV32I-NEXT: mv a5, s0
; RV32I-NEXT: call fma@plt ; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
Show All 28 Lines

llvm/test/CodeGen/RISCV/double-arith.ll

Show First 20 Lines • Show All 473 Lines • ▼ Show 20 Lines
; RV32I-LABEL: fmsub_d: ; RV32I-LABEL: fmsub_d:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3 ; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: lui a0, 524288 ; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a5, a1, a0 ; RV32I-NEXT: xor a5, a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call fma@plt ; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s4, a5 ; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s5, a4 ; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s2, a3 ; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s5 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s4 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: lui a0, 524288 ; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a2, s1, a0 ; RV32I-NEXT: xor a2, s5, a0
; RV32I-NEXT: xor a5, a1, a0 ; RV32I-NEXT: xor a5, a1, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, a2 ; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: call fma@plt ; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmadd_d: ; RV64I-LABEL: fnmadd_d:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt ; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt ; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a2, a1, 63 ; RV64I-NEXT: slli a2, a1, 63
; RV64I-NEXT: xor a1, s1, a2 ; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call fma@plt ; RV64I-NEXT: call fma@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a_ = fadd double 0.0, %a %a_ = fadd double 0.0, %a
Show All 26 Lines
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s4, a5 ; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s1, a4 ; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s4 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: lui a0, 524288 ; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a3, s0, a0 ; RV32I-NEXT: xor a3, s5, a0
; RV32I-NEXT: xor a5, a1, a0 ; RV32I-NEXT: xor a5, a1, a0
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s5 ; RV32I-NEXT: mv a2, s4
; RV32I-NEXT: call fma@plt ; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmadd_d_2: ; RV64I-LABEL: fnmadd_d_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt ; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt ; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a2, a1, 63 ; RV64I-NEXT: slli a2, a1, 63
; RV64I-NEXT: xor a1, s1, a2 ; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call fma@plt ; RV64I-NEXT: call fma@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%b_ = fadd double 0.0, %b %b_ = fadd double 0.0, %b
Show All 22 Lines
; RV32I-LABEL: fnmsub_d: ; RV32I-LABEL: fnmsub_d:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a5 ; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s3, a4 ; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s0, a3 ; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, a1, a2 ; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: mv a3, s2
; RV32I-NEXT: mv a4, s3 ; RV32I-NEXT: mv a4, s1
; RV32I-NEXT: mv a5, s2 ; RV32I-NEXT: mv a5, s0
; RV32I-NEXT: call fma@plt ; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; RV32I-LABEL: fnmsub_d_2: ; RV32I-LABEL: fnmsub_d_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a5 ; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s3, a4 ; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: mv a1, a3
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: lui a0, 524288 ; RV32I-NEXT: lui a0, 524288
; RV32I-NEXT: xor a3, a1, a0 ; RV32I-NEXT: xor a3, a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a4, s3 ; RV32I-NEXT: mv a4, s1
; RV32I-NEXT: mv a5, s2 ; RV32I-NEXT: mv a5, s0
; RV32I-NEXT: call fma@plt ; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3 ; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, a4 ; RV32I-NEXT: mv a0, a4
; RV32I-NEXT: mv a1, a5 ; RV32I-NEXT: mv a1, a5
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __muldf3@plt ; RV32I-NEXT: call __muldf3@plt
; RV32I-NEXT: mv a2, s4 ; RV32I-NEXT: mv a2, s4
; RV32I-NEXT: mv a3, s5 ; RV32I-NEXT: mv a3, s5
; RV32I-NEXT: call __subdf3@plt ; RV32I-NEXT: call __subdf3@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fmsub_d_contract: ; RV64I-LABEL: fmsub_d_contract:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt ; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __muldf3@plt
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __muldf3@plt
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __subdf3@plt ; RV64I-NEXT: call __subdf3@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%c_ = fadd double 0.0, %c ; avoid negation using xor %c_ = fadd double 0.0, %c ; avoid negation using xor
Show All 26 Lines
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a5 ; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s3, a4 ; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s0, a3 ; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s5 ; RV32I-NEXT: mv a1, s5
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s1 ; RV32I-NEXT: mv a3, s3
; RV32I-NEXT: call __muldf3@plt ; RV32I-NEXT: call __muldf3@plt
; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, a1, a2 ; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: mv a3, s3 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: call __subdf3@plt ; RV32I-NEXT: call __subdf3@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmadd_d_contract: ; RV64I-LABEL: fnmadd_d_contract:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a2
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt ; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt ; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt ; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a1, s1 ; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call __muldf3@plt ; RV64I-NEXT: call __muldf3@plt
; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __subdf3@plt ; RV64I-NEXT: call __subdf3@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a_ = fadd double 0.0, %a ; avoid negation using xor %a_ = fadd double 0.0, %a ; avoid negation using xor
%b_ = fadd double 0.0, %b ; avoid negation using xor %b_ = fadd double 0.0, %b ; avoid negation using xor
%c_ = fadd double 0.0, %c ; avoid negation using xor %c_ = fadd double 0.0, %c ; avoid negation using xor
%1 = fmul contract double %a_, %b_ %1 = fmul contract double %a_, %b_
%2 = fneg double %1 %2 = fneg double %1
%3 = fsub contract double %2, %c_ %3 = fsub contract double %2, %c_
ret double %3 ret double %3
Show All 21 Lines
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a5 ; RV32I-NEXT: mv s0, a5
; RV32I-NEXT: mv s3, a4 ; RV32I-NEXT: mv s1, a4
; RV32I-NEXT: mv s4, a3 ; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s5, a2 ; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s5 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s4 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __adddf3@plt ; RV32I-NEXT: call __adddf3@plt
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a1
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s5
; RV32I-NEXT: call __muldf3@plt ; RV32I-NEXT: call __muldf3@plt
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: mv a3, a1
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __subdf3@plt ; RV32I-NEXT: call __subdf3@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmsub_d_contract: ; RV64I-LABEL: fnmsub_d_contract:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt ; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __adddf3@plt ; RV64I-NEXT: call __adddf3@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __muldf3@plt ; RV64I-NEXT: call __muldf3@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __subdf3@plt ; RV64I-NEXT: call __subdf3@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a_ = fadd double 0.0, %a ; avoid negation using xor %a_ = fadd double 0.0, %a ; avoid negation using xor
%b_ = fadd double 0.0, %b ; avoid negation using xor %b_ = fadd double 0.0, %b ; avoid negation using xor
%1 = fmul contract double %a_, %b_ %1 = fmul contract double %a_, %b_
%2 = fsub contract double %c, %1 %2 = fsub contract double %c, %1
ret double %2 ret double %2
} }

llvm/test/CodeGen/RISCV/double-convert.ll

Show First 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 794112 ; RV32I-NEXT: lui a3, 794112
; RV32I-NEXT: li s0, 0 ; RV32I-NEXT: li s0, 0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixdfsi@plt ; RV32I-NEXT: call __fixdfsi@plt
; RV32I-NEXT: lui s5, 524288 ; RV32I-NEXT: lui s5, 524288
; RV32I-NEXT: lui s4, 524288 ; RV32I-NEXT: lui s4, 524288
; RV32I-NEXT: blt s3, s0, .LBB3_2 ; RV32I-NEXT: blt s3, s0, .LBB3_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: .LBB3_2: # %start ; RV32I-NEXT: .LBB3_2: # %start
; RV32I-NEXT: lui a0, 269824 ; RV32I-NEXT: lui a0, 269824
; RV32I-NEXT: addi a3, a0, -1 ; RV32I-NEXT: addi a3, a0, -1
; RV32I-NEXT: lui a2, 1047552 ; RV32I-NEXT: lui a2, 1047552
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: bge s0, a0, .LBB3_4 ; RV32I-NEXT: bge s0, a0, .LBB3_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: addi s4, s5, -1 ; RV32I-NEXT: addi s4, s5, -1
; RV32I-NEXT: .LBB3_4: # %start ; RV32I-NEXT: .LBB3_4: # %start
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: bne a0, s0, .LBB3_6 ; RV32I-NEXT: bne a0, s0, .LBB3_6
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s0, s4 ; RV32I-NEXT: mv s0, s4
; RV32I-NEXT: .LBB3_6: # %start ; RV32I-NEXT: .LBB3_6: # %start
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 180 Lines • ▼ Show 20 Lines
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a0, 270080 ; RV32I-NEXT: lui a0, 270080
; RV32I-NEXT: addi a3, a0, -1 ; RV32I-NEXT: addi a3, a0, -1
; RV32I-NEXT: lui a2, 1048064 ; RV32I-NEXT: lui a2, 1048064
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixunsdfsi@plt ; RV32I-NEXT: call __fixunsdfsi@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: bltz s3, .LBB6_2 ; RV32I-NEXT: bltz s3, .LBB6_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: .LBB6_2: # %start ; RV32I-NEXT: .LBB6_2: # %start
; RV32I-NEXT: li a0, -1 ; RV32I-NEXT: li a0, -1
; RV32I-NEXT: bgtz s2, .LBB6_4 ; RV32I-NEXT: bgtz s0, .LBB6_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB6_4: # %start ; RV32I-NEXT: .LBB6_4: # %start
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 292 Lines • ▼ Show 20 Lines
; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 278016 ; RV32I-NEXT: lui a0, 278016
; RV32I-NEXT: addi s3, a0, -1 ; RV32I-NEXT: addi s3, a0, -1
; RV32I-NEXT: li a2, -1 ; RV32I-NEXT: li a2, -1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a3, s3 ; RV32I-NEXT: mv a3, s3
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: lui a3, 802304 ; RV32I-NEXT: lui a3, 802304
; RV32I-NEXT: li s0, 0 ; RV32I-NEXT: li s2, 0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __fixdfdi@plt ; RV32I-NEXT: call __fixdfdi@plt
; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: blt s6, s0, .LBB12_2 ; RV32I-NEXT: blt s6, s2, .LBB12_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: .LBB12_2: # %start ; RV32I-NEXT: .LBB12_2: # %start
; RV32I-NEXT: li s6, -1 ; RV32I-NEXT: li s6, -1
; RV32I-NEXT: blt s0, s4, .LBB12_4 ; RV32I-NEXT: blt s2, s4, .LBB12_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s6, a1 ; RV32I-NEXT: mv s6, a1
; RV32I-NEXT: .LBB12_4: # %start ; RV32I-NEXT: .LBB12_4: # %start
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: mv s4, s0 ; RV32I-NEXT: mv s4, s2
; RV32I-NEXT: bne a0, s0, .LBB12_6 ; RV32I-NEXT: bne a0, s2, .LBB12_6
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s4, s6 ; RV32I-NEXT: mv s4, s6
; RV32I-NEXT: .LBB12_6: # %start ; RV32I-NEXT: .LBB12_6: # %start
; RV32I-NEXT: lui a3, 802304 ; RV32I-NEXT: lui a3, 802304
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: lui s7, 524288 ; RV32I-NEXT: lui s7, 524288
; RV32I-NEXT: lui s6, 524288 ; RV32I-NEXT: lui s6, 524288
; RV32I-NEXT: blt a0, s0, .LBB12_8 ; RV32I-NEXT: blt a0, s2, .LBB12_8
; RV32I-NEXT: # %bb.7: # %start ; RV32I-NEXT: # %bb.7: # %start
; RV32I-NEXT: mv s6, s5 ; RV32I-NEXT: mv s6, s5
; RV32I-NEXT: .LBB12_8: # %start ; RV32I-NEXT: .LBB12_8: # %start
; RV32I-NEXT: li a2, -1 ; RV32I-NEXT: li a2, -1
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a3, s3 ; RV32I-NEXT: mv a3, s3
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: bge s0, a0, .LBB12_10 ; RV32I-NEXT: bge s2, a0, .LBB12_10
; RV32I-NEXT: # %bb.9: ; RV32I-NEXT: # %bb.9:
; RV32I-NEXT: addi s6, s7, -1 ; RV32I-NEXT: addi s6, s7, -1
; RV32I-NEXT: .LBB12_10: # %start ; RV32I-NEXT: .LBB12_10: # %start
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: bne a0, s0, .LBB12_12 ; RV32I-NEXT: bne a0, s2, .LBB12_12
; RV32I-NEXT: # %bb.11: # %start ; RV32I-NEXT: # %bb.11: # %start
; RV32I-NEXT: mv s0, s6 ; RV32I-NEXT: mv s2, s6
; RV32I-NEXT: .LBB12_12: # %start ; RV32I-NEXT: .LBB12_12: # %start
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
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; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a0, 278272 ; RV32I-NEXT: lui a0, 278272
; RV32I-NEXT: addi s3, a0, -1 ; RV32I-NEXT: addi s3, a0, -1
; RV32I-NEXT: li a2, -1 ; RV32I-NEXT: li a2, -1
; RV32I-NEXT: li s2, -1 ; RV32I-NEXT: li s0, -1
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a3, s3 ; RV32I-NEXT: mv a3, s3
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixunsdfdi@plt ; RV32I-NEXT: call __fixunsdfdi@plt
; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: bltz s4, .LBB14_2 ; RV32I-NEXT: bltz s4, .LBB14_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: .LBB14_2: # %start ; RV32I-NEXT: .LBB14_2: # %start
; RV32I-NEXT: li s4, -1 ; RV32I-NEXT: li s4, -1
; RV32I-NEXT: bgtz s6, .LBB14_4 ; RV32I-NEXT: bgtz s6, .LBB14_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s4, a1 ; RV32I-NEXT: mv s4, a1
; RV32I-NEXT: .LBB14_4: # %start ; RV32I-NEXT: .LBB14_4: # %start
; RV32I-NEXT: li a2, -1 ; RV32I-NEXT: li a2, -1
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a3, s3 ; RV32I-NEXT: mv a3, s3
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: bltz a0, .LBB14_6 ; RV32I-NEXT: bltz a0, .LBB14_6
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv a1, s5 ; RV32I-NEXT: mv a1, s5
; RV32I-NEXT: .LBB14_6: # %start ; RV32I-NEXT: .LBB14_6: # %start
; RV32I-NEXT: bgtz s3, .LBB14_8 ; RV32I-NEXT: bgtz s3, .LBB14_8
; RV32I-NEXT: # %bb.7: # %start ; RV32I-NEXT: # %bb.7: # %start
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: .LBB14_8: # %start ; RV32I-NEXT: .LBB14_8: # %start
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
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; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 790016 ; RV32I-NEXT: lui a3, 790016
; RV32I-NEXT: li s0, 0 ; RV32I-NEXT: li s0, 0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixdfsi@plt ; RV32I-NEXT: call __fixdfsi@plt
; RV32I-NEXT: lui s4, 1048568 ; RV32I-NEXT: lui s4, 1048568
; RV32I-NEXT: blt s3, s0, .LBB26_2 ; RV32I-NEXT: blt s3, s0, .LBB26_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: .LBB26_2: # %start ; RV32I-NEXT: .LBB26_2: # %start
; RV32I-NEXT: lui a0, 265728 ; RV32I-NEXT: lui a0, 265728
; RV32I-NEXT: addi a3, a0, -64 ; RV32I-NEXT: addi a3, a0, -64
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: bge s0, a0, .LBB26_4 ; RV32I-NEXT: bge s0, a0, .LBB26_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: lui a0, 8 ; RV32I-NEXT: lui a0, 8
; RV32I-NEXT: addi s4, a0, -1 ; RV32I-NEXT: addi s4, a0, -1
; RV32I-NEXT: .LBB26_4: # %start ; RV32I-NEXT: .LBB26_4: # %start
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: bne a0, s0, .LBB26_6 ; RV32I-NEXT: bne a0, s0, .LBB26_6
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s0, s4 ; RV32I-NEXT: mv s0, s4
; RV32I-NEXT: .LBB26_6: # %start ; RV32I-NEXT: .LBB26_6: # %start
; RV32I-NEXT: slli a0, s0, 16 ; RV32I-NEXT: slli a0, s0, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
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; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a0, -505 ; RV64I-NEXT: li a0, -505
; RV64I-NEXT: slli a1, a0, 53 ; RV64I-NEXT: slli a1, a0, 53
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gedf2@plt ; RV64I-NEXT: call __gedf2@plt
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixdfdi@plt ; RV64I-NEXT: call __fixdfdi@plt
; RV64I-NEXT: li s1, 0 ; RV64I-NEXT: li s2, 0
; RV64I-NEXT: lui s3, 1048568 ; RV64I-NEXT: lui s3, 1048568
; RV64I-NEXT: bltz s2, .LBB26_2 ; RV64I-NEXT: bltz s1, .LBB26_2
; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: .LBB26_2: # %start ; RV64I-NEXT: .LBB26_2: # %start
; RV64I-NEXT: lui a0, 4152 ; RV64I-NEXT: lui a0, 4152
; RV64I-NEXT: addiw a0, a0, -1 ; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: slli a1, a0, 38 ; RV64I-NEXT: slli a1, a0, 38
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtdf2@plt ; RV64I-NEXT: call __gtdf2@plt
; RV64I-NEXT: bge s1, a0, .LBB26_4 ; RV64I-NEXT: bge s2, a0, .LBB26_4
; RV64I-NEXT: # %bb.3: ; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: lui a0, 8 ; RV64I-NEXT: lui a0, 8
; RV64I-NEXT: addiw s3, a0, -1 ; RV64I-NEXT: addiw s3, a0, -1
; RV64I-NEXT: .LBB26_4: # %start ; RV64I-NEXT: .LBB26_4: # %start
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unorddf2@plt ; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: bne a0, s1, .LBB26_6 ; RV64I-NEXT: bne a0, s2, .LBB26_6
; RV64I-NEXT: # %bb.5: # %start ; RV64I-NEXT: # %bb.5: # %start
; RV64I-NEXT: mv s1, s3 ; RV64I-NEXT: mv s2, s3
; RV64I-NEXT: .LBB26_6: # %start ; RV64I-NEXT: .LBB26_6: # %start
; RV64I-NEXT: slli a0, s1, 48 ; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a0, 265984 ; RV32I-NEXT: lui a0, 265984
; RV32I-NEXT: addi a3, a0, -32 ; RV32I-NEXT: addi a3, a0, -32
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixunsdfsi@plt ; RV32I-NEXT: call __fixunsdfsi@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: bltz s3, .LBB28_2 ; RV32I-NEXT: bltz s3, .LBB28_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: .LBB28_2: # %start ; RV32I-NEXT: .LBB28_2: # %start
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: bgtz s2, .LBB28_4 ; RV32I-NEXT: bgtz s0, .LBB28_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv a2, a1 ; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: .LBB28_4: # %start ; RV32I-NEXT: .LBB28_4: # %start
; RV32I-NEXT: and a0, a2, a0 ; RV32I-NEXT: and a0, a2, a0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 787968 ; RV32I-NEXT: lui a3, 787968
; RV32I-NEXT: li s0, 0 ; RV32I-NEXT: li s0, 0
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixdfsi@plt ; RV32I-NEXT: call __fixdfsi@plt
; RV32I-NEXT: li s4, -128 ; RV32I-NEXT: li s4, -128
; RV32I-NEXT: blt s3, s0, .LBB30_2 ; RV32I-NEXT: blt s3, s0, .LBB30_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: .LBB30_2: # %start ; RV32I-NEXT: .LBB30_2: # %start
; RV32I-NEXT: lui a3, 263676 ; RV32I-NEXT: lui a3, 263676
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: li s3, 127 ; RV32I-NEXT: li s3, 127
; RV32I-NEXT: blt s0, a0, .LBB30_4 ; RV32I-NEXT: blt s0, a0, .LBB30_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s3, s4 ; RV32I-NEXT: mv s3, s4
; RV32I-NEXT: .LBB30_4: # %start ; RV32I-NEXT: .LBB30_4: # %start
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s1
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: bne a0, s0, .LBB30_6 ; RV32I-NEXT: bne a0, s0, .LBB30_6
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s0, s3 ; RV32I-NEXT: mv s0, s3
; RV32I-NEXT: .LBB30_6: # %start ; RV32I-NEXT: .LBB30_6: # %start
; RV32I-NEXT: slli a0, s0, 24 ; RV32I-NEXT: slli a0, s0, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
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; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a0, -509 ; RV64I-NEXT: li a0, -509
; RV64I-NEXT: slli a1, a0, 53 ; RV64I-NEXT: slli a1, a0, 53
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gedf2@plt ; RV64I-NEXT: call __gedf2@plt
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixdfdi@plt ; RV64I-NEXT: call __fixdfdi@plt
; RV64I-NEXT: li s1, 0 ; RV64I-NEXT: li s2, 0
; RV64I-NEXT: li s3, -128 ; RV64I-NEXT: li s3, -128
; RV64I-NEXT: bltz s2, .LBB30_2 ; RV64I-NEXT: bltz s1, .LBB30_2
; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: .LBB30_2: # %start ; RV64I-NEXT: .LBB30_2: # %start
; RV64I-NEXT: lui a0, 65919 ; RV64I-NEXT: lui a0, 65919
; RV64I-NEXT: slli a1, a0, 34 ; RV64I-NEXT: slli a1, a0, 34
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtdf2@plt ; RV64I-NEXT: call __gtdf2@plt
; RV64I-NEXT: li s2, 127 ; RV64I-NEXT: li s1, 127
; RV64I-NEXT: blt s1, a0, .LBB30_4 ; RV64I-NEXT: blt s2, a0, .LBB30_4
; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: mv s2, s3 ; RV64I-NEXT: mv s1, s3
; RV64I-NEXT: .LBB30_4: # %start ; RV64I-NEXT: .LBB30_4: # %start
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unorddf2@plt ; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: bne a0, s1, .LBB30_6 ; RV64I-NEXT: bne a0, s2, .LBB30_6
; RV64I-NEXT: # %bb.5: # %start ; RV64I-NEXT: # %bb.5: # %start
; RV64I-NEXT: mv s1, s2 ; RV64I-NEXT: mv s2, s1
; RV64I-NEXT: .LBB30_6: # %start ; RV64I-NEXT: .LBB30_6: # %start
; RV64I-NEXT: slli a0, s1, 56 ; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
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; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a3, 263934 ; RV32I-NEXT: lui a3, 263934
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __gedf2@plt ; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __fixunsdfsi@plt ; RV32I-NEXT: call __fixunsdfsi@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: bltz s3, .LBB32_2 ; RV32I-NEXT: bltz s3, .LBB32_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: .LBB32_2: # %start ; RV32I-NEXT: .LBB32_2: # %start
; RV32I-NEXT: li a0, 255 ; RV32I-NEXT: li a0, 255
; RV32I-NEXT: bgtz s2, .LBB32_4 ; RV32I-NEXT: bgtz s0, .LBB32_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB32_4: # %start ; RV32I-NEXT: .LBB32_4: # %start
; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
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llvm/test/CodeGen/RISCV/double-fcmp-strict.ll

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; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3 ; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: call __eqdf2@plt ; RV32I-NEXT: call __eqdf2@plt
; RV32I-NEXT: snez s4, a0 ; RV32I-NEXT: snez s4, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: and a0, a0, s4 ; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
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; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3 ; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: call __eqdf2@plt ; RV32I-NEXT: call __eqdf2@plt
; RV32I-NEXT: seqz s4, a0 ; RV32I-NEXT: seqz s4, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: or a0, a0, s4 ; RV32I-NEXT: or a0, a0, s4
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
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; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3 ; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: call __eqdf2@plt ; RV32I-NEXT: call __eqdf2@plt
; RV32I-NEXT: snez s4, a0 ; RV32I-NEXT: snez s4, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: and a0, a0, s4 ; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3 ; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: call __eqdf2@plt ; RV32I-NEXT: call __eqdf2@plt
; RV32I-NEXT: seqz s4, a0 ; RV32I-NEXT: seqz s4, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: or a0, a0, s4 ; RV32I-NEXT: or a0, a0, s4
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
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llvm/test/CodeGen/RISCV/double-fcmp.ll

Show First 20 Lines • Show All 228 Lines • ▼ Show 20 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3 ; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: call __eqdf2@plt ; RV32I-NEXT: call __eqdf2@plt
; RV32I-NEXT: snez s4, a0 ; RV32I-NEXT: snez s4, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: and a0, a0, s4 ; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
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; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a3 ; RV32I-NEXT: mv s0, a3
; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: call __eqdf2@plt ; RV32I-NEXT: call __eqdf2@plt
; RV32I-NEXT: seqz s4, a0 ; RV32I-NEXT: seqz s4, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt ; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: or a0, a0, s4 ; RV32I-NEXT: or a0, a0, s4
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
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llvm/test/CodeGen/RISCV/float-arith-strict.ll

Show First 20 Lines • Show All 373 Lines • ▼ Show 20 Lines
; RV32I-LABEL: fnmadd_s: ; RV32I-LABEL: fnmadd_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, s1, a2 ; RV32I-NEXT: xor a1, s2, a2
; RV32I-NEXT: xor a2, a0, a2 ; RV32I-NEXT: xor a2, a0, a2
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call fmaf@plt ; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmadd_s: ; RV64I-LABEL: fnmadd_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: lui a2, 524288 ; RV64I-NEXT: lui a2, 524288
; RV64I-NEXT: xor a1, s1, a2 ; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call fmaf@plt ; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a_ = fadd float 0.0, %a %a_ = fadd float 0.0, %a
Show All 24 Lines
; RV32I-LABEL: fnmadd_s_2: ; RV32I-LABEL: fnmadd_s_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, s1, a2 ; RV32I-NEXT: xor a1, s2, a2
; RV32I-NEXT: xor a2, a0, a2 ; RV32I-NEXT: xor a2, a0, a2
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call fmaf@plt ; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmadd_s_2: ; RV64I-LABEL: fnmadd_s_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: lui a2, 524288 ; RV64I-NEXT: lui a2, 524288
; RV64I-NEXT: xor a1, s1, a2 ; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call fmaf@plt ; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%b_ = fadd float 0.0, %b %b_ = fadd float 0.0, %b
▲ Show 20 Lines • Show All 132 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-arith.ll

Show First 20 Lines • Show All 551 Lines • ▼ Show 20 Lines
; RV32I-LABEL: fnmadd_s: ; RV32I-LABEL: fnmadd_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, s1, a2 ; RV32I-NEXT: xor a1, s2, a2
; RV32I-NEXT: xor a2, a0, a2 ; RV32I-NEXT: xor a2, a0, a2
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call fmaf@plt ; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmadd_s: ; RV64I-LABEL: fnmadd_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: lui a2, 524288 ; RV64I-NEXT: lui a2, 524288
; RV64I-NEXT: xor a1, s1, a2 ; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call fmaf@plt ; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a_ = fadd float 0.0, %a %a_ = fadd float 0.0, %a
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; RV32I-LABEL: fnmadd_s_2: ; RV32I-LABEL: fnmadd_s_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, s1, a2 ; RV32I-NEXT: xor a1, s2, a2
; RV32I-NEXT: xor a2, a0, a2 ; RV32I-NEXT: xor a2, a0, a2
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call fmaf@plt ; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmadd_s_2: ; RV64I-LABEL: fnmadd_s_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: lui a2, 524288 ; RV64I-NEXT: lui a2, 524288
; RV64I-NEXT: xor a1, s1, a2 ; RV64I-NEXT: xor a1, s2, a2
; RV64I-NEXT: xor a2, a0, a2 ; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call fmaf@plt ; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%b_ = fadd float 0.0, %b %b_ = fadd float 0.0, %b
▲ Show 20 Lines • Show All 190 Lines • ▼ Show 20 Lines
; ;
; RV32I-LABEL: fmsub_s_contract: ; RV32I-LABEL: fmsub_s_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __subsf3@plt ; RV32I-NEXT: call __subsf3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fmsub_s_contract: ; RV64I-LABEL: fmsub_s_contract:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __subsf3@plt ; RV64I-NEXT: call __subsf3@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%c_ = fadd float 0.0, %c ; avoid negation using xor %c_ = fadd float 0.0, %c ; avoid negation using xor
Show All 18 Lines
; RV64IF-NEXT: fadd.s ft1, fa0, ft0 ; RV64IF-NEXT: fadd.s ft1, fa0, ft0
; RV64IF-NEXT: fadd.s ft2, fa1, ft0 ; RV64IF-NEXT: fadd.s ft2, fa1, ft0
; RV64IF-NEXT: fadd.s ft0, fa2, ft0 ; RV64IF-NEXT: fadd.s ft0, fa2, ft0
; RV64IF-NEXT: fnmadd.s fa0, ft1, ft2, ft0 ; RV64IF-NEXT: fnmadd.s fa0, ft1, ft2, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; ;
; RV32I-LABEL: fnmadd_s_contract: ; RV32I-LABEL: fnmadd_s_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s2, a2
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsf3@plt ; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __subsf3@plt ; RV32I-NEXT: call __subsf3@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmadd_s_contract: ; RV64I-LABEL: fnmadd_s_contract:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a2
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a1, s1 ; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call __mulsf3@plt ; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __subsf3@plt ; RV64I-NEXT: call __subsf3@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a_ = fadd float 0.0, %a ; avoid negation using xor %a_ = fadd float 0.0, %a ; avoid negation using xor
%b_ = fadd float 0.0, %b ; avoid negation using xor %b_ = fadd float 0.0, %b ; avoid negation using xor
%c_ = fadd float 0.0, %c ; avoid negation using xor %c_ = fadd float 0.0, %c ; avoid negation using xor
%1 = fmul contract float %a_, %b_ %1 = fmul contract float %a_, %b_
%2 = fneg float %1 %2 = fneg float %1
%3 = fsub contract float %2, %c_ %3 = fsub contract float %2, %c_
ret float %3 ret float %3
Show All 18 Lines
; ;
; RV32I-LABEL: fnmsub_s_contract: ; RV32I-LABEL: fnmsub_s_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a2 ; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __mulsf3@plt ; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __subsf3@plt ; RV32I-NEXT: call __subsf3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmsub_s_contract: ; RV64I-LABEL: fnmsub_s_contract:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __mulsf3@plt ; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __subsf3@plt ; RV64I-NEXT: call __subsf3@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a_ = fadd float 0.0, %a ; avoid negation using xor %a_ = fadd float 0.0, %a ; avoid negation using xor
%b_ = fadd float 0.0, %b ; avoid negation using xor %b_ = fadd float 0.0, %b ; avoid negation using xor
%1 = fmul contract float %a_, %b_ %1 = fmul contract float %a_, %b_
%2 = fsub contract float %c, %1 %2 = fsub contract float %c, %1
ret float %2 ret float %2
} }

llvm/test/CodeGen/RISCV/float-convert.ll

Show First 20 Lines • Show All 897 Lines • ▼ Show 20 Lines
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2@plt ; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixunssfdi@plt ; RV32I-NEXT: call __fixunssfdi@plt
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: li s5, 0 ; RV32I-NEXT: li s5, 0
; RV32I-NEXT: bltz s1, .LBB14_2 ; RV32I-NEXT: bltz s2, .LBB14_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: .LBB14_2: # %start ; RV32I-NEXT: .LBB14_2: # %start
; RV32I-NEXT: lui a0, 391168 ; RV32I-NEXT: lui a0, 391168
; RV32I-NEXT: addi s1, a0, -1 ; RV32I-NEXT: addi s4, a0, -1
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: li s2, -1
; RV32I-NEXT: li s3, -1 ; RV32I-NEXT: li s3, -1
; RV32I-NEXT: li s4, -1
; RV32I-NEXT: bgtz a0, .LBB14_4 ; RV32I-NEXT: bgtz a0, .LBB14_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s4, s5 ; RV32I-NEXT: mv s3, s5
; RV32I-NEXT: .LBB14_4: # %start ; RV32I-NEXT: .LBB14_4: # %start
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2@plt ; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: li s5, 0 ; RV32I-NEXT: li s5, 0
; RV32I-NEXT: bltz a0, .LBB14_6 ; RV32I-NEXT: bltz a0, .LBB14_6
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s5, s2 ; RV32I-NEXT: mv s5, s1
; RV32I-NEXT: .LBB14_6: # %start ; RV32I-NEXT: .LBB14_6: # %start
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: bgtz a0, .LBB14_8 ; RV32I-NEXT: bgtz a0, .LBB14_8
; RV32I-NEXT: # %bb.7: # %start ; RV32I-NEXT: # %bb.7: # %start
; RV32I-NEXT: mv s3, s5 ; RV32I-NEXT: mv s2, s5
; RV32I-NEXT: .LBB14_8: # %start ; RV32I-NEXT: .LBB14_8: # %start
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
▲ Show 20 Lines • Show All 426 Lines • ▼ Show 20 Lines
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui a1, 815104 ; RV32I-NEXT: lui a1, 815104
; RV32I-NEXT: call __gesf2@plt ; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixsfsi@plt ; RV32I-NEXT: call __fixsfsi@plt
; RV32I-NEXT: li s1, 0 ; RV32I-NEXT: li s2, 0
; RV32I-NEXT: lui s3, 1048568 ; RV32I-NEXT: lui s3, 1048568
; RV32I-NEXT: bltz s2, .LBB24_2 ; RV32I-NEXT: bltz s1, .LBB24_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: .LBB24_2: # %start ; RV32I-NEXT: .LBB24_2: # %start
; RV32I-NEXT: lui a0, 290816 ; RV32I-NEXT: lui a0, 290816
; RV32I-NEXT: addi a1, a0, -512 ; RV32I-NEXT: addi a1, a0, -512
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: bge s1, a0, .LBB24_4 ; RV32I-NEXT: bge s2, a0, .LBB24_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: lui a0, 8 ; RV32I-NEXT: lui a0, 8
; RV32I-NEXT: addi s3, a0, -1 ; RV32I-NEXT: addi s3, a0, -1
; RV32I-NEXT: .LBB24_4: # %start ; RV32I-NEXT: .LBB24_4: # %start
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __unordsf2@plt ; RV32I-NEXT: call __unordsf2@plt
; RV32I-NEXT: bne a0, s1, .LBB24_6 ; RV32I-NEXT: bne a0, s2, .LBB24_6
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s1, s3 ; RV32I-NEXT: mv s2, s3
; RV32I-NEXT: .LBB24_6: # %start ; RV32I-NEXT: .LBB24_6: # %start
; RV32I-NEXT: slli a0, s1, 16 ; RV32I-NEXT: slli a0, s2, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_w_s_sat_i16: ; RV64I-LABEL: fcvt_w_s_sat_i16:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 815104 ; RV64I-NEXT: lui a1, 815104
; RV64I-NEXT: call __gesf2@plt ; RV64I-NEXT: call __gesf2@plt
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi@plt ; RV64I-NEXT: call __fixsfdi@plt
; RV64I-NEXT: li s1, 0 ; RV64I-NEXT: li s2, 0
; RV64I-NEXT: lui s3, 1048568 ; RV64I-NEXT: lui s3, 1048568
; RV64I-NEXT: bltz s2, .LBB24_2 ; RV64I-NEXT: bltz s1, .LBB24_2
; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: .LBB24_2: # %start ; RV64I-NEXT: .LBB24_2: # %start
; RV64I-NEXT: lui a0, 290816 ; RV64I-NEXT: lui a0, 290816
; RV64I-NEXT: addiw a1, a0, -512 ; RV64I-NEXT: addiw a1, a0, -512
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: call __gtsf2@plt
; RV64I-NEXT: bge s1, a0, .LBB24_4 ; RV64I-NEXT: bge s2, a0, .LBB24_4
; RV64I-NEXT: # %bb.3: ; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: lui a0, 8 ; RV64I-NEXT: lui a0, 8
; RV64I-NEXT: addiw s3, a0, -1 ; RV64I-NEXT: addiw s3, a0, -1
; RV64I-NEXT: .LBB24_4: # %start ; RV64I-NEXT: .LBB24_4: # %start
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unordsf2@plt ; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: bne a0, s1, .LBB24_6 ; RV64I-NEXT: bne a0, s2, .LBB24_6
; RV64I-NEXT: # %bb.5: # %start ; RV64I-NEXT: # %bb.5: # %start
; RV64I-NEXT: mv s1, s3 ; RV64I-NEXT: mv s2, s3
; RV64I-NEXT: .LBB24_6: # %start ; RV64I-NEXT: .LBB24_6: # %start
; RV64I-NEXT: slli a0, s1, 48 ; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
▲ Show 20 Lines • Show All 208 Lines • ▼ Show 20 Lines
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui a1, 798720 ; RV32I-NEXT: lui a1, 798720
; RV32I-NEXT: call __gesf2@plt ; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixsfsi@plt ; RV32I-NEXT: call __fixsfsi@plt
; RV32I-NEXT: li s1, 0 ; RV32I-NEXT: li s2, 0
; RV32I-NEXT: li s3, -128 ; RV32I-NEXT: li s3, -128
; RV32I-NEXT: bltz s2, .LBB28_2 ; RV32I-NEXT: bltz s1, .LBB28_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: .LBB28_2: # %start ; RV32I-NEXT: .LBB28_2: # %start
; RV32I-NEXT: lui a1, 274400 ; RV32I-NEXT: lui a1, 274400
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: li s2, 127 ; RV32I-NEXT: li s1, 127
; RV32I-NEXT: blt s1, a0, .LBB28_4 ; RV32I-NEXT: blt s2, a0, .LBB28_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s2, s3 ; RV32I-NEXT: mv s1, s3
; RV32I-NEXT: .LBB28_4: # %start ; RV32I-NEXT: .LBB28_4: # %start
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __unordsf2@plt ; RV32I-NEXT: call __unordsf2@plt
; RV32I-NEXT: bne a0, s1, .LBB28_6 ; RV32I-NEXT: bne a0, s2, .LBB28_6
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s1, s2 ; RV32I-NEXT: mv s2, s1
; RV32I-NEXT: .LBB28_6: # %start ; RV32I-NEXT: .LBB28_6: # %start
; RV32I-NEXT: slli a0, s1, 24 ; RV32I-NEXT: slli a0, s2, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_w_s_sat_i8: ; RV64I-LABEL: fcvt_w_s_sat_i8:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 798720 ; RV64I-NEXT: lui a1, 798720
; RV64I-NEXT: call __gesf2@plt ; RV64I-NEXT: call __gesf2@plt
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi@plt ; RV64I-NEXT: call __fixsfdi@plt
; RV64I-NEXT: li s1, 0 ; RV64I-NEXT: li s2, 0
; RV64I-NEXT: li s3, -128 ; RV64I-NEXT: li s3, -128
; RV64I-NEXT: bltz s2, .LBB28_2 ; RV64I-NEXT: bltz s1, .LBB28_2
; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: .LBB28_2: # %start ; RV64I-NEXT: .LBB28_2: # %start
; RV64I-NEXT: lui a1, 274400 ; RV64I-NEXT: lui a1, 274400
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: call __gtsf2@plt
; RV64I-NEXT: li s2, 127 ; RV64I-NEXT: li s1, 127
; RV64I-NEXT: blt s1, a0, .LBB28_4 ; RV64I-NEXT: blt s2, a0, .LBB28_4
; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: mv s2, s3 ; RV64I-NEXT: mv s1, s3
; RV64I-NEXT: .LBB28_4: # %start ; RV64I-NEXT: .LBB28_4: # %start
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unordsf2@plt ; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: bne a0, s1, .LBB28_6 ; RV64I-NEXT: bne a0, s2, .LBB28_6
; RV64I-NEXT: # %bb.5: # %start ; RV64I-NEXT: # %bb.5: # %start
; RV64I-NEXT: mv s1, s2 ; RV64I-NEXT: mv s2, s1
; RV64I-NEXT: .LBB28_6: # %start ; RV64I-NEXT: .LBB28_6: # %start
; RV64I-NEXT: slli a0, s1, 56 ; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
▲ Show 20 Lines • Show All 131 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/fp128.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
@x = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16 @x = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16
@y = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16 @y = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16
; Besides anything else, these tests help verify that libcall ABI lowering ; Besides anything else, these tests help verify that libcall ABI lowering
; works correctly ; works correctly
define i32 @test_load_and_cmp() nounwind { define i32 @test_load_and_cmp() nounwind {
; RV32I-LABEL: test_load_and_cmp: ; RV32I-LABEL: test_load_and_cmp:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, %hi(x) ; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: lw a6, %lo(x)(a0) ; RV32I-NEXT: lw a2, %lo(x)(a0)
; RV32I-NEXT: lw a7, %lo(x+4)(a0) ; RV32I-NEXT: lw a1, %lo(x+4)(a0)
; RV32I-NEXT: lw a3, %lo(x+8)(a0) ; RV32I-NEXT: lw a3, %lo(x+8)(a0)
; RV32I-NEXT: lw a0, %lo(x+12)(a0) ; RV32I-NEXT: lw a0, %lo(x+12)(a0)
; RV32I-NEXT: lui a4, %hi(y) ; RV32I-NEXT: lui a4, %hi(y)
; RV32I-NEXT: lw a5, %lo(y)(a4) ; RV32I-NEXT: lw a5, %lo(y)(a4)
; RV32I-NEXT: lw a2, %lo(y+4)(a4) ; RV32I-NEXT: lw a6, %lo(y+4)(a4)
; RV32I-NEXT: lw a1, %lo(y+8)(a4) ; RV32I-NEXT: lw a7, %lo(y+8)(a4)
; RV32I-NEXT: lw a4, %lo(y+12)(a4) ; RV32I-NEXT: lw a4, %lo(y+12)(a4)
; RV32I-NEXT: sw a4, 20(sp) ; RV32I-NEXT: sw a4, 20(sp)
; RV32I-NEXT: sw a1, 16(sp) ; RV32I-NEXT: sw a7, 16(sp)
; RV32I-NEXT: sw a2, 12(sp) ; RV32I-NEXT: sw a6, 12(sp)
; RV32I-NEXT: sw a5, 8(sp) ; RV32I-NEXT: sw a5, 8(sp)
; RV32I-NEXT: sw a0, 36(sp) ; RV32I-NEXT: sw a0, 36(sp)
; RV32I-NEXT: sw a3, 32(sp) ; RV32I-NEXT: sw a3, 32(sp)
; RV32I-NEXT: sw a7, 28(sp) ; RV32I-NEXT: sw a1, 28(sp)
; RV32I-NEXT: addi a0, sp, 24 ; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8 ; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: sw a6, 24(sp) ; RV32I-NEXT: sw a2, 24(sp)
; RV32I-NEXT: call __netf2@plt ; RV32I-NEXT: call __netf2@plt
; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
%1 = load fp128, fp128* @x, align 16 %1 = load fp128, fp128* @x, align 16
%2 = load fp128, fp128* @y, align 16 %2 = load fp128, fp128* @y, align 16
%cmp = fcmp une fp128 %1, %2 %cmp = fcmp une fp128 %1, %2
%3 = zext i1 %cmp to i32 %3 = zext i1 %cmp to i32
ret i32 %3 ret i32 %3
} }
define i32 @test_add_and_fptosi() nounwind { define i32 @test_add_and_fptosi() nounwind {
; RV32I-LABEL: test_add_and_fptosi: ; RV32I-LABEL: test_add_and_fptosi:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -80 ; RV32I-NEXT: addi sp, sp, -80
; RV32I-NEXT: sw ra, 76(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, %hi(x) ; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: lw a6, %lo(x)(a0) ; RV32I-NEXT: lw a3, %lo(x)(a0)
; RV32I-NEXT: lw a7, %lo(x+4)(a0) ; RV32I-NEXT: lw a1, %lo(x+4)(a0)
; RV32I-NEXT: lw a2, %lo(x+8)(a0) ; RV32I-NEXT: lw a2, %lo(x+8)(a0)
; RV32I-NEXT: lw a0, %lo(x+12)(a0) ; RV32I-NEXT: lw a0, %lo(x+12)(a0)
; RV32I-NEXT: lui a4, %hi(y) ; RV32I-NEXT: lui a4, %hi(y)
; RV32I-NEXT: lw a5, %lo(y)(a4) ; RV32I-NEXT: lw a5, %lo(y)(a4)
; RV32I-NEXT: lw a3, %lo(y+4)(a4) ; RV32I-NEXT: lw a6, %lo(y+4)(a4)
; RV32I-NEXT: lw a1, %lo(y+8)(a4) ; RV32I-NEXT: lw a7, %lo(y+8)(a4)
; RV32I-NEXT: lw a4, %lo(y+12)(a4) ; RV32I-NEXT: lw a4, %lo(y+12)(a4)
; RV32I-NEXT: sw a4, 36(sp) ; RV32I-NEXT: sw a4, 36(sp)
; RV32I-NEXT: sw a1, 32(sp) ; RV32I-NEXT: sw a7, 32(sp)
; RV32I-NEXT: sw a3, 28(sp) ; RV32I-NEXT: sw a6, 28(sp)
; RV32I-NEXT: sw a5, 24(sp) ; RV32I-NEXT: sw a5, 24(sp)
; RV32I-NEXT: sw a0, 52(sp) ; RV32I-NEXT: sw a0, 52(sp)
; RV32I-NEXT: sw a2, 48(sp) ; RV32I-NEXT: sw a2, 48(sp)
; RV32I-NEXT: sw a7, 44(sp) ; RV32I-NEXT: sw a1, 44(sp)
; RV32I-NEXT: addi a0, sp, 56 ; RV32I-NEXT: addi a0, sp, 56
; RV32I-NEXT: addi a1, sp, 40 ; RV32I-NEXT: addi a1, sp, 40
; RV32I-NEXT: addi a2, sp, 24 ; RV32I-NEXT: addi a2, sp, 24
; RV32I-NEXT: sw a6, 40(sp) ; RV32I-NEXT: sw a3, 40(sp)
; RV32I-NEXT: call __addtf3@plt ; RV32I-NEXT: call __addtf3@plt
; RV32I-NEXT: lw a1, 56(sp) ; RV32I-NEXT: lw a1, 56(sp)
; RV32I-NEXT: lw a0, 60(sp) ; RV32I-NEXT: lw a0, 60(sp)
; RV32I-NEXT: lw a2, 64(sp) ; RV32I-NEXT: lw a2, 64(sp)
; RV32I-NEXT: lw a3, 68(sp) ; RV32I-NEXT: lw a3, 68(sp)
; RV32I-NEXT: sw a3, 20(sp) ; RV32I-NEXT: sw a3, 20(sp)
; RV32I-NEXT: sw a2, 16(sp) ; RV32I-NEXT: sw a2, 16(sp)
; RV32I-NEXT: sw a0, 12(sp) ; RV32I-NEXT: sw a0, 12(sp)
Show All 12 Lines

llvm/test/CodeGen/RISCV/fpclamptosat.ll

Show First 20 Lines • Show All 1,153 Lines • ▼ Show 20 Lines
; RV32-NEXT: .cfi_def_cfa_offset 32 ; RV32-NEXT: .cfi_def_cfa_offset 32
; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: mv a2, a1 ; RV32-NEXT: mv a2, a1
; RV32-NEXT: mv a1, a0 ; RV32-NEXT: mv a1, a0
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: call __fixdfti@plt ; RV32-NEXT: call __fixdfti@plt
; RV32-NEXT: lw a2, 20(sp) ; RV32-NEXT: lw a2, 20(sp)
; RV32-NEXT: lw t0, 16(sp) ; RV32-NEXT: lw a3, 16(sp)
; RV32-NEXT: lw a1, 12(sp) ; RV32-NEXT: lw a1, 12(sp)
; RV32-NEXT: lw a0, 8(sp) ; RV32-NEXT: lw a0, 8(sp)
; RV32-NEXT: lui a7, 524288 ; RV32-NEXT: lui a4, 524288
; RV32-NEXT: addi a5, a7, -1 ; RV32-NEXT: addi a5, a4, -1
; RV32-NEXT: beq a1, a5, .LBB18_2 ; RV32-NEXT: beq a1, a5, .LBB18_2
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: sltu a4, a1, a5 ; RV32-NEXT: sltu a7, a1, a5
; RV32-NEXT: or a3, t0, a2 ; RV32-NEXT: or a6, a3, a2
; RV32-NEXT: bnez a3, .LBB18_3 ; RV32-NEXT: bnez a6, .LBB18_3
; RV32-NEXT: j .LBB18_4 ; RV32-NEXT: j .LBB18_4
; RV32-NEXT: .LBB18_2: ; RV32-NEXT: .LBB18_2:
; RV32-NEXT: addi a4, a0, 1 ; RV32-NEXT: addi a6, a0, 1
; RV32-NEXT: snez a4, a4 ; RV32-NEXT: snez a7, a6
; RV32-NEXT: or a3, t0, a2 ; RV32-NEXT: or a6, a3, a2
; RV32-NEXT: beqz a3, .LBB18_4 ; RV32-NEXT: beqz a6, .LBB18_4
; RV32-NEXT: .LBB18_3: # %entry ; RV32-NEXT: .LBB18_3: # %entry
; RV32-NEXT: slti a4, a2, 0 ; RV32-NEXT: slti a7, a2, 0
; RV32-NEXT: .LBB18_4: # %entry ; RV32-NEXT: .LBB18_4: # %entry
; RV32-NEXT: li a6, -1 ; RV32-NEXT: li a6, -1
; RV32-NEXT: beqz a4, .LBB18_7 ; RV32-NEXT: beqz a7, .LBB18_7
; RV32-NEXT: # %bb.5: # %entry ; RV32-NEXT: # %bb.5: # %entry
; RV32-NEXT: beq a1, a7, .LBB18_8 ; RV32-NEXT: beq a1, a4, .LBB18_8
; RV32-NEXT: .LBB18_6: # %entry ; RV32-NEXT: .LBB18_6: # %entry
; RV32-NEXT: sltu a4, a7, a1 ; RV32-NEXT: sltu a4, a4, a1
; RV32-NEXT: and a3, t0, a2 ; RV32-NEXT: and a3, a3, a2
; RV32-NEXT: bne a3, a6, .LBB18_9 ; RV32-NEXT: bne a3, a6, .LBB18_9
; RV32-NEXT: j .LBB18_10 ; RV32-NEXT: j .LBB18_10
; RV32-NEXT: .LBB18_7: # %entry ; RV32-NEXT: .LBB18_7: # %entry
; RV32-NEXT: li a2, 0 ; RV32-NEXT: li a2, 0
; RV32-NEXT: li t0, 0 ; RV32-NEXT: li a3, 0
; RV32-NEXT: li a0, -1 ; RV32-NEXT: li a0, -1
; RV32-NEXT: mv a1, a5 ; RV32-NEXT: mv a1, a5
; RV32-NEXT: bne a1, a7, .LBB18_6 ; RV32-NEXT: bne a1, a4, .LBB18_6
; RV32-NEXT: .LBB18_8: ; RV32-NEXT: .LBB18_8:
; RV32-NEXT: snez a4, a0 ; RV32-NEXT: snez a4, a0
; RV32-NEXT: and a3, t0, a2 ; RV32-NEXT: and a3, a3, a2
; RV32-NEXT: beq a3, a6, .LBB18_10 ; RV32-NEXT: beq a3, a6, .LBB18_10
; RV32-NEXT: .LBB18_9: # %entry ; RV32-NEXT: .LBB18_9: # %entry
; RV32-NEXT: slt a4, a6, a2 ; RV32-NEXT: slt a4, a6, a2
; RV32-NEXT: .LBB18_10: # %entry ; RV32-NEXT: .LBB18_10: # %entry
; RV32-NEXT: bnez a4, .LBB18_12 ; RV32-NEXT: bnez a4, .LBB18_12
; RV32-NEXT: # %bb.11: # %entry ; RV32-NEXT: # %bb.11: # %entry
; RV32-NEXT: li a0, 0 ; RV32-NEXT: li a0, 0
; RV32-NEXT: lui a1, 524288 ; RV32-NEXT: lui a1, 524288
▲ Show 20 Lines • Show All 229 Lines • ▼ Show 20 Lines
; RV32-NEXT: addi sp, sp, -32 ; RV32-NEXT: addi sp, sp, -32
; RV32-NEXT: .cfi_def_cfa_offset 32 ; RV32-NEXT: .cfi_def_cfa_offset 32
; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: mv a1, a0 ; RV32-NEXT: mv a1, a0
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: call __fixsfti@plt ; RV32-NEXT: call __fixsfti@plt
; RV32-NEXT: lw a2, 20(sp) ; RV32-NEXT: lw a2, 20(sp)
; RV32-NEXT: lw t0, 16(sp) ; RV32-NEXT: lw a3, 16(sp)
; RV32-NEXT: lw a1, 12(sp) ; RV32-NEXT: lw a1, 12(sp)
; RV32-NEXT: lw a0, 8(sp) ; RV32-NEXT: lw a0, 8(sp)
; RV32-NEXT: lui a7, 524288 ; RV32-NEXT: lui a4, 524288
; RV32-NEXT: addi a5, a7, -1 ; RV32-NEXT: addi a5, a4, -1
; RV32-NEXT: beq a1, a5, .LBB21_2 ; RV32-NEXT: beq a1, a5, .LBB21_2
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: sltu a4, a1, a5 ; RV32-NEXT: sltu a7, a1, a5
; RV32-NEXT: or a3, t0, a2 ; RV32-NEXT: or a6, a3, a2
; RV32-NEXT: bnez a3, .LBB21_3 ; RV32-NEXT: bnez a6, .LBB21_3
; RV32-NEXT: j .LBB21_4 ; RV32-NEXT: j .LBB21_4
; RV32-NEXT: .LBB21_2: ; RV32-NEXT: .LBB21_2:
; RV32-NEXT: addi a4, a0, 1 ; RV32-NEXT: addi a6, a0, 1
; RV32-NEXT: snez a4, a4 ; RV32-NEXT: snez a7, a6
; RV32-NEXT: or a3, t0, a2 ; RV32-NEXT: or a6, a3, a2
; RV32-NEXT: beqz a3, .LBB21_4 ; RV32-NEXT: beqz a6, .LBB21_4
; RV32-NEXT: .LBB21_3: # %entry ; RV32-NEXT: .LBB21_3: # %entry
; RV32-NEXT: slti a4, a2, 0 ; RV32-NEXT: slti a7, a2, 0
; RV32-NEXT: .LBB21_4: # %entry ; RV32-NEXT: .LBB21_4: # %entry
; RV32-NEXT: li a6, -1 ; RV32-NEXT: li a6, -1
; RV32-NEXT: beqz a4, .LBB21_7 ; RV32-NEXT: beqz a7, .LBB21_7
; RV32-NEXT: # %bb.5: # %entry ; RV32-NEXT: # %bb.5: # %entry
; RV32-NEXT: beq a1, a7, .LBB21_8 ; RV32-NEXT: beq a1, a4, .LBB21_8
; RV32-NEXT: .LBB21_6: # %entry ; RV32-NEXT: .LBB21_6: # %entry
; RV32-NEXT: sltu a4, a7, a1 ; RV32-NEXT: sltu a4, a4, a1
; RV32-NEXT: and a3, t0, a2 ; RV32-NEXT: and a3, a3, a2
; RV32-NEXT: bne a3, a6, .LBB21_9 ; RV32-NEXT: bne a3, a6, .LBB21_9
; RV32-NEXT: j .LBB21_10 ; RV32-NEXT: j .LBB21_10
; RV32-NEXT: .LBB21_7: # %entry ; RV32-NEXT: .LBB21_7: # %entry
; RV32-NEXT: li a2, 0 ; RV32-NEXT: li a2, 0
; RV32-NEXT: li t0, 0 ; RV32-NEXT: li a3, 0
; RV32-NEXT: li a0, -1 ; RV32-NEXT: li a0, -1
; RV32-NEXT: mv a1, a5 ; RV32-NEXT: mv a1, a5
; RV32-NEXT: bne a1, a7, .LBB21_6 ; RV32-NEXT: bne a1, a4, .LBB21_6
; RV32-NEXT: .LBB21_8: ; RV32-NEXT: .LBB21_8:
; RV32-NEXT: snez a4, a0 ; RV32-NEXT: snez a4, a0
; RV32-NEXT: and a3, t0, a2 ; RV32-NEXT: and a3, a3, a2
; RV32-NEXT: beq a3, a6, .LBB21_10 ; RV32-NEXT: beq a3, a6, .LBB21_10
; RV32-NEXT: .LBB21_9: # %entry ; RV32-NEXT: .LBB21_9: # %entry
; RV32-NEXT: slt a4, a6, a2 ; RV32-NEXT: slt a4, a6, a2
; RV32-NEXT: .LBB21_10: # %entry ; RV32-NEXT: .LBB21_10: # %entry
; RV32-NEXT: bnez a4, .LBB21_12 ; RV32-NEXT: bnez a4, .LBB21_12
; RV32-NEXT: # %bb.11: # %entry ; RV32-NEXT: # %bb.11: # %entry
; RV32-NEXT: li a0, 0 ; RV32-NEXT: li a0, 0
; RV32-NEXT: lui a1, 524288 ; RV32-NEXT: lui a1, 524288
▲ Show 20 Lines • Show All 191 Lines • ▼ Show 20 Lines
; RV32-NEXT: .cfi_def_cfa_offset 32 ; RV32-NEXT: .cfi_def_cfa_offset 32
; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: call __gnu_h2f_ieee@plt ; RV32-NEXT: call __gnu_h2f_ieee@plt
; RV32-NEXT: mv a1, a0 ; RV32-NEXT: mv a1, a0
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: call __fixsfti@plt ; RV32-NEXT: call __fixsfti@plt
; RV32-NEXT: lw a2, 20(sp) ; RV32-NEXT: lw a2, 20(sp)
; RV32-NEXT: lw t0, 16(sp) ; RV32-NEXT: lw a3, 16(sp)
; RV32-NEXT: lw a1, 12(sp) ; RV32-NEXT: lw a1, 12(sp)
; RV32-NEXT: lw a0, 8(sp) ; RV32-NEXT: lw a0, 8(sp)
; RV32-NEXT: lui a7, 524288 ; RV32-NEXT: lui a4, 524288
; RV32-NEXT: addi a5, a7, -1 ; RV32-NEXT: addi a5, a4, -1
; RV32-NEXT: beq a1, a5, .LBB24_2 ; RV32-NEXT: beq a1, a5, .LBB24_2
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: sltu a4, a1, a5 ; RV32-NEXT: sltu a7, a1, a5
; RV32-NEXT: or a3, t0, a2 ; RV32-NEXT: or a6, a3, a2
; RV32-NEXT: bnez a3, .LBB24_3 ; RV32-NEXT: bnez a6, .LBB24_3
; RV32-NEXT: j .LBB24_4 ; RV32-NEXT: j .LBB24_4
; RV32-NEXT: .LBB24_2: ; RV32-NEXT: .LBB24_2:
; RV32-NEXT: addi a4, a0, 1 ; RV32-NEXT: addi a6, a0, 1
; RV32-NEXT: snez a4, a4 ; RV32-NEXT: snez a7, a6
; RV32-NEXT: or a3, t0, a2 ; RV32-NEXT: or a6, a3, a2
; RV32-NEXT: beqz a3, .LBB24_4 ; RV32-NEXT: beqz a6, .LBB24_4
; RV32-NEXT: .LBB24_3: # %entry ; RV32-NEXT: .LBB24_3: # %entry
; RV32-NEXT: slti a4, a2, 0 ; RV32-NEXT: slti a7, a2, 0
; RV32-NEXT: .LBB24_4: # %entry ; RV32-NEXT: .LBB24_4: # %entry
; RV32-NEXT: li a6, -1 ; RV32-NEXT: li a6, -1
; RV32-NEXT: beqz a4, .LBB24_7 ; RV32-NEXT: beqz a7, .LBB24_7
; RV32-NEXT: # %bb.5: # %entry ; RV32-NEXT: # %bb.5: # %entry
; RV32-NEXT: beq a1, a7, .LBB24_8 ; RV32-NEXT: beq a1, a4, .LBB24_8
; RV32-NEXT: .LBB24_6: # %entry ; RV32-NEXT: .LBB24_6: # %entry
; RV32-NEXT: sltu a4, a7, a1 ; RV32-NEXT: sltu a4, a4, a1
; RV32-NEXT: and a3, t0, a2 ; RV32-NEXT: and a3, a3, a2
; RV32-NEXT: bne a3, a6, .LBB24_9 ; RV32-NEXT: bne a3, a6, .LBB24_9
; RV32-NEXT: j .LBB24_10 ; RV32-NEXT: j .LBB24_10
; RV32-NEXT: .LBB24_7: # %entry ; RV32-NEXT: .LBB24_7: # %entry
; RV32-NEXT: li a2, 0 ; RV32-NEXT: li a2, 0
; RV32-NEXT: li t0, 0 ; RV32-NEXT: li a3, 0
; RV32-NEXT: li a0, -1 ; RV32-NEXT: li a0, -1
; RV32-NEXT: mv a1, a5 ; RV32-NEXT: mv a1, a5
; RV32-NEXT: bne a1, a7, .LBB24_6 ; RV32-NEXT: bne a1, a4, .LBB24_6
; RV32-NEXT: .LBB24_8: ; RV32-NEXT: .LBB24_8:
; RV32-NEXT: snez a4, a0 ; RV32-NEXT: snez a4, a0
; RV32-NEXT: and a3, t0, a2 ; RV32-NEXT: and a3, a3, a2
; RV32-NEXT: beq a3, a6, .LBB24_10 ; RV32-NEXT: beq a3, a6, .LBB24_10
; RV32-NEXT: .LBB24_9: # %entry ; RV32-NEXT: .LBB24_9: # %entry
; RV32-NEXT: slt a4, a6, a2 ; RV32-NEXT: slt a4, a6, a2
; RV32-NEXT: .LBB24_10: # %entry ; RV32-NEXT: .LBB24_10: # %entry
; RV32-NEXT: bnez a4, .LBB24_12 ; RV32-NEXT: bnez a4, .LBB24_12
; RV32-NEXT: # %bb.11: # %entry ; RV32-NEXT: # %bb.11: # %entry
; RV32-NEXT: li a0, 0 ; RV32-NEXT: li a0, 0
; RV32-NEXT: lui a1, 524288 ; RV32-NEXT: lui a1, 524288
▲ Show 20 Lines • Show All 1,352 Lines • ▼ Show 20 Lines
; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: mv a2, a1 ; RV32-NEXT: mv a2, a1
; RV32-NEXT: mv a1, a0 ; RV32-NEXT: mv a1, a0
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: call __fixdfti@plt ; RV32-NEXT: call __fixdfti@plt
; RV32-NEXT: lw a5, 8(sp) ; RV32-NEXT: lw a5, 8(sp)
; RV32-NEXT: lw a3, 20(sp) ; RV32-NEXT: lw a3, 20(sp)
; RV32-NEXT: lw a1, 12(sp) ; RV32-NEXT: lw a1, 12(sp)
; RV32-NEXT: li a6, -1 ; RV32-NEXT: li a2, -1
; RV32-NEXT: mv a4, a5 ; RV32-NEXT: mv a7, a5
; RV32-NEXT: bltz a3, .LBB45_2 ; RV32-NEXT: bltz a3, .LBB45_2
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: li a4, -1 ; RV32-NEXT: li a7, -1
; RV32-NEXT: .LBB45_2: # %entry ; RV32-NEXT: .LBB45_2: # %entry
; RV32-NEXT: lui a7, 524288 ; RV32-NEXT: lui a4, 524288
; RV32-NEXT: addi a2, a7, -1 ; RV32-NEXT: addi a6, a4, -1
; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv t0, a5
; RV32-NEXT: bgeu a1, a2, .LBB45_19 ; RV32-NEXT: bgeu a1, a6, .LBB45_19
; RV32-NEXT: # %bb.3: # %entry ; RV32-NEXT: # %bb.3: # %entry
; RV32-NEXT: lw t0, 16(sp) ; RV32-NEXT: lw a0, 16(sp)
; RV32-NEXT: bne a1, a2, .LBB45_20 ; RV32-NEXT: bne a1, a6, .LBB45_20
; RV32-NEXT: .LBB45_4: # %entry ; RV32-NEXT: .LBB45_4: # %entry
; RV32-NEXT: or a0, t0, a3 ; RV32-NEXT: or t0, a0, a3
; RV32-NEXT: bnez a0, .LBB45_21 ; RV32-NEXT: bnez t0, .LBB45_21
; RV32-NEXT: .LBB45_5: # %entry ; RV32-NEXT: .LBB45_5: # %entry
; RV32-NEXT: mv a4, a1 ; RV32-NEXT: mv a7, a1
; RV32-NEXT: bgez a3, .LBB45_22 ; RV32-NEXT: bgez a3, .LBB45_22
; RV32-NEXT: .LBB45_6: # %entry ; RV32-NEXT: .LBB45_6: # %entry
; RV32-NEXT: bgeu a1, a2, .LBB45_23 ; RV32-NEXT: bgeu a1, a6, .LBB45_23
; RV32-NEXT: .LBB45_7: # %entry ; RV32-NEXT: .LBB45_7: # %entry
; RV32-NEXT: bnez a0, .LBB45_24 ; RV32-NEXT: bnez t0, .LBB45_24
; RV32-NEXT: .LBB45_8: # %entry ; RV32-NEXT: .LBB45_8: # %entry
; RV32-NEXT: li a2, 0 ; RV32-NEXT: li a6, 0
; RV32-NEXT: bnez a3, .LBB45_25 ; RV32-NEXT: bnez a3, .LBB45_25
; RV32-NEXT: .LBB45_9: # %entry ; RV32-NEXT: .LBB45_9: # %entry
; RV32-NEXT: bgez a3, .LBB45_26 ; RV32-NEXT: bgez a3, .LBB45_26
; RV32-NEXT: .LBB45_10: # %entry ; RV32-NEXT: .LBB45_10: # %entry
; RV32-NEXT: mv a4, a5 ; RV32-NEXT: mv a7, a5
; RV32-NEXT: bgeu a7, a1, .LBB45_27 ; RV32-NEXT: bgeu a4, a1, .LBB45_27
; RV32-NEXT: .LBB45_11: # %entry ; RV32-NEXT: .LBB45_11: # %entry
; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv a0, a5
; RV32-NEXT: bne a1, a7, .LBB45_28 ; RV32-NEXT: bne a1, a4, .LBB45_28
; RV32-NEXT: .LBB45_12: # %entry ; RV32-NEXT: .LBB45_12: # %entry
; RV32-NEXT: bltz a3, .LBB45_29 ; RV32-NEXT: bltz a3, .LBB45_29
; RV32-NEXT: .LBB45_13: # %entry ; RV32-NEXT: .LBB45_13: # %entry
; RV32-NEXT: and a2, a2, a3 ; RV32-NEXT: and a6, a6, a3
; RV32-NEXT: bne a2, a6, .LBB45_30 ; RV32-NEXT: bne a6, a2, .LBB45_30
; RV32-NEXT: .LBB45_14: # %entry ; RV32-NEXT: .LBB45_14: # %entry
; RV32-NEXT: mv a4, a1 ; RV32-NEXT: mv a5, a1
; RV32-NEXT: bltz a3, .LBB45_31 ; RV32-NEXT: bltz a3, .LBB45_31
; RV32-NEXT: .LBB45_15: # %entry ; RV32-NEXT: .LBB45_15: # %entry
; RV32-NEXT: bgeu a7, a1, .LBB45_32 ; RV32-NEXT: bgeu a4, a1, .LBB45_32
; RV32-NEXT: .LBB45_16: # %entry ; RV32-NEXT: .LBB45_16: # %entry
; RV32-NEXT: beq a2, a6, .LBB45_18 ; RV32-NEXT: beq a6, a2, .LBB45_18
; RV32-NEXT: .LBB45_17: # %entry ; RV32-NEXT: .LBB45_17: # %entry
; RV32-NEXT: mv a1, a4 ; RV32-NEXT: mv a1, a5
; RV32-NEXT: .LBB45_18: # %entry ; RV32-NEXT: .LBB45_18: # %entry
; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 32 ; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: ret ; RV32-NEXT: ret
; RV32-NEXT: .LBB45_19: # %entry ; RV32-NEXT: .LBB45_19: # %entry
; RV32-NEXT: li a0, -1 ; RV32-NEXT: li t0, -1
; RV32-NEXT: lw t0, 16(sp) ; RV32-NEXT: lw a0, 16(sp)
; RV32-NEXT: beq a1, a2, .LBB45_4 ; RV32-NEXT: beq a1, a6, .LBB45_4
; RV32-NEXT: .LBB45_20: # %entry ; RV32-NEXT: .LBB45_20: # %entry
; RV32-NEXT: mv a5, a0 ; RV32-NEXT: mv a5, t0
; RV32-NEXT: or a0, t0, a3 ; RV32-NEXT: or t0, a0, a3
; RV32-NEXT: beqz a0, .LBB45_5 ; RV32-NEXT: beqz t0, .LBB45_5
; RV32-NEXT: .LBB45_21: # %entry ; RV32-NEXT: .LBB45_21: # %entry
; RV32-NEXT: mv a5, a4 ; RV32-NEXT: mv a5, a7
; RV32-NEXT: mv a4, a1 ; RV32-NEXT: mv a7, a1
; RV32-NEXT: bltz a3, .LBB45_6 ; RV32-NEXT: bltz a3, .LBB45_6
; RV32-NEXT: .LBB45_22: # %entry ; RV32-NEXT: .LBB45_22: # %entry
; RV32-NEXT: mv a4, a2 ; RV32-NEXT: mv a7, a6
; RV32-NEXT: bltu a1, a2, .LBB45_7 ; RV32-NEXT: bltu a1, a6, .LBB45_7
; RV32-NEXT: .LBB45_23: # %entry ; RV32-NEXT: .LBB45_23: # %entry
; RV32-NEXT: mv a1, a2 ; RV32-NEXT: mv a1, a6
; RV32-NEXT: beqz a0, .LBB45_8 ; RV32-NEXT: beqz t0, .LBB45_8
; RV32-NEXT: .LBB45_24: # %entry ; RV32-NEXT: .LBB45_24: # %entry
; RV32-NEXT: mv a1, a4 ; RV32-NEXT: mv a1, a7
; RV32-NEXT: li a2, 0 ; RV32-NEXT: li a6, 0
; RV32-NEXT: beqz a3, .LBB45_9 ; RV32-NEXT: beqz a3, .LBB45_9
; RV32-NEXT: .LBB45_25: # %entry ; RV32-NEXT: .LBB45_25: # %entry
; RV32-NEXT: srai a0, a3, 31 ; RV32-NEXT: srai a6, a3, 31
; RV32-NEXT: and a2, a0, t0 ; RV32-NEXT: and a6, a6, a0
; RV32-NEXT: bltz a3, .LBB45_10 ; RV32-NEXT: bltz a3, .LBB45_10
; RV32-NEXT: .LBB45_26: # %entry ; RV32-NEXT: .LBB45_26: # %entry
; RV32-NEXT: li a3, 0 ; RV32-NEXT: li a3, 0
; RV32-NEXT: mv a4, a5 ; RV32-NEXT: mv a7, a5
; RV32-NEXT: bltu a7, a1, .LBB45_11 ; RV32-NEXT: bltu a4, a1, .LBB45_11
; RV32-NEXT: .LBB45_27: # %entry ; RV32-NEXT: .LBB45_27: # %entry
; RV32-NEXT: li a4, 0 ; RV32-NEXT: li a7, 0
; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv a0, a5
; RV32-NEXT: beq a1, a7, .LBB45_12 ; RV32-NEXT: beq a1, a4, .LBB45_12
; RV32-NEXT: .LBB45_28: # %entry ; RV32-NEXT: .LBB45_28: # %entry
; RV32-NEXT: mv a0, a4 ; RV32-NEXT: mv a0, a7
; RV32-NEXT: bgez a3, .LBB45_13 ; RV32-NEXT: bgez a3, .LBB45_13
; RV32-NEXT: .LBB45_29: # %entry ; RV32-NEXT: .LBB45_29: # %entry
; RV32-NEXT: li a5, 0 ; RV32-NEXT: li a5, 0
; RV32-NEXT: and a2, a2, a3 ; RV32-NEXT: and a6, a6, a3
; RV32-NEXT: beq a2, a6, .LBB45_14 ; RV32-NEXT: beq a6, a2, .LBB45_14
; RV32-NEXT: .LBB45_30: # %entry ; RV32-NEXT: .LBB45_30: # %entry
; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv a0, a5
; RV32-NEXT: mv a4, a1 ; RV32-NEXT: mv a5, a1
; RV32-NEXT: bgez a3, .LBB45_15 ; RV32-NEXT: bgez a3, .LBB45_15
; RV32-NEXT: .LBB45_31: # %entry ; RV32-NEXT: .LBB45_31: # %entry
; RV32-NEXT: lui a4, 524288 ; RV32-NEXT: lui a5, 524288
; RV32-NEXT: bltu a7, a1, .LBB45_16 ; RV32-NEXT: bltu a4, a1, .LBB45_16
; RV32-NEXT: .LBB45_32: # %entry ; RV32-NEXT: .LBB45_32: # %entry
; RV32-NEXT: lui a1, 524288 ; RV32-NEXT: lui a1, 524288
; RV32-NEXT: bne a2, a6, .LBB45_17 ; RV32-NEXT: bne a6, a2, .LBB45_17
; RV32-NEXT: j .LBB45_18 ; RV32-NEXT: j .LBB45_18
; ;
; RV64IF-LABEL: stest_f64i64_mm: ; RV64IF-LABEL: stest_f64i64_mm:
; RV64IF: # %bb.0: # %entry ; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: .cfi_def_cfa_offset 16 ; RV64IF-NEXT: .cfi_def_cfa_offset 16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: .cfi_offset ra, -8 ; RV64IF-NEXT: .cfi_offset ra, -8
▲ Show 20 Lines • Show All 305 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: mv a1, a0 ; RV32-NEXT: mv a1, a0
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: call __fixsfti@plt ; RV32-NEXT: call __fixsfti@plt
; RV32-NEXT: lw a5, 8(sp) ; RV32-NEXT: lw a5, 8(sp)
; RV32-NEXT: lw a3, 20(sp) ; RV32-NEXT: lw a3, 20(sp)
; RV32-NEXT: lw a1, 12(sp) ; RV32-NEXT: lw a1, 12(sp)
; RV32-NEXT: li a6, -1 ; RV32-NEXT: li a2, -1
; RV32-NEXT: mv a4, a5 ; RV32-NEXT: mv a7, a5
; RV32-NEXT: bltz a3, .LBB48_2 ; RV32-NEXT: bltz a3, .LBB48_2
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: li a4, -1 ; RV32-NEXT: li a7, -1
; RV32-NEXT: .LBB48_2: # %entry ; RV32-NEXT: .LBB48_2: # %entry
; RV32-NEXT: lui a7, 524288 ; RV32-NEXT: lui a4, 524288
; RV32-NEXT: addi a2, a7, -1 ; RV32-NEXT: addi a6, a4, -1
; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv t0, a5
; RV32-NEXT: bgeu a1, a2, .LBB48_19 ; RV32-NEXT: bgeu a1, a6, .LBB48_19
; RV32-NEXT: # %bb.3: # %entry ; RV32-NEXT: # %bb.3: # %entry
; RV32-NEXT: lw t0, 16(sp) ; RV32-NEXT: lw a0, 16(sp)
; RV32-NEXT: bne a1, a2, .LBB48_20 ; RV32-NEXT: bne a1, a6, .LBB48_20
; RV32-NEXT: .LBB48_4: # %entry ; RV32-NEXT: .LBB48_4: # %entry
; RV32-NEXT: or a0, t0, a3 ; RV32-NEXT: or t0, a0, a3
; RV32-NEXT: bnez a0, .LBB48_21 ; RV32-NEXT: bnez t0, .LBB48_21
; RV32-NEXT: .LBB48_5: # %entry ; RV32-NEXT: .LBB48_5: # %entry
; RV32-NEXT: mv a4, a1 ; RV32-NEXT: mv a7, a1
; RV32-NEXT: bgez a3, .LBB48_22 ; RV32-NEXT: bgez a3, .LBB48_22
; RV32-NEXT: .LBB48_6: # %entry ; RV32-NEXT: .LBB48_6: # %entry
; RV32-NEXT: bgeu a1, a2, .LBB48_23 ; RV32-NEXT: bgeu a1, a6, .LBB48_23
; RV32-NEXT: .LBB48_7: # %entry ; RV32-NEXT: .LBB48_7: # %entry
; RV32-NEXT: bnez a0, .LBB48_24 ; RV32-NEXT: bnez t0, .LBB48_24
; RV32-NEXT: .LBB48_8: # %entry ; RV32-NEXT: .LBB48_8: # %entry
; RV32-NEXT: li a2, 0 ; RV32-NEXT: li a6, 0
; RV32-NEXT: bnez a3, .LBB48_25 ; RV32-NEXT: bnez a3, .LBB48_25
; RV32-NEXT: .LBB48_9: # %entry ; RV32-NEXT: .LBB48_9: # %entry
; RV32-NEXT: bgez a3, .LBB48_26 ; RV32-NEXT: bgez a3, .LBB48_26
; RV32-NEXT: .LBB48_10: # %entry ; RV32-NEXT: .LBB48_10: # %entry
; RV32-NEXT: mv a4, a5 ; RV32-NEXT: mv a7, a5
; RV32-NEXT: bgeu a7, a1, .LBB48_27 ; RV32-NEXT: bgeu a4, a1, .LBB48_27
; RV32-NEXT: .LBB48_11: # %entry ; RV32-NEXT: .LBB48_11: # %entry
; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv a0, a5
; RV32-NEXT: bne a1, a7, .LBB48_28 ; RV32-NEXT: bne a1, a4, .LBB48_28
; RV32-NEXT: .LBB48_12: # %entry ; RV32-NEXT: .LBB48_12: # %entry
; RV32-NEXT: bltz a3, .LBB48_29 ; RV32-NEXT: bltz a3, .LBB48_29
; RV32-NEXT: .LBB48_13: # %entry ; RV32-NEXT: .LBB48_13: # %entry
; RV32-NEXT: and a2, a2, a3 ; RV32-NEXT: and a6, a6, a3
; RV32-NEXT: bne a2, a6, .LBB48_30 ; RV32-NEXT: bne a6, a2, .LBB48_30
; RV32-NEXT: .LBB48_14: # %entry ; RV32-NEXT: .LBB48_14: # %entry
; RV32-NEXT: mv a4, a1 ; RV32-NEXT: mv a5, a1
; RV32-NEXT: bltz a3, .LBB48_31 ; RV32-NEXT: bltz a3, .LBB48_31
; RV32-NEXT: .LBB48_15: # %entry ; RV32-NEXT: .LBB48_15: # %entry
; RV32-NEXT: bgeu a7, a1, .LBB48_32 ; RV32-NEXT: bgeu a4, a1, .LBB48_32
; RV32-NEXT: .LBB48_16: # %entry ; RV32-NEXT: .LBB48_16: # %entry
; RV32-NEXT: beq a2, a6, .LBB48_18 ; RV32-NEXT: beq a6, a2, .LBB48_18
; RV32-NEXT: .LBB48_17: # %entry ; RV32-NEXT: .LBB48_17: # %entry
; RV32-NEXT: mv a1, a4 ; RV32-NEXT: mv a1, a5
; RV32-NEXT: .LBB48_18: # %entry ; RV32-NEXT: .LBB48_18: # %entry
; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 32 ; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: ret ; RV32-NEXT: ret
; RV32-NEXT: .LBB48_19: # %entry ; RV32-NEXT: .LBB48_19: # %entry
; RV32-NEXT: li a0, -1 ; RV32-NEXT: li t0, -1
; RV32-NEXT: lw t0, 16(sp) ; RV32-NEXT: lw a0, 16(sp)
; RV32-NEXT: beq a1, a2, .LBB48_4 ; RV32-NEXT: beq a1, a6, .LBB48_4
; RV32-NEXT: .LBB48_20: # %entry ; RV32-NEXT: .LBB48_20: # %entry
; RV32-NEXT: mv a5, a0 ; RV32-NEXT: mv a5, t0
; RV32-NEXT: or a0, t0, a3 ; RV32-NEXT: or t0, a0, a3
; RV32-NEXT: beqz a0, .LBB48_5 ; RV32-NEXT: beqz t0, .LBB48_5
; RV32-NEXT: .LBB48_21: # %entry ; RV32-NEXT: .LBB48_21: # %entry
; RV32-NEXT: mv a5, a4 ; RV32-NEXT: mv a5, a7
; RV32-NEXT: mv a4, a1 ; RV32-NEXT: mv a7, a1
; RV32-NEXT: bltz a3, .LBB48_6 ; RV32-NEXT: bltz a3, .LBB48_6
; RV32-NEXT: .LBB48_22: # %entry ; RV32-NEXT: .LBB48_22: # %entry
; RV32-NEXT: mv a4, a2 ; RV32-NEXT: mv a7, a6
; RV32-NEXT: bltu a1, a2, .LBB48_7 ; RV32-NEXT: bltu a1, a6, .LBB48_7
; RV32-NEXT: .LBB48_23: # %entry ; RV32-NEXT: .LBB48_23: # %entry
; RV32-NEXT: mv a1, a2 ; RV32-NEXT: mv a1, a6
; RV32-NEXT: beqz a0, .LBB48_8 ; RV32-NEXT: beqz t0, .LBB48_8
; RV32-NEXT: .LBB48_24: # %entry ; RV32-NEXT: .LBB48_24: # %entry
; RV32-NEXT: mv a1, a4 ; RV32-NEXT: mv a1, a7
; RV32-NEXT: li a2, 0 ; RV32-NEXT: li a6, 0
; RV32-NEXT: beqz a3, .LBB48_9 ; RV32-NEXT: beqz a3, .LBB48_9
; RV32-NEXT: .LBB48_25: # %entry ; RV32-NEXT: .LBB48_25: # %entry
; RV32-NEXT: srai a0, a3, 31 ; RV32-NEXT: srai a6, a3, 31
; RV32-NEXT: and a2, a0, t0 ; RV32-NEXT: and a6, a6, a0
; RV32-NEXT: bltz a3, .LBB48_10 ; RV32-NEXT: bltz a3, .LBB48_10
; RV32-NEXT: .LBB48_26: # %entry ; RV32-NEXT: .LBB48_26: # %entry
; RV32-NEXT: li a3, 0 ; RV32-NEXT: li a3, 0
; RV32-NEXT: mv a4, a5 ; RV32-NEXT: mv a7, a5
; RV32-NEXT: bltu a7, a1, .LBB48_11 ; RV32-NEXT: bltu a4, a1, .LBB48_11
; RV32-NEXT: .LBB48_27: # %entry ; RV32-NEXT: .LBB48_27: # %entry
; RV32-NEXT: li a4, 0 ; RV32-NEXT: li a7, 0
; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv a0, a5
; RV32-NEXT: beq a1, a7, .LBB48_12 ; RV32-NEXT: beq a1, a4, .LBB48_12
; RV32-NEXT: .LBB48_28: # %entry ; RV32-NEXT: .LBB48_28: # %entry
; RV32-NEXT: mv a0, a4 ; RV32-NEXT: mv a0, a7
; RV32-NEXT: bgez a3, .LBB48_13 ; RV32-NEXT: bgez a3, .LBB48_13
; RV32-NEXT: .LBB48_29: # %entry ; RV32-NEXT: .LBB48_29: # %entry
; RV32-NEXT: li a5, 0 ; RV32-NEXT: li a5, 0
; RV32-NEXT: and a2, a2, a3 ; RV32-NEXT: and a6, a6, a3
; RV32-NEXT: beq a2, a6, .LBB48_14 ; RV32-NEXT: beq a6, a2, .LBB48_14
; RV32-NEXT: .LBB48_30: # %entry ; RV32-NEXT: .LBB48_30: # %entry
; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv a0, a5
; RV32-NEXT: mv a4, a1 ; RV32-NEXT: mv a5, a1
; RV32-NEXT: bgez a3, .LBB48_15 ; RV32-NEXT: bgez a3, .LBB48_15
; RV32-NEXT: .LBB48_31: # %entry ; RV32-NEXT: .LBB48_31: # %entry
; RV32-NEXT: lui a4, 524288 ; RV32-NEXT: lui a5, 524288
; RV32-NEXT: bltu a7, a1, .LBB48_16 ; RV32-NEXT: bltu a4, a1, .LBB48_16
; RV32-NEXT: .LBB48_32: # %entry ; RV32-NEXT: .LBB48_32: # %entry
; RV32-NEXT: lui a1, 524288 ; RV32-NEXT: lui a1, 524288
; RV32-NEXT: bne a2, a6, .LBB48_17 ; RV32-NEXT: bne a6, a2, .LBB48_17
; RV32-NEXT: j .LBB48_18 ; RV32-NEXT: j .LBB48_18
; ;
; RV64-LABEL: stest_f32i64_mm: ; RV64-LABEL: stest_f32i64_mm:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: fmv.w.x ft0, a0 ; RV64-NEXT: fmv.w.x ft0, a0
; RV64-NEXT: feq.s a0, ft0, ft0 ; RV64-NEXT: feq.s a0, ft0, ft0
; RV64-NEXT: bnez a0, .LBB48_2 ; RV64-NEXT: bnez a0, .LBB48_2
; RV64-NEXT: # %bb.1: # %entry ; RV64-NEXT: # %bb.1: # %entry
▲ Show 20 Lines • Show All 253 Lines • ▼ Show 20 Lines
; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: call __gnu_h2f_ieee@plt ; RV32-NEXT: call __gnu_h2f_ieee@plt
; RV32-NEXT: mv a1, a0 ; RV32-NEXT: mv a1, a0
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: call __fixsfti@plt ; RV32-NEXT: call __fixsfti@plt
; RV32-NEXT: lw a5, 8(sp) ; RV32-NEXT: lw a5, 8(sp)
; RV32-NEXT: lw a3, 20(sp) ; RV32-NEXT: lw a3, 20(sp)
; RV32-NEXT: lw a1, 12(sp) ; RV32-NEXT: lw a1, 12(sp)
; RV32-NEXT: li a6, -1 ; RV32-NEXT: li a2, -1
; RV32-NEXT: mv a4, a5 ; RV32-NEXT: mv a7, a5
; RV32-NEXT: bltz a3, .LBB51_2 ; RV32-NEXT: bltz a3, .LBB51_2
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: li a4, -1 ; RV32-NEXT: li a7, -1
; RV32-NEXT: .LBB51_2: # %entry ; RV32-NEXT: .LBB51_2: # %entry
; RV32-NEXT: lui a7, 524288 ; RV32-NEXT: lui a4, 524288
; RV32-NEXT: addi a2, a7, -1 ; RV32-NEXT: addi a6, a4, -1
; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv t0, a5
; RV32-NEXT: bgeu a1, a2, .LBB51_19 ; RV32-NEXT: bgeu a1, a6, .LBB51_19
; RV32-NEXT: # %bb.3: # %entry ; RV32-NEXT: # %bb.3: # %entry
; RV32-NEXT: lw t0, 16(sp) ; RV32-NEXT: lw a0, 16(sp)
; RV32-NEXT: bne a1, a2, .LBB51_20 ; RV32-NEXT: bne a1, a6, .LBB51_20
; RV32-NEXT: .LBB51_4: # %entry ; RV32-NEXT: .LBB51_4: # %entry
; RV32-NEXT: or a0, t0, a3 ; RV32-NEXT: or t0, a0, a3
; RV32-NEXT: bnez a0, .LBB51_21 ; RV32-NEXT: bnez t0, .LBB51_21
; RV32-NEXT: .LBB51_5: # %entry ; RV32-NEXT: .LBB51_5: # %entry
; RV32-NEXT: mv a4, a1 ; RV32-NEXT: mv a7, a1
; RV32-NEXT: bgez a3, .LBB51_22 ; RV32-NEXT: bgez a3, .LBB51_22
; RV32-NEXT: .LBB51_6: # %entry ; RV32-NEXT: .LBB51_6: # %entry
; RV32-NEXT: bgeu a1, a2, .LBB51_23 ; RV32-NEXT: bgeu a1, a6, .LBB51_23
; RV32-NEXT: .LBB51_7: # %entry ; RV32-NEXT: .LBB51_7: # %entry
; RV32-NEXT: bnez a0, .LBB51_24 ; RV32-NEXT: bnez t0, .LBB51_24
; RV32-NEXT: .LBB51_8: # %entry ; RV32-NEXT: .LBB51_8: # %entry
; RV32-NEXT: li a2, 0 ; RV32-NEXT: li a6, 0
; RV32-NEXT: bnez a3, .LBB51_25 ; RV32-NEXT: bnez a3, .LBB51_25
; RV32-NEXT: .LBB51_9: # %entry ; RV32-NEXT: .LBB51_9: # %entry
; RV32-NEXT: bgez a3, .LBB51_26 ; RV32-NEXT: bgez a3, .LBB51_26
; RV32-NEXT: .LBB51_10: # %entry ; RV32-NEXT: .LBB51_10: # %entry
; RV32-NEXT: mv a4, a5 ; RV32-NEXT: mv a7, a5
; RV32-NEXT: bgeu a7, a1, .LBB51_27 ; RV32-NEXT: bgeu a4, a1, .LBB51_27
; RV32-NEXT: .LBB51_11: # %entry ; RV32-NEXT: .LBB51_11: # %entry
; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv a0, a5
; RV32-NEXT: bne a1, a7, .LBB51_28 ; RV32-NEXT: bne a1, a4, .LBB51_28
; RV32-NEXT: .LBB51_12: # %entry ; RV32-NEXT: .LBB51_12: # %entry
; RV32-NEXT: bltz a3, .LBB51_29 ; RV32-NEXT: bltz a3, .LBB51_29
; RV32-NEXT: .LBB51_13: # %entry ; RV32-NEXT: .LBB51_13: # %entry
; RV32-NEXT: and a2, a2, a3 ; RV32-NEXT: and a6, a6, a3
; RV32-NEXT: bne a2, a6, .LBB51_30 ; RV32-NEXT: bne a6, a2, .LBB51_30
; RV32-NEXT: .LBB51_14: # %entry ; RV32-NEXT: .LBB51_14: # %entry
; RV32-NEXT: mv a4, a1 ; RV32-NEXT: mv a5, a1
; RV32-NEXT: bltz a3, .LBB51_31 ; RV32-NEXT: bltz a3, .LBB51_31
; RV32-NEXT: .LBB51_15: # %entry ; RV32-NEXT: .LBB51_15: # %entry
; RV32-NEXT: bgeu a7, a1, .LBB51_32 ; RV32-NEXT: bgeu a4, a1, .LBB51_32
; RV32-NEXT: .LBB51_16: # %entry ; RV32-NEXT: .LBB51_16: # %entry
; RV32-NEXT: beq a2, a6, .LBB51_18 ; RV32-NEXT: beq a6, a2, .LBB51_18
; RV32-NEXT: .LBB51_17: # %entry ; RV32-NEXT: .LBB51_17: # %entry
; RV32-NEXT: mv a1, a4 ; RV32-NEXT: mv a1, a5
; RV32-NEXT: .LBB51_18: # %entry ; RV32-NEXT: .LBB51_18: # %entry
; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 32 ; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: ret ; RV32-NEXT: ret
; RV32-NEXT: .LBB51_19: # %entry ; RV32-NEXT: .LBB51_19: # %entry
; RV32-NEXT: li a0, -1 ; RV32-NEXT: li t0, -1
; RV32-NEXT: lw t0, 16(sp) ; RV32-NEXT: lw a0, 16(sp)
; RV32-NEXT: beq a1, a2, .LBB51_4 ; RV32-NEXT: beq a1, a6, .LBB51_4
; RV32-NEXT: .LBB51_20: # %entry ; RV32-NEXT: .LBB51_20: # %entry
; RV32-NEXT: mv a5, a0 ; RV32-NEXT: mv a5, t0
; RV32-NEXT: or a0, t0, a3 ; RV32-NEXT: or t0, a0, a3
; RV32-NEXT: beqz a0, .LBB51_5 ; RV32-NEXT: beqz t0, .LBB51_5
; RV32-NEXT: .LBB51_21: # %entry ; RV32-NEXT: .LBB51_21: # %entry
; RV32-NEXT: mv a5, a4 ; RV32-NEXT: mv a5, a7
; RV32-NEXT: mv a4, a1 ; RV32-NEXT: mv a7, a1
; RV32-NEXT: bltz a3, .LBB51_6 ; RV32-NEXT: bltz a3, .LBB51_6
; RV32-NEXT: .LBB51_22: # %entry ; RV32-NEXT: .LBB51_22: # %entry
; RV32-NEXT: mv a4, a2 ; RV32-NEXT: mv a7, a6
; RV32-NEXT: bltu a1, a2, .LBB51_7 ; RV32-NEXT: bltu a1, a6, .LBB51_7
; RV32-NEXT: .LBB51_23: # %entry ; RV32-NEXT: .LBB51_23: # %entry
; RV32-NEXT: mv a1, a2 ; RV32-NEXT: mv a1, a6
; RV32-NEXT: beqz a0, .LBB51_8 ; RV32-NEXT: beqz t0, .LBB51_8
; RV32-NEXT: .LBB51_24: # %entry ; RV32-NEXT: .LBB51_24: # %entry
; RV32-NEXT: mv a1, a4 ; RV32-NEXT: mv a1, a7
; RV32-NEXT: li a2, 0 ; RV32-NEXT: li a6, 0
; RV32-NEXT: beqz a3, .LBB51_9 ; RV32-NEXT: beqz a3, .LBB51_9
; RV32-NEXT: .LBB51_25: # %entry ; RV32-NEXT: .LBB51_25: # %entry
; RV32-NEXT: srai a0, a3, 31 ; RV32-NEXT: srai a6, a3, 31
; RV32-NEXT: and a2, a0, t0 ; RV32-NEXT: and a6, a6, a0
; RV32-NEXT: bltz a3, .LBB51_10 ; RV32-NEXT: bltz a3, .LBB51_10
; RV32-NEXT: .LBB51_26: # %entry ; RV32-NEXT: .LBB51_26: # %entry
; RV32-NEXT: li a3, 0 ; RV32-NEXT: li a3, 0
; RV32-NEXT: mv a4, a5 ; RV32-NEXT: mv a7, a5
; RV32-NEXT: bltu a7, a1, .LBB51_11 ; RV32-NEXT: bltu a4, a1, .LBB51_11
; RV32-NEXT: .LBB51_27: # %entry ; RV32-NEXT: .LBB51_27: # %entry
; RV32-NEXT: li a4, 0 ; RV32-NEXT: li a7, 0
; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv a0, a5
; RV32-NEXT: beq a1, a7, .LBB51_12 ; RV32-NEXT: beq a1, a4, .LBB51_12
; RV32-NEXT: .LBB51_28: # %entry ; RV32-NEXT: .LBB51_28: # %entry
; RV32-NEXT: mv a0, a4 ; RV32-NEXT: mv a0, a7
; RV32-NEXT: bgez a3, .LBB51_13 ; RV32-NEXT: bgez a3, .LBB51_13
; RV32-NEXT: .LBB51_29: # %entry ; RV32-NEXT: .LBB51_29: # %entry
; RV32-NEXT: li a5, 0 ; RV32-NEXT: li a5, 0
; RV32-NEXT: and a2, a2, a3 ; RV32-NEXT: and a6, a6, a3
; RV32-NEXT: beq a2, a6, .LBB51_14 ; RV32-NEXT: beq a6, a2, .LBB51_14
; RV32-NEXT: .LBB51_30: # %entry ; RV32-NEXT: .LBB51_30: # %entry
; RV32-NEXT: mv a0, a5 ; RV32-NEXT: mv a0, a5
; RV32-NEXT: mv a4, a1 ; RV32-NEXT: mv a5, a1
; RV32-NEXT: bgez a3, .LBB51_15 ; RV32-NEXT: bgez a3, .LBB51_15
; RV32-NEXT: .LBB51_31: # %entry ; RV32-NEXT: .LBB51_31: # %entry
; RV32-NEXT: lui a4, 524288 ; RV32-NEXT: lui a5, 524288
; RV32-NEXT: bltu a7, a1, .LBB51_16 ; RV32-NEXT: bltu a4, a1, .LBB51_16
; RV32-NEXT: .LBB51_32: # %entry ; RV32-NEXT: .LBB51_32: # %entry
; RV32-NEXT: lui a1, 524288 ; RV32-NEXT: lui a1, 524288
; RV32-NEXT: bne a2, a6, .LBB51_17 ; RV32-NEXT: bne a6, a2, .LBB51_17
; RV32-NEXT: j .LBB51_18 ; RV32-NEXT: j .LBB51_18
; ;
; RV64-LABEL: stest_f16i64_mm: ; RV64-LABEL: stest_f16i64_mm:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8 ; RV64-NEXT: .cfi_offset ra, -8
▲ Show 20 Lines • Show All 300 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines
define <4 x i32> @stest_f32i32(<4 x float> %x) { define <4 x i32> @stest_f32i32(<4 x float> %x) {
; CHECK-LABEL: stest_f32i32: ; CHECK-LABEL: stest_f32i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft1, a4 ; CHECK-NEXT: fmv.w.x ft1, a4
; CHECK-NEXT: fmv.w.x ft2, a3 ; CHECK-NEXT: fmv.w.x ft2, a3
; CHECK-NEXT: fmv.w.x ft0, a2 ; CHECK-NEXT: fmv.w.x ft0, a2
; CHECK-NEXT: fcvt.l.s a2, ft1, rtz ; CHECK-NEXT: fcvt.l.s a2, ft1, rtz
; CHECK-NEXT: lui a6, 524288 ; CHECK-NEXT: lui a4, 524288
; CHECK-NEXT: addiw a5, a6, -1 ; CHECK-NEXT: addiw a6, a4, -1
; CHECK-NEXT: fcvt.l.s a3, ft2, rtz ; CHECK-NEXT: fcvt.l.s a3, ft2, rtz
; CHECK-NEXT: blt a2, a5, .LBB3_2 ; CHECK-NEXT: blt a2, a6, .LBB3_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a2, a5 ; CHECK-NEXT: mv a2, a6
; CHECK-NEXT: .LBB3_2: # %entry ; CHECK-NEXT: .LBB3_2: # %entry
; CHECK-NEXT: fmv.w.x ft1, a1 ; CHECK-NEXT: fmv.w.x ft1, a1
; CHECK-NEXT: fcvt.l.s a1, ft0, rtz ; CHECK-NEXT: fcvt.l.s a1, ft0, rtz
; CHECK-NEXT: bge a3, a5, .LBB3_11 ; CHECK-NEXT: bge a3, a6, .LBB3_11
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: fcvt.l.s a4, ft1, rtz ; CHECK-NEXT: fcvt.l.s a5, ft1, rtz
; CHECK-NEXT: bge a1, a5, .LBB3_12 ; CHECK-NEXT: bge a1, a6, .LBB3_12
; CHECK-NEXT: .LBB3_4: # %entry ; CHECK-NEXT: .LBB3_4: # %entry
; CHECK-NEXT: bge a4, a5, .LBB3_13 ; CHECK-NEXT: bge a5, a6, .LBB3_13
; CHECK-NEXT: .LBB3_5: # %entry ; CHECK-NEXT: .LBB3_5: # %entry
; CHECK-NEXT: bge a6, a4, .LBB3_14 ; CHECK-NEXT: bge a4, a5, .LBB3_14
; CHECK-NEXT: .LBB3_6: # %entry ; CHECK-NEXT: .LBB3_6: # %entry
; CHECK-NEXT: bge a6, a1, .LBB3_15 ; CHECK-NEXT: bge a4, a1, .LBB3_15
; CHECK-NEXT: .LBB3_7: # %entry ; CHECK-NEXT: .LBB3_7: # %entry
; CHECK-NEXT: bge a6, a3, .LBB3_16 ; CHECK-NEXT: bge a4, a3, .LBB3_16
; CHECK-NEXT: .LBB3_8: # %entry ; CHECK-NEXT: .LBB3_8: # %entry
; CHECK-NEXT: blt a6, a2, .LBB3_10 ; CHECK-NEXT: blt a4, a2, .LBB3_10
; CHECK-NEXT: .LBB3_9: # %entry ; CHECK-NEXT: .LBB3_9: # %entry
; CHECK-NEXT: lui a2, 524288 ; CHECK-NEXT: lui a2, 524288
; CHECK-NEXT: .LBB3_10: # %entry ; CHECK-NEXT: .LBB3_10: # %entry
; CHECK-NEXT: sw a2, 12(a0) ; CHECK-NEXT: sw a2, 12(a0)
; CHECK-NEXT: sw a3, 8(a0) ; CHECK-NEXT: sw a3, 8(a0)
; CHECK-NEXT: sw a1, 4(a0) ; CHECK-NEXT: sw a1, 4(a0)
; CHECK-NEXT: sw a4, 0(a0) ; CHECK-NEXT: sw a5, 0(a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB3_11: # %entry ; CHECK-NEXT: .LBB3_11: # %entry
; CHECK-NEXT: mv a3, a5 ; CHECK-NEXT: mv a3, a6
; CHECK-NEXT: fcvt.l.s a4, ft1, rtz ; CHECK-NEXT: fcvt.l.s a5, ft1, rtz
; CHECK-NEXT: blt a1, a5, .LBB3_4 ; CHECK-NEXT: blt a1, a6, .LBB3_4
; CHECK-NEXT: .LBB3_12: # %entry ; CHECK-NEXT: .LBB3_12: # %entry
; CHECK-NEXT: mv a1, a5 ; CHECK-NEXT: mv a1, a6
; CHECK-NEXT: blt a4, a5, .LBB3_5 ; CHECK-NEXT: blt a5, a6, .LBB3_5
; CHECK-NEXT: .LBB3_13: # %entry ; CHECK-NEXT: .LBB3_13: # %entry
; CHECK-NEXT: mv a4, a5 ; CHECK-NEXT: mv a5, a6
; CHECK-NEXT: blt a6, a4, .LBB3_6 ; CHECK-NEXT: blt a4, a5, .LBB3_6
; CHECK-NEXT: .LBB3_14: # %entry ; CHECK-NEXT: .LBB3_14: # %entry
; CHECK-NEXT: lui a4, 524288 ; CHECK-NEXT: lui a5, 524288
; CHECK-NEXT: blt a6, a1, .LBB3_7 ; CHECK-NEXT: blt a4, a1, .LBB3_7
; CHECK-NEXT: .LBB3_15: # %entry ; CHECK-NEXT: .LBB3_15: # %entry
; CHECK-NEXT: lui a1, 524288 ; CHECK-NEXT: lui a1, 524288
; CHECK-NEXT: blt a6, a3, .LBB3_8 ; CHECK-NEXT: blt a4, a3, .LBB3_8
; CHECK-NEXT: .LBB3_16: # %entry ; CHECK-NEXT: .LBB3_16: # %entry
; CHECK-NEXT: lui a3, 524288 ; CHECK-NEXT: lui a3, 524288
; CHECK-NEXT: bge a6, a2, .LBB3_9 ; CHECK-NEXT: bge a4, a2, .LBB3_9
; CHECK-NEXT: j .LBB3_10 ; CHECK-NEXT: j .LBB3_10
entry: entry:
%conv = fptosi <4 x float> %x to <4 x i64> %conv = fptosi <4 x float> %x to <4 x i64>
%0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647> %0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
%spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647> %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
%1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648> %1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
%spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648> %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
%conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32> %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
; CHECK-NEXT: sd s4, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: .cfi_offset s3, -40 ; CHECK-NEXT: .cfi_offset s3, -40
; CHECK-NEXT: .cfi_offset s4, -48 ; CHECK-NEXT: .cfi_offset s4, -48
; CHECK-NEXT: lhu s2, 24(a1) ; CHECK-NEXT: lhu s2, 24(a1)
; CHECK-NEXT: lhu s4, 0(a1) ; CHECK-NEXT: lhu s1, 0(a1)
; CHECK-NEXT: lhu s0, 8(a1) ; CHECK-NEXT: lhu s3, 8(a1)
; CHECK-NEXT: lhu a1, 16(a1) ; CHECK-NEXT: lhu a1, 16(a1)
; CHECK-NEXT: mv s3, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: mv s4, a0
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s3
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s3, a0
; CHECK-NEXT: mv a0, s4 ; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s4, a0 ; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: fmv.w.x ft0, s0 ; CHECK-NEXT: fmv.w.x ft0, s3
; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill ; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: fmv.w.x ft0, s1 ; CHECK-NEXT: fmv.w.x ft0, s4
; CHECK-NEXT: fcvt.l.s s0, ft0, rtz ; CHECK-NEXT: fcvt.l.s s3, ft0, rtz
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: fcvt.l.s a0, ft0, rtz ; CHECK-NEXT: fcvt.l.s a0, ft0, rtz
; CHECK-NEXT: lui a1, 524288 ; CHECK-NEXT: lui a1, 524288
; CHECK-NEXT: addiw a4, a1, -1 ; CHECK-NEXT: addiw a4, a1, -1
; CHECK-NEXT: blt a0, a4, .LBB6_2 ; CHECK-NEXT: blt a0, a4, .LBB6_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a0, a4 ; CHECK-NEXT: mv a0, a4
; CHECK-NEXT: .LBB6_2: # %entry ; CHECK-NEXT: .LBB6_2: # %entry
; CHECK-NEXT: fmv.w.x ft0, s4 ; CHECK-NEXT: fmv.w.x ft0, s1
; CHECK-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload ; CHECK-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: fcvt.l.s a2, ft1, rtz ; CHECK-NEXT: fcvt.l.s a2, ft1, rtz
; CHECK-NEXT: bge s0, a4, .LBB6_11 ; CHECK-NEXT: bge s3, a4, .LBB6_11
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: fcvt.l.s a3, ft0, rtz ; CHECK-NEXT: fcvt.l.s a3, ft0, rtz
; CHECK-NEXT: bge a2, a4, .LBB6_12 ; CHECK-NEXT: bge a2, a4, .LBB6_12
; CHECK-NEXT: .LBB6_4: # %entry ; CHECK-NEXT: .LBB6_4: # %entry
; CHECK-NEXT: bge a3, a4, .LBB6_13 ; CHECK-NEXT: bge a3, a4, .LBB6_13
; CHECK-NEXT: .LBB6_5: # %entry ; CHECK-NEXT: .LBB6_5: # %entry
; CHECK-NEXT: bge a1, a3, .LBB6_14 ; CHECK-NEXT: bge a1, a3, .LBB6_14
; CHECK-NEXT: .LBB6_6: # %entry ; CHECK-NEXT: .LBB6_6: # %entry
; CHECK-NEXT: bge a1, a2, .LBB6_15 ; CHECK-NEXT: bge a1, a2, .LBB6_15
; CHECK-NEXT: .LBB6_7: # %entry ; CHECK-NEXT: .LBB6_7: # %entry
; CHECK-NEXT: bge a1, s0, .LBB6_16 ; CHECK-NEXT: bge a1, s3, .LBB6_16
; CHECK-NEXT: .LBB6_8: # %entry ; CHECK-NEXT: .LBB6_8: # %entry
; CHECK-NEXT: blt a1, a0, .LBB6_10 ; CHECK-NEXT: blt a1, a0, .LBB6_10
; CHECK-NEXT: .LBB6_9: # %entry ; CHECK-NEXT: .LBB6_9: # %entry
; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: .LBB6_10: # %entry ; CHECK-NEXT: .LBB6_10: # %entry
; CHECK-NEXT: sw a0, 12(s3) ; CHECK-NEXT: sw a0, 12(s0)
; CHECK-NEXT: sw s0, 8(s3) ; CHECK-NEXT: sw s3, 8(s0)
; CHECK-NEXT: sw a2, 4(s3) ; CHECK-NEXT: sw a2, 4(s0)
; CHECK-NEXT: sw a3, 0(s3) ; CHECK-NEXT: sw a3, 0(s0)
; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 32(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s3, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s4, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 64 ; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB6_11: # %entry ; CHECK-NEXT: .LBB6_11: # %entry
; CHECK-NEXT: mv s0, a4 ; CHECK-NEXT: mv s3, a4
; CHECK-NEXT: fcvt.l.s a3, ft0, rtz ; CHECK-NEXT: fcvt.l.s a3, ft0, rtz
; CHECK-NEXT: blt a2, a4, .LBB6_4 ; CHECK-NEXT: blt a2, a4, .LBB6_4
; CHECK-NEXT: .LBB6_12: # %entry ; CHECK-NEXT: .LBB6_12: # %entry
; CHECK-NEXT: mv a2, a4 ; CHECK-NEXT: mv a2, a4
; CHECK-NEXT: blt a3, a4, .LBB6_5 ; CHECK-NEXT: blt a3, a4, .LBB6_5
; CHECK-NEXT: .LBB6_13: # %entry ; CHECK-NEXT: .LBB6_13: # %entry
; CHECK-NEXT: mv a3, a4 ; CHECK-NEXT: mv a3, a4
; CHECK-NEXT: blt a1, a3, .LBB6_6 ; CHECK-NEXT: blt a1, a3, .LBB6_6
; CHECK-NEXT: .LBB6_14: # %entry ; CHECK-NEXT: .LBB6_14: # %entry
; CHECK-NEXT: lui a3, 524288 ; CHECK-NEXT: lui a3, 524288
; CHECK-NEXT: blt a1, a2, .LBB6_7 ; CHECK-NEXT: blt a1, a2, .LBB6_7
; CHECK-NEXT: .LBB6_15: # %entry ; CHECK-NEXT: .LBB6_15: # %entry
; CHECK-NEXT: lui a2, 524288 ; CHECK-NEXT: lui a2, 524288
; CHECK-NEXT: blt a1, s0, .LBB6_8 ; CHECK-NEXT: blt a1, s3, .LBB6_8
; CHECK-NEXT: .LBB6_16: # %entry ; CHECK-NEXT: .LBB6_16: # %entry
; CHECK-NEXT: lui s0, 524288 ; CHECK-NEXT: lui s3, 524288
; CHECK-NEXT: bge a1, a0, .LBB6_9 ; CHECK-NEXT: bge a1, a0, .LBB6_9
; CHECK-NEXT: j .LBB6_10 ; CHECK-NEXT: j .LBB6_10
entry: entry:
%conv = fptosi <4 x half> %x to <4 x i64> %conv = fptosi <4 x half> %x to <4 x i64>
%0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647> %0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
%spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647> %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
%1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648> %1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
%spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648> %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
Show All 14 Lines
; CHECK-NEXT: sd s4, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: .cfi_offset s3, -40 ; CHECK-NEXT: .cfi_offset s3, -40
; CHECK-NEXT: .cfi_offset s4, -48 ; CHECK-NEXT: .cfi_offset s4, -48
; CHECK-NEXT: lhu s2, 0(a1) ; CHECK-NEXT: lhu s2, 0(a1)
; CHECK-NEXT: lhu s3, 24(a1) ; CHECK-NEXT: lhu s1, 24(a1)
; CHECK-NEXT: lhu s1, 16(a1) ; CHECK-NEXT: lhu s3, 16(a1)
; CHECK-NEXT: lhu a1, 8(a1) ; CHECK-NEXT: lhu a1, 8(a1)
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s4, a0 ; CHECK-NEXT: mv s4, a0
; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: mv a0, s3 ; CHECK-NEXT: mv a0, s3
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s3, a0 ; CHECK-NEXT: mv s3, a0
; CHECK-NEXT: fmv.w.x ft0, s1 ; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: fmv.w.x ft0, s3
; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill ; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: fmv.w.x ft0, s4 ; CHECK-NEXT: fmv.w.x ft0, s4
; CHECK-NEXT: fcvt.lu.s s1, ft0, rtz ; CHECK-NEXT: fcvt.lu.s s3, ft0, rtz
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: fcvt.lu.s a0, ft0, rtz ; CHECK-NEXT: fcvt.lu.s a0, ft0, rtz
; CHECK-NEXT: li a1, -1 ; CHECK-NEXT: li a1, -1
; CHECK-NEXT: srli a1, a1, 32 ; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: bltu a0, a1, .LBB7_2 ; CHECK-NEXT: bltu a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB7_2: # %entry ; CHECK-NEXT: .LBB7_2: # %entry
; CHECK-NEXT: fmv.w.x ft0, s3 ; CHECK-NEXT: fmv.w.x ft0, s1
; CHECK-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload ; CHECK-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: fcvt.lu.s a2, ft1, rtz ; CHECK-NEXT: fcvt.lu.s a2, ft1, rtz
; CHECK-NEXT: bgeu s1, a1, .LBB7_7 ; CHECK-NEXT: bgeu s3, a1, .LBB7_7
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: fcvt.lu.s a3, ft0, rtz ; CHECK-NEXT: fcvt.lu.s a3, ft0, rtz
; CHECK-NEXT: bgeu a2, a1, .LBB7_8 ; CHECK-NEXT: bgeu a2, a1, .LBB7_8
; CHECK-NEXT: .LBB7_4: # %entry ; CHECK-NEXT: .LBB7_4: # %entry
; CHECK-NEXT: bltu a3, a1, .LBB7_6 ; CHECK-NEXT: bltu a3, a1, .LBB7_6
; CHECK-NEXT: .LBB7_5: # %entry ; CHECK-NEXT: .LBB7_5: # %entry
; CHECK-NEXT: mv a3, a1 ; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: .LBB7_6: # %entry ; CHECK-NEXT: .LBB7_6: # %entry
; CHECK-NEXT: sw a3, 12(s0) ; CHECK-NEXT: sw a3, 12(s0)
; CHECK-NEXT: sw a2, 8(s0) ; CHECK-NEXT: sw a2, 8(s0)
; CHECK-NEXT: sw s1, 4(s0) ; CHECK-NEXT: sw s3, 4(s0)
; CHECK-NEXT: sw a0, 0(s0) ; CHECK-NEXT: sw a0, 0(s0)
; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 32(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s3, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s4, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 64 ; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB7_7: # %entry ; CHECK-NEXT: .LBB7_7: # %entry
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv s3, a1
; CHECK-NEXT: fcvt.lu.s a3, ft0, rtz ; CHECK-NEXT: fcvt.lu.s a3, ft0, rtz
; CHECK-NEXT: bltu a2, a1, .LBB7_4 ; CHECK-NEXT: bltu a2, a1, .LBB7_4
; CHECK-NEXT: .LBB7_8: # %entry ; CHECK-NEXT: .LBB7_8: # %entry
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bgeu a3, a1, .LBB7_5 ; CHECK-NEXT: bgeu a3, a1, .LBB7_5
; CHECK-NEXT: j .LBB7_6 ; CHECK-NEXT: j .LBB7_6
entry: entry:
%conv = fptoui <4 x half> %x to <4 x i64> %conv = fptoui <4 x half> %x to <4 x i64>
Show All 16 Lines
; CHECK-NEXT: sd s4, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: .cfi_offset s3, -40 ; CHECK-NEXT: .cfi_offset s3, -40
; CHECK-NEXT: .cfi_offset s4, -48 ; CHECK-NEXT: .cfi_offset s4, -48
; CHECK-NEXT: lhu s2, 24(a1) ; CHECK-NEXT: lhu s2, 24(a1)
; CHECK-NEXT: lhu s4, 0(a1) ; CHECK-NEXT: lhu s1, 0(a1)
; CHECK-NEXT: lhu s0, 8(a1) ; CHECK-NEXT: lhu s3, 8(a1)
; CHECK-NEXT: lhu a1, 16(a1) ; CHECK-NEXT: lhu a1, 16(a1)
; CHECK-NEXT: mv s3, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: mv s4, a0
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s3
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s3, a0
; CHECK-NEXT: mv a0, s4 ; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s4, a0 ; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: fmv.w.x ft0, s0 ; CHECK-NEXT: fmv.w.x ft0, s3
; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill ; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: fmv.w.x ft0, s1 ; CHECK-NEXT: fmv.w.x ft0, s4
; CHECK-NEXT: fcvt.l.s s0, ft0, rtz ; CHECK-NEXT: fcvt.l.s s3, ft0, rtz
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: fcvt.l.s a0, ft0, rtz ; CHECK-NEXT: fcvt.l.s a0, ft0, rtz
; CHECK-NEXT: li a1, -1 ; CHECK-NEXT: li a1, -1
; CHECK-NEXT: srli a3, a1, 32 ; CHECK-NEXT: srli a3, a1, 32
; CHECK-NEXT: blt a0, a3, .LBB8_2 ; CHECK-NEXT: blt a0, a3, .LBB8_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a0, a3 ; CHECK-NEXT: mv a0, a3
; CHECK-NEXT: .LBB8_2: # %entry ; CHECK-NEXT: .LBB8_2: # %entry
; CHECK-NEXT: fmv.w.x ft0, s4 ; CHECK-NEXT: fmv.w.x ft0, s1
; CHECK-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload ; CHECK-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: fcvt.l.s a1, ft1, rtz ; CHECK-NEXT: fcvt.l.s a1, ft1, rtz
; CHECK-NEXT: bge s0, a3, .LBB8_11 ; CHECK-NEXT: bge s3, a3, .LBB8_11
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: fcvt.l.s a2, ft0, rtz ; CHECK-NEXT: fcvt.l.s a2, ft0, rtz
; CHECK-NEXT: bge a1, a3, .LBB8_12 ; CHECK-NEXT: bge a1, a3, .LBB8_12
; CHECK-NEXT: .LBB8_4: # %entry ; CHECK-NEXT: .LBB8_4: # %entry
; CHECK-NEXT: bge a2, a3, .LBB8_13 ; CHECK-NEXT: bge a2, a3, .LBB8_13
; CHECK-NEXT: .LBB8_5: # %entry ; CHECK-NEXT: .LBB8_5: # %entry
; CHECK-NEXT: blez a2, .LBB8_14 ; CHECK-NEXT: blez a2, .LBB8_14
; CHECK-NEXT: .LBB8_6: # %entry ; CHECK-NEXT: .LBB8_6: # %entry
; CHECK-NEXT: blez a1, .LBB8_15 ; CHECK-NEXT: blez a1, .LBB8_15
; CHECK-NEXT: .LBB8_7: # %entry ; CHECK-NEXT: .LBB8_7: # %entry
; CHECK-NEXT: blez s0, .LBB8_16 ; CHECK-NEXT: blez s3, .LBB8_16
; CHECK-NEXT: .LBB8_8: # %entry ; CHECK-NEXT: .LBB8_8: # %entry
; CHECK-NEXT: bgtz a0, .LBB8_10 ; CHECK-NEXT: bgtz a0, .LBB8_10
; CHECK-NEXT: .LBB8_9: # %entry ; CHECK-NEXT: .LBB8_9: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: .LBB8_10: # %entry ; CHECK-NEXT: .LBB8_10: # %entry
; CHECK-NEXT: sw a0, 12(s3) ; CHECK-NEXT: sw a0, 12(s0)
; CHECK-NEXT: sw s0, 8(s3) ; CHECK-NEXT: sw s3, 8(s0)
; CHECK-NEXT: sw a1, 4(s3) ; CHECK-NEXT: sw a1, 4(s0)
; CHECK-NEXT: sw a2, 0(s3) ; CHECK-NEXT: sw a2, 0(s0)
; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 32(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s3, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s4, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 64 ; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB8_11: # %entry ; CHECK-NEXT: .LBB8_11: # %entry
; CHECK-NEXT: mv s0, a3 ; CHECK-NEXT: mv s3, a3
; CHECK-NEXT: fcvt.l.s a2, ft0, rtz ; CHECK-NEXT: fcvt.l.s a2, ft0, rtz
; CHECK-NEXT: blt a1, a3, .LBB8_4 ; CHECK-NEXT: blt a1, a3, .LBB8_4
; CHECK-NEXT: .LBB8_12: # %entry ; CHECK-NEXT: .LBB8_12: # %entry
; CHECK-NEXT: mv a1, a3 ; CHECK-NEXT: mv a1, a3
; CHECK-NEXT: blt a2, a3, .LBB8_5 ; CHECK-NEXT: blt a2, a3, .LBB8_5
; CHECK-NEXT: .LBB8_13: # %entry ; CHECK-NEXT: .LBB8_13: # %entry
; CHECK-NEXT: mv a2, a3 ; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: bgtz a2, .LBB8_6 ; CHECK-NEXT: bgtz a2, .LBB8_6
; CHECK-NEXT: .LBB8_14: # %entry ; CHECK-NEXT: .LBB8_14: # %entry
; CHECK-NEXT: li a2, 0 ; CHECK-NEXT: li a2, 0
; CHECK-NEXT: bgtz a1, .LBB8_7 ; CHECK-NEXT: bgtz a1, .LBB8_7
; CHECK-NEXT: .LBB8_15: # %entry ; CHECK-NEXT: .LBB8_15: # %entry
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: bgtz s0, .LBB8_8 ; CHECK-NEXT: bgtz s3, .LBB8_8
; CHECK-NEXT: .LBB8_16: # %entry ; CHECK-NEXT: .LBB8_16: # %entry
; CHECK-NEXT: li s0, 0 ; CHECK-NEXT: li s3, 0
; CHECK-NEXT: blez a0, .LBB8_9 ; CHECK-NEXT: blez a0, .LBB8_9
; CHECK-NEXT: j .LBB8_10 ; CHECK-NEXT: j .LBB8_10
entry: entry:
%conv = fptosi <4 x half> %x to <4 x i64> %conv = fptosi <4 x half> %x to <4 x i64>
%0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> %0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
%spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
%1 = icmp sgt <4 x i64> %spec.store.select, zeroinitializer %1 = icmp sgt <4 x i64> %spec.store.select, zeroinitializer
%spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> zeroinitializer %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> zeroinitializer
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; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 64(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 64(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s3, 56(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s3, 56(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s4, 48(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s4, 48(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s5, 40(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s5, 40(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s6, 32(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s6, 32(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s7, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s7, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s8, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s8, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s9, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: .cfi_offset s3, -40 ; CHECK-NEXT: .cfi_offset s3, -40
; CHECK-NEXT: .cfi_offset s4, -48 ; CHECK-NEXT: .cfi_offset s4, -48
; CHECK-NEXT: .cfi_offset s5, -56 ; CHECK-NEXT: .cfi_offset s5, -56
; CHECK-NEXT: .cfi_offset s6, -64 ; CHECK-NEXT: .cfi_offset s6, -64
; CHECK-NEXT: .cfi_offset s7, -72 ; CHECK-NEXT: .cfi_offset s7, -72
; CHECK-NEXT: .cfi_offset s8, -80 ; CHECK-NEXT: .cfi_offset s8, -80
; CHECK-NEXT: .cfi_offset s9, -88
; CHECK-NEXT: lhu s6, 56(a1) ; CHECK-NEXT: lhu s6, 56(a1)
; CHECK-NEXT: lhu s2, 0(a1) ; CHECK-NEXT: lhu s1, 0(a1)
; CHECK-NEXT: lhu s3, 8(a1) ; CHECK-NEXT: lhu s2, 8(a1)
; CHECK-NEXT: lhu s4, 16(a1) ; CHECK-NEXT: lhu s3, 16(a1)
; CHECK-NEXT: lhu s5, 24(a1) ; CHECK-NEXT: lhu s4, 24(a1)
; CHECK-NEXT: lhu s1, 32(a1) ; CHECK-NEXT: lhu s5, 32(a1)
; CHECK-NEXT: lhu s0, 40(a1) ; CHECK-NEXT: lhu s7, 40(a1)
; CHECK-NEXT: lhu a1, 48(a1) ; CHECK-NEXT: lhu a1, 48(a1)
; CHECK-NEXT: mv s8, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s9, a0 ; CHECK-NEXT: mv s8, a0
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s7
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s7, a0 ; CHECK-NEXT: mv s7, a0
; CHECK-NEXT: mv a0, s5 ; CHECK-NEXT: mv a0, s5
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s5, a0 ; CHECK-NEXT: mv s5, a0
; CHECK-NEXT: mv a0, s4 ; CHECK-NEXT: mv a0, s4
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s4, a0 ; CHECK-NEXT: mv s4, a0
; CHECK-NEXT: mv a0, s3 ; CHECK-NEXT: mv a0, s3
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s3, a0 ; CHECK-NEXT: mv s3, a0
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: fmv.w.x ft0, s0 ; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, s9 ; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: fcvt.l.s s9, ft0, rtz ; CHECK-NEXT: fmv.w.x ft0, s7
; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: fmv.w.x ft0, s8
; CHECK-NEXT: fcvt.l.s s7, ft0, rtz
; CHECK-NEXT: mv a0, s6 ; CHECK-NEXT: mv a0, s6
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: fcvt.l.s a0, ft0, rtz ; CHECK-NEXT: fcvt.l.s a0, ft0, rtz
; CHECK-NEXT: lui a1, 8 ; CHECK-NEXT: lui a1, 8
; CHECK-NEXT: addiw s1, a1, -1 ; CHECK-NEXT: addiw a7, a1, -1
; CHECK-NEXT: blt a0, s1, .LBB15_2 ; CHECK-NEXT: blt a0, a7, .LBB15_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a0, s1 ; CHECK-NEXT: mv a0, a7
; CHECK-NEXT: .LBB15_2: # %entry ; CHECK-NEXT: .LBB15_2: # %entry
; CHECK-NEXT: fmv.w.x ft1, s7 ; CHECK-NEXT: fmv.w.x ft1, s5
; CHECK-NEXT: flw ft0, 4(sp) # 4-byte Folded Reload ; CHECK-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: fcvt.l.s a1, ft0, rtz ; CHECK-NEXT: fcvt.l.s a1, ft0, rtz
; CHECK-NEXT: blt s9, s1, .LBB15_4 ; CHECK-NEXT: blt s7, a7, .LBB15_4
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: mv s9, s1 ; CHECK-NEXT: mv s7, a7
; CHECK-NEXT: .LBB15_4: # %entry ; CHECK-NEXT: .LBB15_4: # %entry
; CHECK-NEXT: fmv.w.x ft0, s5 ; CHECK-NEXT: fmv.w.x ft0, s4
; CHECK-NEXT: fcvt.l.s a2, ft1, rtz ; CHECK-NEXT: fcvt.l.s a2, ft1, rtz
; CHECK-NEXT: blt a1, s1, .LBB15_6 ; CHECK-NEXT: blt a1, a7, .LBB15_6
; CHECK-NEXT: # %bb.5: # %entry ; CHECK-NEXT: # %bb.5: # %entry
; CHECK-NEXT: mv a1, s1 ; CHECK-NEXT: mv a1, a7
; CHECK-NEXT: .LBB15_6: # %entry ; CHECK-NEXT: .LBB15_6: # %entry
; CHECK-NEXT: fmv.w.x ft1, s4 ; CHECK-NEXT: fmv.w.x ft1, s3
; CHECK-NEXT: fcvt.l.s a3, ft0, rtz ; CHECK-NEXT: fcvt.l.s a3, ft0, rtz
; CHECK-NEXT: blt a2, s1, .LBB15_8 ; CHECK-NEXT: blt a2, a7, .LBB15_8
; CHECK-NEXT: # %bb.7: # %entry ; CHECK-NEXT: # %bb.7: # %entry
; CHECK-NEXT: mv a2, s1 ; CHECK-NEXT: mv a2, a7
; CHECK-NEXT: .LBB15_8: # %entry ; CHECK-NEXT: .LBB15_8: # %entry
; CHECK-NEXT: fmv.w.x ft0, s3 ; CHECK-NEXT: fmv.w.x ft0, s2
; CHECK-NEXT: fcvt.l.s a4, ft1, rtz ; CHECK-NEXT: fcvt.l.s a4, ft1, rtz
; CHECK-NEXT: blt a3, s1, .LBB15_10 ; CHECK-NEXT: blt a3, a7, .LBB15_10
; CHECK-NEXT: # %bb.9: # %entry ; CHECK-NEXT: # %bb.9: # %entry
; CHECK-NEXT: mv a3, s1 ; CHECK-NEXT: mv a3, a7
; CHECK-NEXT: .LBB15_10: # %entry ; CHECK-NEXT: .LBB15_10: # %entry
; CHECK-NEXT: fmv.w.x ft1, s2 ; CHECK-NEXT: fmv.w.x ft1, s1
; CHECK-NEXT: fcvt.l.s a5, ft0, rtz ; CHECK-NEXT: fcvt.l.s a5, ft0, rtz
; CHECK-NEXT: bge a4, s1, .LBB15_23 ; CHECK-NEXT: bge a4, a7, .LBB15_23
; CHECK-NEXT: # %bb.11: # %entry ; CHECK-NEXT: # %bb.11: # %entry
; CHECK-NEXT: fcvt.l.s s0, ft1, rtz ; CHECK-NEXT: fcvt.l.s a6, ft1, rtz
; CHECK-NEXT: bge a5, s1, .LBB15_24 ; CHECK-NEXT: bge a5, a7, .LBB15_24
; CHECK-NEXT: .LBB15_12: # %entry ; CHECK-NEXT: .LBB15_12: # %entry
; CHECK-NEXT: bge s0, s1, .LBB15_25 ; CHECK-NEXT: bge a6, a7, .LBB15_25
; CHECK-NEXT: .LBB15_13: # %entry ; CHECK-NEXT: .LBB15_13: # %entry
; CHECK-NEXT: lui s1, 1048568 ; CHECK-NEXT: lui a7, 1048568
; CHECK-NEXT: bge s1, s0, .LBB15_26 ; CHECK-NEXT: bge a7, a6, .LBB15_26
; CHECK-NEXT: .LBB15_14: # %entry ; CHECK-NEXT: .LBB15_14: # %entry
; CHECK-NEXT: bge s1, a5, .LBB15_27 ; CHECK-NEXT: bge a7, a5, .LBB15_27
; CHECK-NEXT: .LBB15_15: # %entry ; CHECK-NEXT: .LBB15_15: # %entry
; CHECK-NEXT: bge s1, a4, .LBB15_28 ; CHECK-NEXT: bge a7, a4, .LBB15_28
; CHECK-NEXT: .LBB15_16: # %entry ; CHECK-NEXT: .LBB15_16: # %entry
; CHECK-NEXT: bge s1, a3, .LBB15_29 ; CHECK-NEXT: bge a7, a3, .LBB15_29
; CHECK-NEXT: .LBB15_17: # %entry ; CHECK-NEXT: .LBB15_17: # %entry
; CHECK-NEXT: bge s1, a2, .LBB15_30 ; CHECK-NEXT: bge a7, a2, .LBB15_30
; CHECK-NEXT: .LBB15_18: # %entry ; CHECK-NEXT: .LBB15_18: # %entry
; CHECK-NEXT: bge s1, a1, .LBB15_31 ; CHECK-NEXT: bge a7, a1, .LBB15_31
; CHECK-NEXT: .LBB15_19: # %entry ; CHECK-NEXT: .LBB15_19: # %entry
; CHECK-NEXT: bge s1, s9, .LBB15_32 ; CHECK-NEXT: bge a7, s7, .LBB15_32
; CHECK-NEXT: .LBB15_20: # %entry ; CHECK-NEXT: .LBB15_20: # %entry
; CHECK-NEXT: blt s1, a0, .LBB15_22 ; CHECK-NEXT: blt a7, a0, .LBB15_22
; CHECK-NEXT: .LBB15_21: # %entry ; CHECK-NEXT: .LBB15_21: # %entry
; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: .LBB15_22: # %entry ; CHECK-NEXT: .LBB15_22: # %entry
; CHECK-NEXT: sh a0, 14(s8) ; CHECK-NEXT: sh a0, 14(s0)
; CHECK-NEXT: sh s9, 12(s8) ; CHECK-NEXT: sh s7, 12(s0)
; CHECK-NEXT: sh a1, 10(s8) ; CHECK-NEXT: sh a1, 10(s0)
; CHECK-NEXT: sh a2, 8(s8) ; CHECK-NEXT: sh a2, 8(s0)
; CHECK-NEXT: sh a3, 6(s8) ; CHECK-NEXT: sh a3, 6(s0)
; CHECK-NEXT: sh a4, 4(s8) ; CHECK-NEXT: sh a4, 4(s0)
; CHECK-NEXT: sh a5, 2(s8) ; CHECK-NEXT: sh a5, 2(s0)
; CHECK-NEXT: sh s0, 0(s8) ; CHECK-NEXT: sh a6, 0(s0)
; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 80(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 72(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 72(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 64(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 64(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s3, 56(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s3, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s4, 48(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s4, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s5, 40(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s5, 40(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s6, 32(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s6, 32(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s7, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s7, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s8, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s8, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s9, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 96 ; CHECK-NEXT: addi sp, sp, 96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB15_23: # %entry ; CHECK-NEXT: .LBB15_23: # %entry
; CHECK-NEXT: mv a4, s1 ; CHECK-NEXT: mv a4, a7
; CHECK-NEXT: fcvt.l.s s0, ft1, rtz ; CHECK-NEXT: fcvt.l.s a6, ft1, rtz
; CHECK-NEXT: blt a5, s1, .LBB15_12 ; CHECK-NEXT: blt a5, a7, .LBB15_12
; CHECK-NEXT: .LBB15_24: # %entry ; CHECK-NEXT: .LBB15_24: # %entry
; CHECK-NEXT: mv a5, s1 ; CHECK-NEXT: mv a5, a7
; CHECK-NEXT: blt s0, s1, .LBB15_13 ; CHECK-NEXT: blt a6, a7, .LBB15_13
; CHECK-NEXT: .LBB15_25: # %entry ; CHECK-NEXT: .LBB15_25: # %entry
; CHECK-NEXT: mv s0, s1 ; CHECK-NEXT: mv a6, a7
; CHECK-NEXT: lui s1, 1048568 ; CHECK-NEXT: lui a7, 1048568
; CHECK-NEXT: blt s1, s0, .LBB15_14 ; CHECK-NEXT: blt a7, a6, .LBB15_14
; CHECK-NEXT: .LBB15_26: # %entry ; CHECK-NEXT: .LBB15_26: # %entry
; CHECK-NEXT: lui s0, 1048568 ; CHECK-NEXT: lui a6, 1048568
; CHECK-NEXT: blt s1, a5, .LBB15_15 ; CHECK-NEXT: blt a7, a5, .LBB15_15
; CHECK-NEXT: .LBB15_27: # %entry ; CHECK-NEXT: .LBB15_27: # %entry
; CHECK-NEXT: lui a5, 1048568 ; CHECK-NEXT: lui a5, 1048568
; CHECK-NEXT: blt s1, a4, .LBB15_16 ; CHECK-NEXT: blt a7, a4, .LBB15_16
; CHECK-NEXT: .LBB15_28: # %entry ; CHECK-NEXT: .LBB15_28: # %entry
; CHECK-NEXT: lui a4, 1048568 ; CHECK-NEXT: lui a4, 1048568
; CHECK-NEXT: blt s1, a3, .LBB15_17 ; CHECK-NEXT: blt a7, a3, .LBB15_17
; CHECK-NEXT: .LBB15_29: # %entry ; CHECK-NEXT: .LBB15_29: # %entry
; CHECK-NEXT: lui a3, 1048568 ; CHECK-NEXT: lui a3, 1048568
; CHECK-NEXT: blt s1, a2, .LBB15_18 ; CHECK-NEXT: blt a7, a2, .LBB15_18
; CHECK-NEXT: .LBB15_30: # %entry ; CHECK-NEXT: .LBB15_30: # %entry
; CHECK-NEXT: lui a2, 1048568 ; CHECK-NEXT: lui a2, 1048568
; CHECK-NEXT: blt s1, a1, .LBB15_19 ; CHECK-NEXT: blt a7, a1, .LBB15_19
; CHECK-NEXT: .LBB15_31: # %entry ; CHECK-NEXT: .LBB15_31: # %entry
; CHECK-NEXT: lui a1, 1048568 ; CHECK-NEXT: lui a1, 1048568
; CHECK-NEXT: blt s1, s9, .LBB15_20 ; CHECK-NEXT: blt a7, s7, .LBB15_20
; CHECK-NEXT: .LBB15_32: # %entry ; CHECK-NEXT: .LBB15_32: # %entry
; CHECK-NEXT: lui s9, 1048568 ; CHECK-NEXT: lui s7, 1048568
; CHECK-NEXT: bge s1, a0, .LBB15_21 ; CHECK-NEXT: bge a7, a0, .LBB15_21
; CHECK-NEXT: j .LBB15_22 ; CHECK-NEXT: j .LBB15_22
entry: entry:
%conv = fptosi <8 x half> %x to <8 x i32> %conv = fptosi <8 x half> %x to <8 x i32>
%0 = icmp slt <8 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> %0 = icmp slt <8 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>
%spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767> %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>
%1 = icmp sgt <8 x i32> %spec.store.select, <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> %1 = icmp sgt <8 x i32> %spec.store.select, <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>
%spec.store.select7 = select <8 x i1> %1, <8 x i32> %spec.store.select, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768> %spec.store.select7 = select <8 x i1> %1, <8 x i32> %spec.store.select, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>
%conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16> %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>
Show All 21 Lines
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: .cfi_offset s3, -40 ; CHECK-NEXT: .cfi_offset s3, -40
; CHECK-NEXT: .cfi_offset s4, -48 ; CHECK-NEXT: .cfi_offset s4, -48
; CHECK-NEXT: .cfi_offset s5, -56 ; CHECK-NEXT: .cfi_offset s5, -56
; CHECK-NEXT: .cfi_offset s6, -64 ; CHECK-NEXT: .cfi_offset s6, -64
; CHECK-NEXT: .cfi_offset s7, -72 ; CHECK-NEXT: .cfi_offset s7, -72
; CHECK-NEXT: .cfi_offset s8, -80 ; CHECK-NEXT: .cfi_offset s8, -80
; CHECK-NEXT: lhu s6, 0(a1) ; CHECK-NEXT: lhu s6, 0(a1)
; CHECK-NEXT: lhu s2, 56(a1) ; CHECK-NEXT: lhu s1, 56(a1)
; CHECK-NEXT: lhu s3, 48(a1) ; CHECK-NEXT: lhu s2, 48(a1)
; CHECK-NEXT: lhu s4, 40(a1) ; CHECK-NEXT: lhu s3, 40(a1)
; CHECK-NEXT: lhu s5, 32(a1) ; CHECK-NEXT: lhu s4, 32(a1)
; CHECK-NEXT: lhu s7, 24(a1) ; CHECK-NEXT: lhu s5, 24(a1)
; CHECK-NEXT: lhu s1, 16(a1) ; CHECK-NEXT: lhu s7, 16(a1)
; CHECK-NEXT: lhu a1, 8(a1) ; CHECK-NEXT: lhu a1, 8(a1)
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s8, a0 ; CHECK-NEXT: mv s8, a0
; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: mv a0, s7 ; CHECK-NEXT: mv a0, s7
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s7, a0 ; CHECK-NEXT: mv s7, a0
; CHECK-NEXT: mv a0, s5 ; CHECK-NEXT: mv a0, s5
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s5, a0 ; CHECK-NEXT: mv s5, a0
; CHECK-NEXT: mv a0, s4 ; CHECK-NEXT: mv a0, s4
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s4, a0 ; CHECK-NEXT: mv s4, a0
; CHECK-NEXT: mv a0, s3 ; CHECK-NEXT: mv a0, s3
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s3, a0 ; CHECK-NEXT: mv s3, a0
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: fmv.w.x ft0, s1 ; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: fmv.w.x ft0, s7
; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill ; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: fmv.w.x ft0, s8 ; CHECK-NEXT: fmv.w.x ft0, s8
; CHECK-NEXT: fcvt.lu.s s8, ft0, rtz ; CHECK-NEXT: fcvt.lu.s s7, ft0, rtz
; CHECK-NEXT: mv a0, s6 ; CHECK-NEXT: mv a0, s6
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: fcvt.lu.s a6, ft0, rtz ; CHECK-NEXT: fcvt.lu.s a0, ft0, rtz
; CHECK-NEXT: lui a0, 16 ; CHECK-NEXT: lui a1, 16
; CHECK-NEXT: addiw a1, a0, -1 ; CHECK-NEXT: addiw a1, a1, -1
; CHECK-NEXT: bltu a6, a1, .LBB16_2 ; CHECK-NEXT: bltu a0, a1, .LBB16_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a6, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB16_2: # %entry ; CHECK-NEXT: .LBB16_2: # %entry
; CHECK-NEXT: fmv.w.x ft1, s7 ; CHECK-NEXT: fmv.w.x ft1, s5
; CHECK-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload ; CHECK-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: fcvt.lu.s a2, ft0, rtz ; CHECK-NEXT: fcvt.lu.s a2, ft0, rtz
; CHECK-NEXT: bltu s8, a1, .LBB16_4 ; CHECK-NEXT: bltu s7, a1, .LBB16_4
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: mv s8, a1 ; CHECK-NEXT: mv s7, a1
; CHECK-NEXT: .LBB16_4: # %entry ; CHECK-NEXT: .LBB16_4: # %entry
; CHECK-NEXT: fmv.w.x ft0, s5 ; CHECK-NEXT: fmv.w.x ft0, s4
; CHECK-NEXT: fcvt.lu.s a3, ft1, rtz ; CHECK-NEXT: fcvt.lu.s a3, ft1, rtz
; CHECK-NEXT: bltu a2, a1, .LBB16_6 ; CHECK-NEXT: bltu a2, a1, .LBB16_6
; CHECK-NEXT: # %bb.5: # %entry ; CHECK-NEXT: # %bb.5: # %entry
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB16_6: # %entry ; CHECK-NEXT: .LBB16_6: # %entry
; CHECK-NEXT: fmv.w.x ft1, s4 ; CHECK-NEXT: fmv.w.x ft1, s3
; CHECK-NEXT: fcvt.lu.s a4, ft0, rtz ; CHECK-NEXT: fcvt.lu.s a4, ft0, rtz
; CHECK-NEXT: bltu a3, a1, .LBB16_8 ; CHECK-NEXT: bltu a3, a1, .LBB16_8
; CHECK-NEXT: # %bb.7: # %entry ; CHECK-NEXT: # %bb.7: # %entry
; CHECK-NEXT: mv a3, a1 ; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: .LBB16_8: # %entry ; CHECK-NEXT: .LBB16_8: # %entry
; CHECK-NEXT: fmv.w.x ft0, s3 ; CHECK-NEXT: fmv.w.x ft0, s2
; CHECK-NEXT: fcvt.lu.s a5, ft1, rtz ; CHECK-NEXT: fcvt.lu.s a5, ft1, rtz
; CHECK-NEXT: bltu a4, a1, .LBB16_10 ; CHECK-NEXT: bltu a4, a1, .LBB16_10
; CHECK-NEXT: # %bb.9: # %entry ; CHECK-NEXT: # %bb.9: # %entry
; CHECK-NEXT: mv a4, a1 ; CHECK-NEXT: mv a4, a1
; CHECK-NEXT: .LBB16_10: # %entry ; CHECK-NEXT: .LBB16_10: # %entry
; CHECK-NEXT: fmv.w.x ft1, s2 ; CHECK-NEXT: fmv.w.x ft1, s1
; CHECK-NEXT: fcvt.lu.s s1, ft0, rtz ; CHECK-NEXT: fcvt.lu.s a6, ft0, rtz
; CHECK-NEXT: bgeu a5, a1, .LBB16_15 ; CHECK-NEXT: bgeu a5, a1, .LBB16_15
; CHECK-NEXT: # %bb.11: # %entry ; CHECK-NEXT: # %bb.11: # %entry
; CHECK-NEXT: fcvt.lu.s a0, ft1, rtz ; CHECK-NEXT: fcvt.lu.s a7, ft1, rtz
; CHECK-NEXT: bgeu s1, a1, .LBB16_16 ; CHECK-NEXT: bgeu a6, a1, .LBB16_16
; CHECK-NEXT: .LBB16_12: # %entry ; CHECK-NEXT: .LBB16_12: # %entry
; CHECK-NEXT: bltu a0, a1, .LBB16_14 ; CHECK-NEXT: bltu a7, a1, .LBB16_14
; CHECK-NEXT: .LBB16_13: # %entry ; CHECK-NEXT: .LBB16_13: # %entry
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a7, a1
; CHECK-NEXT: .LBB16_14: # %entry ; CHECK-NEXT: .LBB16_14: # %entry
; CHECK-NEXT: sh a0, 14(s0) ; CHECK-NEXT: sh a7, 14(s0)
; CHECK-NEXT: sh s1, 12(s0) ; CHECK-NEXT: sh a6, 12(s0)
; CHECK-NEXT: sh a5, 10(s0) ; CHECK-NEXT: sh a5, 10(s0)
; CHECK-NEXT: sh a4, 8(s0) ; CHECK-NEXT: sh a4, 8(s0)
; CHECK-NEXT: sh a3, 6(s0) ; CHECK-NEXT: sh a3, 6(s0)
; CHECK-NEXT: sh a2, 4(s0) ; CHECK-NEXT: sh a2, 4(s0)
; CHECK-NEXT: sh s8, 2(s0) ; CHECK-NEXT: sh s7, 2(s0)
; CHECK-NEXT: sh a6, 0(s0) ; CHECK-NEXT: sh a0, 0(s0)
; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 80(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 72(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 72(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 64(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 64(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s3, 56(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s3, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s4, 48(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s4, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s5, 40(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s5, 40(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s6, 32(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s6, 32(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s7, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s7, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s8, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s8, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 96 ; CHECK-NEXT: addi sp, sp, 96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB16_15: # %entry ; CHECK-NEXT: .LBB16_15: # %entry
; CHECK-NEXT: mv a5, a1 ; CHECK-NEXT: mv a5, a1
; CHECK-NEXT: fcvt.lu.s a0, ft1, rtz ; CHECK-NEXT: fcvt.lu.s a7, ft1, rtz
; CHECK-NEXT: bltu s1, a1, .LBB16_12 ; CHECK-NEXT: bltu a6, a1, .LBB16_12
; CHECK-NEXT: .LBB16_16: # %entry ; CHECK-NEXT: .LBB16_16: # %entry
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv a6, a1
; CHECK-NEXT: bgeu a0, a1, .LBB16_13 ; CHECK-NEXT: bgeu a7, a1, .LBB16_13
; CHECK-NEXT: j .LBB16_14 ; CHECK-NEXT: j .LBB16_14
entry: entry:
%conv = fptoui <8 x half> %x to <8 x i32> %conv = fptoui <8 x half> %x to <8 x i32>
%0 = icmp ult <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535> %0 = icmp ult <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
%spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535> %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
%conv6 = trunc <8 x i32> %spec.store.select to <8 x i16> %conv6 = trunc <8 x i32> %spec.store.select to <8 x i16>
ret <8 x i16> %conv6 ret <8 x i16> %conv6
} }
define <8 x i16> @ustest_f16i16(<8 x half> %x) { define <8 x i16> @ustest_f16i16(<8 x half> %x) {
; CHECK-LABEL: ustest_f16i16: ; CHECK-LABEL: ustest_f16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -96 ; CHECK-NEXT: addi sp, sp, -96
; CHECK-NEXT: .cfi_def_cfa_offset 96 ; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: sd ra, 88(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 88(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 80(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 80(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 64(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 64(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s3, 56(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s3, 56(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s4, 48(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s4, 48(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s5, 40(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s5, 40(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s6, 32(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s6, 32(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s7, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s7, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s8, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s8, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s9, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: .cfi_offset s3, -40 ; CHECK-NEXT: .cfi_offset s3, -40
; CHECK-NEXT: .cfi_offset s4, -48 ; CHECK-NEXT: .cfi_offset s4, -48
; CHECK-NEXT: .cfi_offset s5, -56 ; CHECK-NEXT: .cfi_offset s5, -56
; CHECK-NEXT: .cfi_offset s6, -64 ; CHECK-NEXT: .cfi_offset s6, -64
; CHECK-NEXT: .cfi_offset s7, -72 ; CHECK-NEXT: .cfi_offset s7, -72
; CHECK-NEXT: .cfi_offset s8, -80 ; CHECK-NEXT: .cfi_offset s8, -80
; CHECK-NEXT: .cfi_offset s9, -88
; CHECK-NEXT: lhu s6, 56(a1) ; CHECK-NEXT: lhu s6, 56(a1)
; CHECK-NEXT: lhu s2, 0(a1) ; CHECK-NEXT: lhu s1, 0(a1)
; CHECK-NEXT: lhu s3, 8(a1) ; CHECK-NEXT: lhu s2, 8(a1)
; CHECK-NEXT: lhu s4, 16(a1) ; CHECK-NEXT: lhu s3, 16(a1)
; CHECK-NEXT: lhu s5, 24(a1) ; CHECK-NEXT: lhu s4, 24(a1)
; CHECK-NEXT: lhu s1, 32(a1) ; CHECK-NEXT: lhu s5, 32(a1)
; CHECK-NEXT: lhu s0, 40(a1) ; CHECK-NEXT: lhu s7, 40(a1)
; CHECK-NEXT: lhu a1, 48(a1) ; CHECK-NEXT: lhu a1, 48(a1)
; CHECK-NEXT: mv s8, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s9, a0 ; CHECK-NEXT: mv s8, a0
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s7
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s7, a0 ; CHECK-NEXT: mv s7, a0
; CHECK-NEXT: mv a0, s5 ; CHECK-NEXT: mv a0, s5
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s5, a0 ; CHECK-NEXT: mv s5, a0
; CHECK-NEXT: mv a0, s4 ; CHECK-NEXT: mv a0, s4
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s4, a0 ; CHECK-NEXT: mv s4, a0
; CHECK-NEXT: mv a0, s3 ; CHECK-NEXT: mv a0, s3
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s3, a0 ; CHECK-NEXT: mv s3, a0
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: fmv.w.x ft0, s0 ; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, s9 ; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: fcvt.l.s s9, ft0, rtz ; CHECK-NEXT: fmv.w.x ft0, s7
; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: fmv.w.x ft0, s8
; CHECK-NEXT: fcvt.l.s s7, ft0, rtz
; CHECK-NEXT: mv a0, s6 ; CHECK-NEXT: mv a0, s6
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: fcvt.l.s a0, ft0, rtz ; CHECK-NEXT: fcvt.l.s a0, ft0, rtz
; CHECK-NEXT: lui a1, 16 ; CHECK-NEXT: lui a1, 16
; CHECK-NEXT: addiw s1, a1, -1 ; CHECK-NEXT: addiw a7, a1, -1
; CHECK-NEXT: blt a0, s1, .LBB17_2 ; CHECK-NEXT: blt a0, a7, .LBB17_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a0, s1 ; CHECK-NEXT: mv a0, a7
; CHECK-NEXT: .LBB17_2: # %entry ; CHECK-NEXT: .LBB17_2: # %entry
; CHECK-NEXT: fmv.w.x ft1, s7 ; CHECK-NEXT: fmv.w.x ft1, s5
; CHECK-NEXT: flw ft0, 4(sp) # 4-byte Folded Reload ; CHECK-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: fcvt.l.s a1, ft0, rtz ; CHECK-NEXT: fcvt.l.s a1, ft0, rtz
; CHECK-NEXT: blt s9, s1, .LBB17_4 ; CHECK-NEXT: blt s7, a7, .LBB17_4
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: mv s9, s1 ; CHECK-NEXT: mv s7, a7
; CHECK-NEXT: .LBB17_4: # %entry ; CHECK-NEXT: .LBB17_4: # %entry
; CHECK-NEXT: fmv.w.x ft0, s5 ; CHECK-NEXT: fmv.w.x ft0, s4
; CHECK-NEXT: fcvt.l.s a2, ft1, rtz ; CHECK-NEXT: fcvt.l.s a2, ft1, rtz
; CHECK-NEXT: blt a1, s1, .LBB17_6 ; CHECK-NEXT: blt a1, a7, .LBB17_6
; CHECK-NEXT: # %bb.5: # %entry ; CHECK-NEXT: # %bb.5: # %entry
; CHECK-NEXT: mv a1, s1 ; CHECK-NEXT: mv a1, a7
; CHECK-NEXT: .LBB17_6: # %entry ; CHECK-NEXT: .LBB17_6: # %entry
; CHECK-NEXT: fmv.w.x ft1, s4 ; CHECK-NEXT: fmv.w.x ft1, s3
; CHECK-NEXT: fcvt.l.s a3, ft0, rtz ; CHECK-NEXT: fcvt.l.s a3, ft0, rtz
; CHECK-NEXT: blt a2, s1, .LBB17_8 ; CHECK-NEXT: blt a2, a7, .LBB17_8
; CHECK-NEXT: # %bb.7: # %entry ; CHECK-NEXT: # %bb.7: # %entry
; CHECK-NEXT: mv a2, s1 ; CHECK-NEXT: mv a2, a7
; CHECK-NEXT: .LBB17_8: # %entry ; CHECK-NEXT: .LBB17_8: # %entry
; CHECK-NEXT: fmv.w.x ft0, s3 ; CHECK-NEXT: fmv.w.x ft0, s2
; CHECK-NEXT: fcvt.l.s a4, ft1, rtz ; CHECK-NEXT: fcvt.l.s a4, ft1, rtz
; CHECK-NEXT: blt a3, s1, .LBB17_10 ; CHECK-NEXT: blt a3, a7, .LBB17_10
; CHECK-NEXT: # %bb.9: # %entry ; CHECK-NEXT: # %bb.9: # %entry
; CHECK-NEXT: mv a3, s1 ; CHECK-NEXT: mv a3, a7
; CHECK-NEXT: .LBB17_10: # %entry ; CHECK-NEXT: .LBB17_10: # %entry
; CHECK-NEXT: fmv.w.x ft1, s2 ; CHECK-NEXT: fmv.w.x ft1, s1
; CHECK-NEXT: fcvt.l.s a5, ft0, rtz ; CHECK-NEXT: fcvt.l.s a5, ft0, rtz
; CHECK-NEXT: bge a4, s1, .LBB17_23 ; CHECK-NEXT: bge a4, a7, .LBB17_23
; CHECK-NEXT: # %bb.11: # %entry ; CHECK-NEXT: # %bb.11: # %entry
; CHECK-NEXT: fcvt.l.s s0, ft1, rtz ; CHECK-NEXT: fcvt.l.s a6, ft1, rtz
; CHECK-NEXT: bge a5, s1, .LBB17_24 ; CHECK-NEXT: bge a5, a7, .LBB17_24
; CHECK-NEXT: .LBB17_12: # %entry ; CHECK-NEXT: .LBB17_12: # %entry
; CHECK-NEXT: bge s0, s1, .LBB17_25 ; CHECK-NEXT: bge a6, a7, .LBB17_25
; CHECK-NEXT: .LBB17_13: # %entry ; CHECK-NEXT: .LBB17_13: # %entry
; CHECK-NEXT: blez s0, .LBB17_26 ; CHECK-NEXT: blez a6, .LBB17_26
; CHECK-NEXT: .LBB17_14: # %entry ; CHECK-NEXT: .LBB17_14: # %entry
; CHECK-NEXT: blez a5, .LBB17_27 ; CHECK-NEXT: blez a5, .LBB17_27
; CHECK-NEXT: .LBB17_15: # %entry ; CHECK-NEXT: .LBB17_15: # %entry
; CHECK-NEXT: blez a4, .LBB17_28 ; CHECK-NEXT: blez a4, .LBB17_28
; CHECK-NEXT: .LBB17_16: # %entry ; CHECK-NEXT: .LBB17_16: # %entry
; CHECK-NEXT: blez a3, .LBB17_29 ; CHECK-NEXT: blez a3, .LBB17_29
; CHECK-NEXT: .LBB17_17: # %entry ; CHECK-NEXT: .LBB17_17: # %entry
; CHECK-NEXT: blez a2, .LBB17_30 ; CHECK-NEXT: blez a2, .LBB17_30
; CHECK-NEXT: .LBB17_18: # %entry ; CHECK-NEXT: .LBB17_18: # %entry
; CHECK-NEXT: blez a1, .LBB17_31 ; CHECK-NEXT: blez a1, .LBB17_31
; CHECK-NEXT: .LBB17_19: # %entry ; CHECK-NEXT: .LBB17_19: # %entry
; CHECK-NEXT: blez s9, .LBB17_32 ; CHECK-NEXT: blez s7, .LBB17_32
; CHECK-NEXT: .LBB17_20: # %entry ; CHECK-NEXT: .LBB17_20: # %entry
; CHECK-NEXT: bgtz a0, .LBB17_22 ; CHECK-NEXT: bgtz a0, .LBB17_22
; CHECK-NEXT: .LBB17_21: # %entry ; CHECK-NEXT: .LBB17_21: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: .LBB17_22: # %entry ; CHECK-NEXT: .LBB17_22: # %entry
; CHECK-NEXT: sh a0, 14(s8) ; CHECK-NEXT: sh a0, 14(s0)
; CHECK-NEXT: sh s9, 12(s8) ; CHECK-NEXT: sh s7, 12(s0)
; CHECK-NEXT: sh a1, 10(s8) ; CHECK-NEXT: sh a1, 10(s0)
; CHECK-NEXT: sh a2, 8(s8) ; CHECK-NEXT: sh a2, 8(s0)
; CHECK-NEXT: sh a3, 6(s8) ; CHECK-NEXT: sh a3, 6(s0)
; CHECK-NEXT: sh a4, 4(s8) ; CHECK-NEXT: sh a4, 4(s0)
; CHECK-NEXT: sh a5, 2(s8) ; CHECK-NEXT: sh a5, 2(s0)
; CHECK-NEXT: sh s0, 0(s8) ; CHECK-NEXT: sh a6, 0(s0)
; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 80(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 72(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 72(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 64(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 64(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s3, 56(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s3, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s4, 48(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s4, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s5, 40(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s5, 40(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s6, 32(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s6, 32(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s7, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s7, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s8, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s8, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s9, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 96 ; CHECK-NEXT: addi sp, sp, 96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB17_23: # %entry ; CHECK-NEXT: .LBB17_23: # %entry
; CHECK-NEXT: mv a4, s1 ; CHECK-NEXT: mv a4, a7
; CHECK-NEXT: fcvt.l.s s0, ft1, rtz ; CHECK-NEXT: fcvt.l.s a6, ft1, rtz
; CHECK-NEXT: blt a5, s1, .LBB17_12 ; CHECK-NEXT: blt a5, a7, .LBB17_12
; CHECK-NEXT: .LBB17_24: # %entry ; CHECK-NEXT: .LBB17_24: # %entry
; CHECK-NEXT: mv a5, s1 ; CHECK-NEXT: mv a5, a7
; CHECK-NEXT: blt s0, s1, .LBB17_13 ; CHECK-NEXT: blt a6, a7, .LBB17_13
; CHECK-NEXT: .LBB17_25: # %entry ; CHECK-NEXT: .LBB17_25: # %entry
; CHECK-NEXT: mv s0, s1 ; CHECK-NEXT: mv a6, a7
; CHECK-NEXT: bgtz s0, .LBB17_14 ; CHECK-NEXT: bgtz a6, .LBB17_14
; CHECK-NEXT: .LBB17_26: # %entry ; CHECK-NEXT: .LBB17_26: # %entry
; CHECK-NEXT: li s0, 0 ; CHECK-NEXT: li a6, 0
; CHECK-NEXT: bgtz a5, .LBB17_15 ; CHECK-NEXT: bgtz a5, .LBB17_15
; CHECK-NEXT: .LBB17_27: # %entry ; CHECK-NEXT: .LBB17_27: # %entry
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: bgtz a4, .LBB17_16 ; CHECK-NEXT: bgtz a4, .LBB17_16
; CHECK-NEXT: .LBB17_28: # %entry ; CHECK-NEXT: .LBB17_28: # %entry
; CHECK-NEXT: li a4, 0 ; CHECK-NEXT: li a4, 0
; CHECK-NEXT: bgtz a3, .LBB17_17 ; CHECK-NEXT: bgtz a3, .LBB17_17
; CHECK-NEXT: .LBB17_29: # %entry ; CHECK-NEXT: .LBB17_29: # %entry
; CHECK-NEXT: li a3, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: bgtz a2, .LBB17_18 ; CHECK-NEXT: bgtz a2, .LBB17_18
; CHECK-NEXT: .LBB17_30: # %entry ; CHECK-NEXT: .LBB17_30: # %entry
; CHECK-NEXT: li a2, 0 ; CHECK-NEXT: li a2, 0
; CHECK-NEXT: bgtz a1, .LBB17_19 ; CHECK-NEXT: bgtz a1, .LBB17_19
; CHECK-NEXT: .LBB17_31: # %entry ; CHECK-NEXT: .LBB17_31: # %entry
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: bgtz s9, .LBB17_20 ; CHECK-NEXT: bgtz s7, .LBB17_20
; CHECK-NEXT: .LBB17_32: # %entry ; CHECK-NEXT: .LBB17_32: # %entry
; CHECK-NEXT: li s9, 0 ; CHECK-NEXT: li s7, 0
; CHECK-NEXT: blez a0, .LBB17_21 ; CHECK-NEXT: blez a0, .LBB17_21
; CHECK-NEXT: j .LBB17_22 ; CHECK-NEXT: j .LBB17_22
entry: entry:
%conv = fptosi <8 x half> %x to <8 x i32> %conv = fptosi <8 x half> %x to <8 x i32>
%0 = icmp slt <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535> %0 = icmp slt <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
%spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535> %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
%1 = icmp sgt <8 x i32> %spec.store.select, zeroinitializer %1 = icmp sgt <8 x i32> %spec.store.select, zeroinitializer
%spec.store.select7 = select <8 x i1> %1, <8 x i32> %spec.store.select, <8 x i32> zeroinitializer %spec.store.select7 = select <8 x i1> %1, <8 x i32> %spec.store.select, <8 x i32> zeroinitializer
Show All 11 Lines
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s0, a1 ; CHECK-NEXT: mv s2, a1
; CHECK-NEXT: call __fixdfti@plt ; CHECK-NEXT: call __fixdfti@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv s1, a1
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __fixdfti@plt ; CHECK-NEXT: call __fixdfti@plt
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: li a0, -1 ; CHECK-NEXT: li a0, -1
; CHECK-NEXT: srli a3, a0, 1 ; CHECK-NEXT: srli a3, a0, 1
; CHECK-NEXT: beqz a1, .LBB18_3 ; CHECK-NEXT: beqz a1, .LBB18_3
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: slti a4, a1, 0 ; CHECK-NEXT: slti a4, a1, 0
; CHECK-NEXT: bnez s1, .LBB18_4 ; CHECK-NEXT: bnez s1, .LBB18_4
; CHECK-NEXT: .LBB18_2: ; CHECK-NEXT: .LBB18_2:
; CHECK-NEXT: sltu a5, s2, a3 ; CHECK-NEXT: sltu a5, s0, a3
; CHECK-NEXT: beqz a5, .LBB18_5 ; CHECK-NEXT: beqz a5, .LBB18_5
; CHECK-NEXT: j .LBB18_6 ; CHECK-NEXT: j .LBB18_6
; CHECK-NEXT: .LBB18_3: ; CHECK-NEXT: .LBB18_3:
; CHECK-NEXT: sltu a4, a2, a3 ; CHECK-NEXT: sltu a4, a2, a3
; CHECK-NEXT: beqz s1, .LBB18_2 ; CHECK-NEXT: beqz s1, .LBB18_2
; CHECK-NEXT: .LBB18_4: # %entry ; CHECK-NEXT: .LBB18_4: # %entry
; CHECK-NEXT: slti a5, s1, 0 ; CHECK-NEXT: slti a5, s1, 0
; CHECK-NEXT: bnez a5, .LBB18_6 ; CHECK-NEXT: bnez a5, .LBB18_6
; CHECK-NEXT: .LBB18_5: # %entry ; CHECK-NEXT: .LBB18_5: # %entry
; CHECK-NEXT: li s1, 0 ; CHECK-NEXT: li s1, 0
; CHECK-NEXT: mv s2, a3 ; CHECK-NEXT: mv s0, a3
; CHECK-NEXT: .LBB18_6: # %entry ; CHECK-NEXT: .LBB18_6: # %entry
; CHECK-NEXT: beqz a4, .LBB18_10 ; CHECK-NEXT: beqz a4, .LBB18_10
; CHECK-NEXT: # %bb.7: # %entry ; CHECK-NEXT: # %bb.7: # %entry
; CHECK-NEXT: slli a3, a0, 63 ; CHECK-NEXT: slli a3, a0, 63
; CHECK-NEXT: beq a1, a0, .LBB18_11 ; CHECK-NEXT: beq a1, a0, .LBB18_11
; CHECK-NEXT: .LBB18_8: # %entry ; CHECK-NEXT: .LBB18_8: # %entry
; CHECK-NEXT: slt a1, a0, a1 ; CHECK-NEXT: slt a1, a0, a1
; CHECK-NEXT: bne s1, a0, .LBB18_12 ; CHECK-NEXT: bne s1, a0, .LBB18_12
; CHECK-NEXT: .LBB18_9: ; CHECK-NEXT: .LBB18_9:
; CHECK-NEXT: sltu a0, a3, s2 ; CHECK-NEXT: sltu a0, a3, s0
; CHECK-NEXT: beqz a0, .LBB18_13 ; CHECK-NEXT: beqz a0, .LBB18_13
; CHECK-NEXT: j .LBB18_14 ; CHECK-NEXT: j .LBB18_14
; CHECK-NEXT: .LBB18_10: # %entry ; CHECK-NEXT: .LBB18_10: # %entry
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: mv a2, a3 ; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: slli a3, a0, 63 ; CHECK-NEXT: slli a3, a0, 63
; CHECK-NEXT: bne a1, a0, .LBB18_8 ; CHECK-NEXT: bne a1, a0, .LBB18_8
; CHECK-NEXT: .LBB18_11: ; CHECK-NEXT: .LBB18_11:
; CHECK-NEXT: sltu a1, a3, a2 ; CHECK-NEXT: sltu a1, a3, a2
; CHECK-NEXT: beq s1, a0, .LBB18_9 ; CHECK-NEXT: beq s1, a0, .LBB18_9
; CHECK-NEXT: .LBB18_12: # %entry ; CHECK-NEXT: .LBB18_12: # %entry
; CHECK-NEXT: slt a0, a0, s1 ; CHECK-NEXT: slt a0, a0, s1
; CHECK-NEXT: bnez a0, .LBB18_14 ; CHECK-NEXT: bnez a0, .LBB18_14
; CHECK-NEXT: .LBB18_13: # %entry ; CHECK-NEXT: .LBB18_13: # %entry
; CHECK-NEXT: mv s2, a3 ; CHECK-NEXT: mv s0, a3
; CHECK-NEXT: .LBB18_14: # %entry ; CHECK-NEXT: .LBB18_14: # %entry
; CHECK-NEXT: bnez a1, .LBB18_16 ; CHECK-NEXT: bnez a1, .LBB18_16
; CHECK-NEXT: # %bb.15: # %entry ; CHECK-NEXT: # %bb.15: # %entry
; CHECK-NEXT: mv a2, a3 ; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB18_16: # %entry ; CHECK-NEXT: .LBB18_16: # %entry
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s0
; CHECK-NEXT: mv a1, a2 ; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 14 Lines
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __fixunsdfti@plt ; CHECK-NEXT: call __fixunsdfti@plt
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv s2, a1 ; CHECK-NEXT: mv s1, a1
; CHECK-NEXT: mv a0, s1 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __fixunsdfti@plt ; CHECK-NEXT: call __fixunsdfti@plt
; CHECK-NEXT: beqz a1, .LBB19_2 ; CHECK-NEXT: beqz a1, .LBB19_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: .LBB19_2: # %entry ; CHECK-NEXT: .LBB19_2: # %entry
; CHECK-NEXT: beqz s2, .LBB19_4 ; CHECK-NEXT: beqz s1, .LBB19_4
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: li s0, 0 ; CHECK-NEXT: li s0, 0
; CHECK-NEXT: .LBB19_4: # %entry ; CHECK-NEXT: .LBB19_4: # %entry
; CHECK-NEXT: mv a1, s0 ; CHECK-NEXT: mv a1, s0
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
Show All 15 Lines
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __fixdfti@plt ; CHECK-NEXT: call __fixdfti@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv s1, a1
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __fixdfti@plt ; CHECK-NEXT: call __fixdfti@plt
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bgtz a1, .LBB20_7 ; CHECK-NEXT: bgtz a1, .LBB20_7
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a3, s1 ; CHECK-NEXT: mv a3, s1
; CHECK-NEXT: bgtz s1, .LBB20_8 ; CHECK-NEXT: bgtz s1, .LBB20_8
; CHECK-NEXT: .LBB20_2: # %entry ; CHECK-NEXT: .LBB20_2: # %entry
; CHECK-NEXT: bgtz a1, .LBB20_9 ; CHECK-NEXT: bgtz a1, .LBB20_9
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; CHECK-NEXT: blez s1, .LBB20_2 ; CHECK-NEXT: blez s1, .LBB20_2
; CHECK-NEXT: .LBB20_8: # %entry ; CHECK-NEXT: .LBB20_8: # %entry
; CHECK-NEXT: li a3, 1 ; CHECK-NEXT: li a3, 1
; CHECK-NEXT: blez a1, .LBB20_3 ; CHECK-NEXT: blez a1, .LBB20_3
; CHECK-NEXT: .LBB20_9: # %entry ; CHECK-NEXT: .LBB20_9: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: blez s1, .LBB20_4 ; CHECK-NEXT: blez s1, .LBB20_4
; CHECK-NEXT: .LBB20_10: # %entry ; CHECK-NEXT: .LBB20_10: # %entry
; CHECK-NEXT: li s2, 0 ; CHECK-NEXT: li s0, 0
; CHECK-NEXT: bnez a3, .LBB20_5 ; CHECK-NEXT: bnez a3, .LBB20_5
; CHECK-NEXT: .LBB20_11: ; CHECK-NEXT: .LBB20_11:
; CHECK-NEXT: snez a1, s2 ; CHECK-NEXT: snez a1, s0
; CHECK-NEXT: beqz a2, .LBB20_6 ; CHECK-NEXT: beqz a2, .LBB20_6
; CHECK-NEXT: .LBB20_12: # %entry ; CHECK-NEXT: .LBB20_12: # %entry
; CHECK-NEXT: sgtz a2, a2 ; CHECK-NEXT: sgtz a2, a2
; CHECK-NEXT: bnez a2, .LBB20_14 ; CHECK-NEXT: bnez a2, .LBB20_14
; CHECK-NEXT: .LBB20_13: # %entry ; CHECK-NEXT: .LBB20_13: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: .LBB20_14: # %entry ; CHECK-NEXT: .LBB20_14: # %entry
; CHECK-NEXT: bnez a1, .LBB20_16 ; CHECK-NEXT: bnez a1, .LBB20_16
; CHECK-NEXT: # %bb.15: # %entry ; CHECK-NEXT: # %bb.15: # %entry
; CHECK-NEXT: li s2, 0 ; CHECK-NEXT: li s0, 0
; CHECK-NEXT: .LBB20_16: # %entry ; CHECK-NEXT: .LBB20_16: # %entry
; CHECK-NEXT: mv a1, s2 ; CHECK-NEXT: mv a1, s0
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%conv = fptosi <2 x double> %x to <2 x i128> %conv = fptosi <2 x double> %x to <2 x i128>
Show All 13 Lines
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s0, a1 ; CHECK-NEXT: mv s2, a1
; CHECK-NEXT: call __fixsfti@plt ; CHECK-NEXT: call __fixsfti@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv s1, a1
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __fixsfti@plt ; CHECK-NEXT: call __fixsfti@plt
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: li a0, -1 ; CHECK-NEXT: li a0, -1
; CHECK-NEXT: srli a3, a0, 1 ; CHECK-NEXT: srli a3, a0, 1
; CHECK-NEXT: beqz a1, .LBB21_3 ; CHECK-NEXT: beqz a1, .LBB21_3
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: slti a4, a1, 0 ; CHECK-NEXT: slti a4, a1, 0
; CHECK-NEXT: bnez s1, .LBB21_4 ; CHECK-NEXT: bnez s1, .LBB21_4
; CHECK-NEXT: .LBB21_2: ; CHECK-NEXT: .LBB21_2:
; CHECK-NEXT: sltu a5, s2, a3 ; CHECK-NEXT: sltu a5, s0, a3
; CHECK-NEXT: beqz a5, .LBB21_5 ; CHECK-NEXT: beqz a5, .LBB21_5
; CHECK-NEXT: j .LBB21_6 ; CHECK-NEXT: j .LBB21_6
; CHECK-NEXT: .LBB21_3: ; CHECK-NEXT: .LBB21_3:
; CHECK-NEXT: sltu a4, a2, a3 ; CHECK-NEXT: sltu a4, a2, a3
; CHECK-NEXT: beqz s1, .LBB21_2 ; CHECK-NEXT: beqz s1, .LBB21_2
; CHECK-NEXT: .LBB21_4: # %entry ; CHECK-NEXT: .LBB21_4: # %entry
; CHECK-NEXT: slti a5, s1, 0 ; CHECK-NEXT: slti a5, s1, 0
; CHECK-NEXT: bnez a5, .LBB21_6 ; CHECK-NEXT: bnez a5, .LBB21_6
; CHECK-NEXT: .LBB21_5: # %entry ; CHECK-NEXT: .LBB21_5: # %entry
; CHECK-NEXT: li s1, 0 ; CHECK-NEXT: li s1, 0
; CHECK-NEXT: mv s2, a3 ; CHECK-NEXT: mv s0, a3
; CHECK-NEXT: .LBB21_6: # %entry ; CHECK-NEXT: .LBB21_6: # %entry
; CHECK-NEXT: beqz a4, .LBB21_10 ; CHECK-NEXT: beqz a4, .LBB21_10
; CHECK-NEXT: # %bb.7: # %entry ; CHECK-NEXT: # %bb.7: # %entry
; CHECK-NEXT: slli a3, a0, 63 ; CHECK-NEXT: slli a3, a0, 63
; CHECK-NEXT: beq a1, a0, .LBB21_11 ; CHECK-NEXT: beq a1, a0, .LBB21_11
; CHECK-NEXT: .LBB21_8: # %entry ; CHECK-NEXT: .LBB21_8: # %entry
; CHECK-NEXT: slt a1, a0, a1 ; CHECK-NEXT: slt a1, a0, a1
; CHECK-NEXT: bne s1, a0, .LBB21_12 ; CHECK-NEXT: bne s1, a0, .LBB21_12
; CHECK-NEXT: .LBB21_9: ; CHECK-NEXT: .LBB21_9:
; CHECK-NEXT: sltu a0, a3, s2 ; CHECK-NEXT: sltu a0, a3, s0
; CHECK-NEXT: beqz a0, .LBB21_13 ; CHECK-NEXT: beqz a0, .LBB21_13
; CHECK-NEXT: j .LBB21_14 ; CHECK-NEXT: j .LBB21_14
; CHECK-NEXT: .LBB21_10: # %entry ; CHECK-NEXT: .LBB21_10: # %entry
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: mv a2, a3 ; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: slli a3, a0, 63 ; CHECK-NEXT: slli a3, a0, 63
; CHECK-NEXT: bne a1, a0, .LBB21_8 ; CHECK-NEXT: bne a1, a0, .LBB21_8
; CHECK-NEXT: .LBB21_11: ; CHECK-NEXT: .LBB21_11:
; CHECK-NEXT: sltu a1, a3, a2 ; CHECK-NEXT: sltu a1, a3, a2
; CHECK-NEXT: beq s1, a0, .LBB21_9 ; CHECK-NEXT: beq s1, a0, .LBB21_9
; CHECK-NEXT: .LBB21_12: # %entry ; CHECK-NEXT: .LBB21_12: # %entry
; CHECK-NEXT: slt a0, a0, s1 ; CHECK-NEXT: slt a0, a0, s1
; CHECK-NEXT: bnez a0, .LBB21_14 ; CHECK-NEXT: bnez a0, .LBB21_14
; CHECK-NEXT: .LBB21_13: # %entry ; CHECK-NEXT: .LBB21_13: # %entry
; CHECK-NEXT: mv s2, a3 ; CHECK-NEXT: mv s0, a3
; CHECK-NEXT: .LBB21_14: # %entry ; CHECK-NEXT: .LBB21_14: # %entry
; CHECK-NEXT: bnez a1, .LBB21_16 ; CHECK-NEXT: bnez a1, .LBB21_16
; CHECK-NEXT: # %bb.15: # %entry ; CHECK-NEXT: # %bb.15: # %entry
; CHECK-NEXT: mv a2, a3 ; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB21_16: # %entry ; CHECK-NEXT: .LBB21_16: # %entry
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s0
; CHECK-NEXT: mv a1, a2 ; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
Show All 14 Lines
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __fixunssfti@plt ; CHECK-NEXT: call __fixunssfti@plt
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv s2, a1 ; CHECK-NEXT: mv s1, a1
; CHECK-NEXT: mv a0, s1 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __fixunssfti@plt ; CHECK-NEXT: call __fixunssfti@plt
; CHECK-NEXT: beqz a1, .LBB22_2 ; CHECK-NEXT: beqz a1, .LBB22_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: .LBB22_2: # %entry ; CHECK-NEXT: .LBB22_2: # %entry
; CHECK-NEXT: beqz s2, .LBB22_4 ; CHECK-NEXT: beqz s1, .LBB22_4
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: li s0, 0 ; CHECK-NEXT: li s0, 0
; CHECK-NEXT: .LBB22_4: # %entry ; CHECK-NEXT: .LBB22_4: # %entry
; CHECK-NEXT: mv a1, s0 ; CHECK-NEXT: mv a1, s0
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
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; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __fixsfti@plt ; CHECK-NEXT: call __fixsfti@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv s1, a1
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __fixsfti@plt ; CHECK-NEXT: call __fixsfti@plt
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bgtz a1, .LBB23_7 ; CHECK-NEXT: bgtz a1, .LBB23_7
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a3, s1 ; CHECK-NEXT: mv a3, s1
; CHECK-NEXT: bgtz s1, .LBB23_8 ; CHECK-NEXT: bgtz s1, .LBB23_8
; CHECK-NEXT: .LBB23_2: # %entry ; CHECK-NEXT: .LBB23_2: # %entry
; CHECK-NEXT: bgtz a1, .LBB23_9 ; CHECK-NEXT: bgtz a1, .LBB23_9
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; CHECK-NEXT: blez s1, .LBB23_2 ; CHECK-NEXT: blez s1, .LBB23_2
; CHECK-NEXT: .LBB23_8: # %entry ; CHECK-NEXT: .LBB23_8: # %entry
; CHECK-NEXT: li a3, 1 ; CHECK-NEXT: li a3, 1
; CHECK-NEXT: blez a1, .LBB23_3 ; CHECK-NEXT: blez a1, .LBB23_3
; CHECK-NEXT: .LBB23_9: # %entry ; CHECK-NEXT: .LBB23_9: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: blez s1, .LBB23_4 ; CHECK-NEXT: blez s1, .LBB23_4
; CHECK-NEXT: .LBB23_10: # %entry ; CHECK-NEXT: .LBB23_10: # %entry
; CHECK-NEXT: li s2, 0 ; CHECK-NEXT: li s0, 0
; CHECK-NEXT: bnez a3, .LBB23_5 ; CHECK-NEXT: bnez a3, .LBB23_5
; CHECK-NEXT: .LBB23_11: ; CHECK-NEXT: .LBB23_11:
; CHECK-NEXT: snez a1, s2 ; CHECK-NEXT: snez a1, s0
; CHECK-NEXT: beqz a2, .LBB23_6 ; CHECK-NEXT: beqz a2, .LBB23_6
; CHECK-NEXT: .LBB23_12: # %entry ; CHECK-NEXT: .LBB23_12: # %entry
; CHECK-NEXT: sgtz a2, a2 ; CHECK-NEXT: sgtz a2, a2
; CHECK-NEXT: bnez a2, .LBB23_14 ; CHECK-NEXT: bnez a2, .LBB23_14
; CHECK-NEXT: .LBB23_13: # %entry ; CHECK-NEXT: .LBB23_13: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: .LBB23_14: # %entry ; CHECK-NEXT: .LBB23_14: # %entry
; CHECK-NEXT: bnez a1, .LBB23_16 ; CHECK-NEXT: bnez a1, .LBB23_16
; CHECK-NEXT: # %bb.15: # %entry ; CHECK-NEXT: # %bb.15: # %entry
; CHECK-NEXT: li s2, 0 ; CHECK-NEXT: li s0, 0
; CHECK-NEXT: .LBB23_16: # %entry ; CHECK-NEXT: .LBB23_16: # %entry
; CHECK-NEXT: mv a1, s2 ; CHECK-NEXT: mv a1, s0
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%conv = fptosi <2 x float> %x to <2 x i128> %conv = fptosi <2 x float> %x to <2 x i128>
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; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s0, a1 ; CHECK-NEXT: mv s2, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __fixsfti@plt ; CHECK-NEXT: call __fixsfti@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv s1, a1
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __fixsfti@plt ; CHECK-NEXT: call __fixsfti@plt
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: li a0, -1 ; CHECK-NEXT: li a0, -1
; CHECK-NEXT: srli a3, a0, 1 ; CHECK-NEXT: srli a3, a0, 1
; CHECK-NEXT: beqz a1, .LBB24_3 ; CHECK-NEXT: beqz a1, .LBB24_3
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: slti a4, a1, 0 ; CHECK-NEXT: slti a4, a1, 0
; CHECK-NEXT: bnez s1, .LBB24_4 ; CHECK-NEXT: bnez s1, .LBB24_4
; CHECK-NEXT: .LBB24_2: ; CHECK-NEXT: .LBB24_2:
; CHECK-NEXT: sltu a5, s2, a3 ; CHECK-NEXT: sltu a5, s0, a3
; CHECK-NEXT: beqz a5, .LBB24_5 ; CHECK-NEXT: beqz a5, .LBB24_5
; CHECK-NEXT: j .LBB24_6 ; CHECK-NEXT: j .LBB24_6
; CHECK-NEXT: .LBB24_3: ; CHECK-NEXT: .LBB24_3:
; CHECK-NEXT: sltu a4, a2, a3 ; CHECK-NEXT: sltu a4, a2, a3
; CHECK-NEXT: beqz s1, .LBB24_2 ; CHECK-NEXT: beqz s1, .LBB24_2
; CHECK-NEXT: .LBB24_4: # %entry ; CHECK-NEXT: .LBB24_4: # %entry
; CHECK-NEXT: slti a5, s1, 0 ; CHECK-NEXT: slti a5, s1, 0
; CHECK-NEXT: bnez a5, .LBB24_6 ; CHECK-NEXT: bnez a5, .LBB24_6
; CHECK-NEXT: .LBB24_5: # %entry ; CHECK-NEXT: .LBB24_5: # %entry
; CHECK-NEXT: li s1, 0 ; CHECK-NEXT: li s1, 0
; CHECK-NEXT: mv s2, a3 ; CHECK-NEXT: mv s0, a3
; CHECK-NEXT: .LBB24_6: # %entry ; CHECK-NEXT: .LBB24_6: # %entry
; CHECK-NEXT: beqz a4, .LBB24_10 ; CHECK-NEXT: beqz a4, .LBB24_10
; CHECK-NEXT: # %bb.7: # %entry ; CHECK-NEXT: # %bb.7: # %entry
; CHECK-NEXT: slli a3, a0, 63 ; CHECK-NEXT: slli a3, a0, 63
; CHECK-NEXT: beq a1, a0, .LBB24_11 ; CHECK-NEXT: beq a1, a0, .LBB24_11
; CHECK-NEXT: .LBB24_8: # %entry ; CHECK-NEXT: .LBB24_8: # %entry
; CHECK-NEXT: slt a1, a0, a1 ; CHECK-NEXT: slt a1, a0, a1
; CHECK-NEXT: bne s1, a0, .LBB24_12 ; CHECK-NEXT: bne s1, a0, .LBB24_12
; CHECK-NEXT: .LBB24_9: ; CHECK-NEXT: .LBB24_9:
; CHECK-NEXT: sltu a0, a3, s2 ; CHECK-NEXT: sltu a0, a3, s0
; CHECK-NEXT: beqz a0, .LBB24_13 ; CHECK-NEXT: beqz a0, .LBB24_13
; CHECK-NEXT: j .LBB24_14 ; CHECK-NEXT: j .LBB24_14
; CHECK-NEXT: .LBB24_10: # %entry ; CHECK-NEXT: .LBB24_10: # %entry
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: mv a2, a3 ; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: slli a3, a0, 63 ; CHECK-NEXT: slli a3, a0, 63
; CHECK-NEXT: bne a1, a0, .LBB24_8 ; CHECK-NEXT: bne a1, a0, .LBB24_8
; CHECK-NEXT: .LBB24_11: ; CHECK-NEXT: .LBB24_11:
; CHECK-NEXT: sltu a1, a3, a2 ; CHECK-NEXT: sltu a1, a3, a2
; CHECK-NEXT: beq s1, a0, .LBB24_9 ; CHECK-NEXT: beq s1, a0, .LBB24_9
; CHECK-NEXT: .LBB24_12: # %entry ; CHECK-NEXT: .LBB24_12: # %entry
; CHECK-NEXT: slt a0, a0, s1 ; CHECK-NEXT: slt a0, a0, s1
; CHECK-NEXT: bnez a0, .LBB24_14 ; CHECK-NEXT: bnez a0, .LBB24_14
; CHECK-NEXT: .LBB24_13: # %entry ; CHECK-NEXT: .LBB24_13: # %entry
; CHECK-NEXT: mv s2, a3 ; CHECK-NEXT: mv s0, a3
; CHECK-NEXT: .LBB24_14: # %entry ; CHECK-NEXT: .LBB24_14: # %entry
; CHECK-NEXT: bnez a1, .LBB24_16 ; CHECK-NEXT: bnez a1, .LBB24_16
; CHECK-NEXT: # %bb.15: # %entry ; CHECK-NEXT: # %bb.15: # %entry
; CHECK-NEXT: mv a2, a3 ; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB24_16: # %entry ; CHECK-NEXT: .LBB24_16: # %entry
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s0
; CHECK-NEXT: mv a1, a2 ; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
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; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __fixunssfti@plt ; CHECK-NEXT: call __fixunssfti@plt
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv s2, a1 ; CHECK-NEXT: mv s1, a1
; CHECK-NEXT: mv a0, s1 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __fixunssfti@plt ; CHECK-NEXT: call __fixunssfti@plt
; CHECK-NEXT: beqz a1, .LBB25_2 ; CHECK-NEXT: beqz a1, .LBB25_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: .LBB25_2: # %entry ; CHECK-NEXT: .LBB25_2: # %entry
; CHECK-NEXT: beqz s2, .LBB25_4 ; CHECK-NEXT: beqz s1, .LBB25_4
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: li s0, 0 ; CHECK-NEXT: li s0, 0
; CHECK-NEXT: .LBB25_4: # %entry ; CHECK-NEXT: .LBB25_4: # %entry
; CHECK-NEXT: mv a1, s0 ; CHECK-NEXT: mv a1, s0
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
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; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __fixsfti@plt ; CHECK-NEXT: call __fixsfti@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv s1, a1
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __fixsfti@plt ; CHECK-NEXT: call __fixsfti@plt
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bgtz a1, .LBB26_7 ; CHECK-NEXT: bgtz a1, .LBB26_7
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a3, s1 ; CHECK-NEXT: mv a3, s1
; CHECK-NEXT: bgtz s1, .LBB26_8 ; CHECK-NEXT: bgtz s1, .LBB26_8
; CHECK-NEXT: .LBB26_2: # %entry ; CHECK-NEXT: .LBB26_2: # %entry
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; CHECK-NEXT: blez s1, .LBB26_2 ; CHECK-NEXT: blez s1, .LBB26_2
; CHECK-NEXT: .LBB26_8: # %entry ; CHECK-NEXT: .LBB26_8: # %entry
; CHECK-NEXT: li a3, 1 ; CHECK-NEXT: li a3, 1
; CHECK-NEXT: blez a1, .LBB26_3 ; CHECK-NEXT: blez a1, .LBB26_3
; CHECK-NEXT: .LBB26_9: # %entry ; CHECK-NEXT: .LBB26_9: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: blez s1, .LBB26_4 ; CHECK-NEXT: blez s1, .LBB26_4
; CHECK-NEXT: .LBB26_10: # %entry ; CHECK-NEXT: .LBB26_10: # %entry
; CHECK-NEXT: li s2, 0 ; CHECK-NEXT: li s0, 0
; CHECK-NEXT: bnez a3, .LBB26_5 ; CHECK-NEXT: bnez a3, .LBB26_5
; CHECK-NEXT: .LBB26_11: ; CHECK-NEXT: .LBB26_11:
; CHECK-NEXT: snez a1, s2 ; CHECK-NEXT: snez a1, s0
; CHECK-NEXT: beqz a2, .LBB26_6 ; CHECK-NEXT: beqz a2, .LBB26_6
; CHECK-NEXT: .LBB26_12: # %entry ; CHECK-NEXT: .LBB26_12: # %entry
; CHECK-NEXT: sgtz a2, a2 ; CHECK-NEXT: sgtz a2, a2
; CHECK-NEXT: bnez a2, .LBB26_14 ; CHECK-NEXT: bnez a2, .LBB26_14
; CHECK-NEXT: .LBB26_13: # %entry ; CHECK-NEXT: .LBB26_13: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: .LBB26_14: # %entry ; CHECK-NEXT: .LBB26_14: # %entry
; CHECK-NEXT: bnez a1, .LBB26_16 ; CHECK-NEXT: bnez a1, .LBB26_16
; CHECK-NEXT: # %bb.15: # %entry ; CHECK-NEXT: # %bb.15: # %entry
; CHECK-NEXT: li s2, 0 ; CHECK-NEXT: li s0, 0
; CHECK-NEXT: .LBB26_16: # %entry ; CHECK-NEXT: .LBB26_16: # %entry
; CHECK-NEXT: mv a1, s2 ; CHECK-NEXT: mv a1, s0
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%conv = fptosi <2 x half> %x to <2 x i128> %conv = fptosi <2 x half> %x to <2 x i128>
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
define <4 x i32> @stest_f32i32_mm(<4 x float> %x) { define <4 x i32> @stest_f32i32_mm(<4 x float> %x) {
; CHECK-LABEL: stest_f32i32_mm: ; CHECK-LABEL: stest_f32i32_mm:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft1, a4 ; CHECK-NEXT: fmv.w.x ft1, a4
; CHECK-NEXT: fmv.w.x ft2, a3 ; CHECK-NEXT: fmv.w.x ft2, a3
; CHECK-NEXT: fmv.w.x ft0, a2 ; CHECK-NEXT: fmv.w.x ft0, a2
; CHECK-NEXT: fcvt.l.s a2, ft1, rtz ; CHECK-NEXT: fcvt.l.s a2, ft1, rtz
; CHECK-NEXT: lui a6, 524288 ; CHECK-NEXT: lui a4, 524288
; CHECK-NEXT: addiw a5, a6, -1 ; CHECK-NEXT: addiw a6, a4, -1
; CHECK-NEXT: fcvt.l.s a3, ft2, rtz ; CHECK-NEXT: fcvt.l.s a3, ft2, rtz
; CHECK-NEXT: blt a2, a5, .LBB30_2 ; CHECK-NEXT: blt a2, a6, .LBB30_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a2, a5 ; CHECK-NEXT: mv a2, a6
; CHECK-NEXT: .LBB30_2: # %entry ; CHECK-NEXT: .LBB30_2: # %entry
; CHECK-NEXT: fmv.w.x ft1, a1 ; CHECK-NEXT: fmv.w.x ft1, a1
; CHECK-NEXT: fcvt.l.s a1, ft0, rtz ; CHECK-NEXT: fcvt.l.s a1, ft0, rtz
; CHECK-NEXT: bge a3, a5, .LBB30_11 ; CHECK-NEXT: bge a3, a6, .LBB30_11
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: fcvt.l.s a4, ft1, rtz ; CHECK-NEXT: fcvt.l.s a5, ft1, rtz
; CHECK-NEXT: bge a1, a5, .LBB30_12 ; CHECK-NEXT: bge a1, a6, .LBB30_12
; CHECK-NEXT: .LBB30_4: # %entry ; CHECK-NEXT: .LBB30_4: # %entry
; CHECK-NEXT: bge a4, a5, .LBB30_13 ; CHECK-NEXT: bge a5, a6, .LBB30_13
; CHECK-NEXT: .LBB30_5: # %entry ; CHECK-NEXT: .LBB30_5: # %entry
; CHECK-NEXT: bge a6, a4, .LBB30_14 ; CHECK-NEXT: bge a4, a5, .LBB30_14
; CHECK-NEXT: .LBB30_6: # %entry ; CHECK-NEXT: .LBB30_6: # %entry
; CHECK-NEXT: bge a6, a1, .LBB30_15 ; CHECK-NEXT: bge a4, a1, .LBB30_15
; CHECK-NEXT: .LBB30_7: # %entry ; CHECK-NEXT: .LBB30_7: # %entry
; CHECK-NEXT: bge a6, a3, .LBB30_16 ; CHECK-NEXT: bge a4, a3, .LBB30_16
; CHECK-NEXT: .LBB30_8: # %entry ; CHECK-NEXT: .LBB30_8: # %entry
; CHECK-NEXT: blt a6, a2, .LBB30_10 ; CHECK-NEXT: blt a4, a2, .LBB30_10
; CHECK-NEXT: .LBB30_9: # %entry ; CHECK-NEXT: .LBB30_9: # %entry
; CHECK-NEXT: lui a2, 524288 ; CHECK-NEXT: lui a2, 524288
; CHECK-NEXT: .LBB30_10: # %entry ; CHECK-NEXT: .LBB30_10: # %entry
; CHECK-NEXT: sw a2, 12(a0) ; CHECK-NEXT: sw a2, 12(a0)
; CHECK-NEXT: sw a3, 8(a0) ; CHECK-NEXT: sw a3, 8(a0)
; CHECK-NEXT: sw a1, 4(a0) ; CHECK-NEXT: sw a1, 4(a0)
; CHECK-NEXT: sw a4, 0(a0) ; CHECK-NEXT: sw a5, 0(a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB30_11: # %entry ; CHECK-NEXT: .LBB30_11: # %entry
; CHECK-NEXT: mv a3, a5 ; CHECK-NEXT: mv a3, a6
; CHECK-NEXT: fcvt.l.s a4, ft1, rtz ; CHECK-NEXT: fcvt.l.s a5, ft1, rtz
; CHECK-NEXT: blt a1, a5, .LBB30_4 ; CHECK-NEXT: blt a1, a6, .LBB30_4
; CHECK-NEXT: .LBB30_12: # %entry ; CHECK-NEXT: .LBB30_12: # %entry
; CHECK-NEXT: mv a1, a5 ; CHECK-NEXT: mv a1, a6
; CHECK-NEXT: blt a4, a5, .LBB30_5 ; CHECK-NEXT: blt a5, a6, .LBB30_5
; CHECK-NEXT: .LBB30_13: # %entry ; CHECK-NEXT: .LBB30_13: # %entry
; CHECK-NEXT: mv a4, a5 ; CHECK-NEXT: mv a5, a6
; CHECK-NEXT: blt a6, a4, .LBB30_6 ; CHECK-NEXT: blt a4, a5, .LBB30_6
; CHECK-NEXT: .LBB30_14: # %entry ; CHECK-NEXT: .LBB30_14: # %entry
; CHECK-NEXT: lui a4, 524288 ; CHECK-NEXT: lui a5, 524288
; CHECK-NEXT: blt a6, a1, .LBB30_7 ; CHECK-NEXT: blt a4, a1, .LBB30_7
; CHECK-NEXT: .LBB30_15: # %entry ; CHECK-NEXT: .LBB30_15: # %entry
; CHECK-NEXT: lui a1, 524288 ; CHECK-NEXT: lui a1, 524288
; CHECK-NEXT: blt a6, a3, .LBB30_8 ; CHECK-NEXT: blt a4, a3, .LBB30_8
; CHECK-NEXT: .LBB30_16: # %entry ; CHECK-NEXT: .LBB30_16: # %entry
; CHECK-NEXT: lui a3, 524288 ; CHECK-NEXT: lui a3, 524288
; CHECK-NEXT: bge a6, a2, .LBB30_9 ; CHECK-NEXT: bge a4, a2, .LBB30_9
; CHECK-NEXT: j .LBB30_10 ; CHECK-NEXT: j .LBB30_10
entry: entry:
%conv = fptosi <4 x float> %x to <4 x i64> %conv = fptosi <4 x float> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>) %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)
%spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>) %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>)
%conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32> %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
ret <4 x i32> %conv6 ret <4 x i32> %conv6
} }
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; CHECK-NEXT: sd s4, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: .cfi_offset s3, -40 ; CHECK-NEXT: .cfi_offset s3, -40
; CHECK-NEXT: .cfi_offset s4, -48 ; CHECK-NEXT: .cfi_offset s4, -48
; CHECK-NEXT: lhu s2, 24(a1) ; CHECK-NEXT: lhu s2, 24(a1)
; CHECK-NEXT: lhu s4, 0(a1) ; CHECK-NEXT: lhu s1, 0(a1)
; CHECK-NEXT: lhu s0, 8(a1) ; CHECK-NEXT: lhu s3, 8(a1)
; CHECK-NEXT: lhu a1, 16(a1) ; CHECK-NEXT: lhu a1, 16(a1)
; CHECK-NEXT: mv s3, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: mv s4, a0
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s3
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s3, a0
; CHECK-NEXT: mv a0, s4 ; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s4, a0 ; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: fmv.w.x ft0, s0 ; CHECK-NEXT: fmv.w.x ft0, s3
; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill ; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: fmv.w.x ft0, s1 ; CHECK-NEXT: fmv.w.x ft0, s4
; CHECK-NEXT: fcvt.l.s s0, ft0, rtz ; CHECK-NEXT: fcvt.l.s s3, ft0, rtz
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: fcvt.l.s a0, ft0, rtz ; CHECK-NEXT: fcvt.l.s a0, ft0, rtz
; CHECK-NEXT: lui a1, 524288 ; CHECK-NEXT: lui a1, 524288
; CHECK-NEXT: addiw a4, a1, -1 ; CHECK-NEXT: addiw a4, a1, -1
; CHECK-NEXT: blt a0, a4, .LBB33_2 ; CHECK-NEXT: blt a0, a4, .LBB33_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a0, a4 ; CHECK-NEXT: mv a0, a4
; CHECK-NEXT: .LBB33_2: # %entry ; CHECK-NEXT: .LBB33_2: # %entry
; CHECK-NEXT: fmv.w.x ft0, s4 ; CHECK-NEXT: fmv.w.x ft0, s1
; CHECK-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload ; CHECK-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: fcvt.l.s a2, ft1, rtz ; CHECK-NEXT: fcvt.l.s a2, ft1, rtz
; CHECK-NEXT: bge s0, a4, .LBB33_11 ; CHECK-NEXT: bge s3, a4, .LBB33_11
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: fcvt.l.s a3, ft0, rtz ; CHECK-NEXT: fcvt.l.s a3, ft0, rtz
; CHECK-NEXT: bge a2, a4, .LBB33_12 ; CHECK-NEXT: bge a2, a4, .LBB33_12
; CHECK-NEXT: .LBB33_4: # %entry ; CHECK-NEXT: .LBB33_4: # %entry
; CHECK-NEXT: bge a3, a4, .LBB33_13 ; CHECK-NEXT: bge a3, a4, .LBB33_13
; CHECK-NEXT: .LBB33_5: # %entry ; CHECK-NEXT: .LBB33_5: # %entry
; CHECK-NEXT: bge a1, a3, .LBB33_14 ; CHECK-NEXT: bge a1, a3, .LBB33_14
; CHECK-NEXT: .LBB33_6: # %entry ; CHECK-NEXT: .LBB33_6: # %entry
; CHECK-NEXT: bge a1, a2, .LBB33_15 ; CHECK-NEXT: bge a1, a2, .LBB33_15
; CHECK-NEXT: .LBB33_7: # %entry ; CHECK-NEXT: .LBB33_7: # %entry
; CHECK-NEXT: bge a1, s0, .LBB33_16 ; CHECK-NEXT: bge a1, s3, .LBB33_16
; CHECK-NEXT: .LBB33_8: # %entry ; CHECK-NEXT: .LBB33_8: # %entry
; CHECK-NEXT: blt a1, a0, .LBB33_10 ; CHECK-NEXT: blt a1, a0, .LBB33_10
; CHECK-NEXT: .LBB33_9: # %entry ; CHECK-NEXT: .LBB33_9: # %entry
; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: .LBB33_10: # %entry ; CHECK-NEXT: .LBB33_10: # %entry
; CHECK-NEXT: sw a0, 12(s3) ; CHECK-NEXT: sw a0, 12(s0)
; CHECK-NEXT: sw s0, 8(s3) ; CHECK-NEXT: sw s3, 8(s0)
; CHECK-NEXT: sw a2, 4(s3) ; CHECK-NEXT: sw a2, 4(s0)
; CHECK-NEXT: sw a3, 0(s3) ; CHECK-NEXT: sw a3, 0(s0)
; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 32(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s3, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s4, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 64 ; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB33_11: # %entry ; CHECK-NEXT: .LBB33_11: # %entry
; CHECK-NEXT: mv s0, a4 ; CHECK-NEXT: mv s3, a4
; CHECK-NEXT: fcvt.l.s a3, ft0, rtz ; CHECK-NEXT: fcvt.l.s a3, ft0, rtz
; CHECK-NEXT: blt a2, a4, .LBB33_4 ; CHECK-NEXT: blt a2, a4, .LBB33_4
; CHECK-NEXT: .LBB33_12: # %entry ; CHECK-NEXT: .LBB33_12: # %entry
; CHECK-NEXT: mv a2, a4 ; CHECK-NEXT: mv a2, a4
; CHECK-NEXT: blt a3, a4, .LBB33_5 ; CHECK-NEXT: blt a3, a4, .LBB33_5
; CHECK-NEXT: .LBB33_13: # %entry ; CHECK-NEXT: .LBB33_13: # %entry
; CHECK-NEXT: mv a3, a4 ; CHECK-NEXT: mv a3, a4
; CHECK-NEXT: blt a1, a3, .LBB33_6 ; CHECK-NEXT: blt a1, a3, .LBB33_6
; CHECK-NEXT: .LBB33_14: # %entry ; CHECK-NEXT: .LBB33_14: # %entry
; CHECK-NEXT: lui a3, 524288 ; CHECK-NEXT: lui a3, 524288
; CHECK-NEXT: blt a1, a2, .LBB33_7 ; CHECK-NEXT: blt a1, a2, .LBB33_7
; CHECK-NEXT: .LBB33_15: # %entry ; CHECK-NEXT: .LBB33_15: # %entry
; CHECK-NEXT: lui a2, 524288 ; CHECK-NEXT: lui a2, 524288
; CHECK-NEXT: blt a1, s0, .LBB33_8 ; CHECK-NEXT: blt a1, s3, .LBB33_8
; CHECK-NEXT: .LBB33_16: # %entry ; CHECK-NEXT: .LBB33_16: # %entry
; CHECK-NEXT: lui s0, 524288 ; CHECK-NEXT: lui s3, 524288
; CHECK-NEXT: bge a1, a0, .LBB33_9 ; CHECK-NEXT: bge a1, a0, .LBB33_9
; CHECK-NEXT: j .LBB33_10 ; CHECK-NEXT: j .LBB33_10
entry: entry:
%conv = fptosi <4 x half> %x to <4 x i64> %conv = fptosi <4 x half> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>) %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)
%spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>) %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>)
%conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32> %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
ret <4 x i32> %conv6 ret <4 x i32> %conv6
Show All 12 Lines
; CHECK-NEXT: sd s4, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: .cfi_offset s3, -40 ; CHECK-NEXT: .cfi_offset s3, -40
; CHECK-NEXT: .cfi_offset s4, -48 ; CHECK-NEXT: .cfi_offset s4, -48
; CHECK-NEXT: lhu s2, 0(a1) ; CHECK-NEXT: lhu s2, 0(a1)
; CHECK-NEXT: lhu s3, 24(a1) ; CHECK-NEXT: lhu s1, 24(a1)
; CHECK-NEXT: lhu s1, 16(a1) ; CHECK-NEXT: lhu s3, 16(a1)
; CHECK-NEXT: lhu a1, 8(a1) ; CHECK-NEXT: lhu a1, 8(a1)
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s4, a0 ; CHECK-NEXT: mv s4, a0
; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: mv a0, s3 ; CHECK-NEXT: mv a0, s3
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s3, a0 ; CHECK-NEXT: mv s3, a0
; CHECK-NEXT: fmv.w.x ft0, s1 ; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: fmv.w.x ft0, s3
; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill ; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: fmv.w.x ft0, s4 ; CHECK-NEXT: fmv.w.x ft0, s4
; CHECK-NEXT: fcvt.lu.s s1, ft0, rtz ; CHECK-NEXT: fcvt.lu.s s3, ft0, rtz
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: fcvt.lu.s a0, ft0, rtz ; CHECK-NEXT: fcvt.lu.s a0, ft0, rtz
; CHECK-NEXT: li a1, -1 ; CHECK-NEXT: li a1, -1
; CHECK-NEXT: srli a1, a1, 32 ; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: bltu a0, a1, .LBB34_2 ; CHECK-NEXT: bltu a0, a1, .LBB34_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB34_2: # %entry ; CHECK-NEXT: .LBB34_2: # %entry
; CHECK-NEXT: fmv.w.x ft0, s3 ; CHECK-NEXT: fmv.w.x ft0, s1
; CHECK-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload ; CHECK-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: fcvt.lu.s a2, ft1, rtz ; CHECK-NEXT: fcvt.lu.s a2, ft1, rtz
; CHECK-NEXT: bgeu s1, a1, .LBB34_7 ; CHECK-NEXT: bgeu s3, a1, .LBB34_7
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: fcvt.lu.s a3, ft0, rtz ; CHECK-NEXT: fcvt.lu.s a3, ft0, rtz
; CHECK-NEXT: bgeu a2, a1, .LBB34_8 ; CHECK-NEXT: bgeu a2, a1, .LBB34_8
; CHECK-NEXT: .LBB34_4: # %entry ; CHECK-NEXT: .LBB34_4: # %entry
; CHECK-NEXT: bltu a3, a1, .LBB34_6 ; CHECK-NEXT: bltu a3, a1, .LBB34_6
; CHECK-NEXT: .LBB34_5: # %entry ; CHECK-NEXT: .LBB34_5: # %entry
; CHECK-NEXT: mv a3, a1 ; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: .LBB34_6: # %entry ; CHECK-NEXT: .LBB34_6: # %entry
; CHECK-NEXT: sw a3, 12(s0) ; CHECK-NEXT: sw a3, 12(s0)
; CHECK-NEXT: sw a2, 8(s0) ; CHECK-NEXT: sw a2, 8(s0)
; CHECK-NEXT: sw s1, 4(s0) ; CHECK-NEXT: sw s3, 4(s0)
; CHECK-NEXT: sw a0, 0(s0) ; CHECK-NEXT: sw a0, 0(s0)
; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 32(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s3, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s4, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 64 ; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB34_7: # %entry ; CHECK-NEXT: .LBB34_7: # %entry
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv s3, a1
; CHECK-NEXT: fcvt.lu.s a3, ft0, rtz ; CHECK-NEXT: fcvt.lu.s a3, ft0, rtz
; CHECK-NEXT: bltu a2, a1, .LBB34_4 ; CHECK-NEXT: bltu a2, a1, .LBB34_4
; CHECK-NEXT: .LBB34_8: # %entry ; CHECK-NEXT: .LBB34_8: # %entry
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bgeu a3, a1, .LBB34_5 ; CHECK-NEXT: bgeu a3, a1, .LBB34_5
; CHECK-NEXT: j .LBB34_6 ; CHECK-NEXT: j .LBB34_6
entry: entry:
%conv = fptoui <4 x half> %x to <4 x i64> %conv = fptoui <4 x half> %x to <4 x i64>
Show All 15 Lines
; CHECK-NEXT: sd s4, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: .cfi_offset s3, -40 ; CHECK-NEXT: .cfi_offset s3, -40
; CHECK-NEXT: .cfi_offset s4, -48 ; CHECK-NEXT: .cfi_offset s4, -48
; CHECK-NEXT: lhu s2, 24(a1) ; CHECK-NEXT: lhu s2, 24(a1)
; CHECK-NEXT: lhu s4, 0(a1) ; CHECK-NEXT: lhu s1, 0(a1)
; CHECK-NEXT: lhu s0, 8(a1) ; CHECK-NEXT: lhu s3, 8(a1)
; CHECK-NEXT: lhu a1, 16(a1) ; CHECK-NEXT: lhu a1, 16(a1)
; CHECK-NEXT: mv s3, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: mv s4, a0
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s3
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s3, a0
; CHECK-NEXT: mv a0, s4 ; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s4, a0 ; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: fmv.w.x ft0, s0 ; CHECK-NEXT: fmv.w.x ft0, s3
; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill ; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: fmv.w.x ft0, s1 ; CHECK-NEXT: fmv.w.x ft0, s4
; CHECK-NEXT: fcvt.l.s s0, ft0, rtz ; CHECK-NEXT: fcvt.l.s s3, ft0, rtz
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: fcvt.l.s a0, ft0, rtz ; CHECK-NEXT: fcvt.l.s a0, ft0, rtz
; CHECK-NEXT: li a1, -1 ; CHECK-NEXT: li a1, -1
; CHECK-NEXT: srli a3, a1, 32 ; CHECK-NEXT: srli a3, a1, 32
; CHECK-NEXT: blt a0, a3, .LBB35_2 ; CHECK-NEXT: blt a0, a3, .LBB35_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a0, a3 ; CHECK-NEXT: mv a0, a3
; CHECK-NEXT: .LBB35_2: # %entry ; CHECK-NEXT: .LBB35_2: # %entry
; CHECK-NEXT: fmv.w.x ft0, s4 ; CHECK-NEXT: fmv.w.x ft0, s1
; CHECK-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload ; CHECK-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: fcvt.l.s a1, ft1, rtz ; CHECK-NEXT: fcvt.l.s a1, ft1, rtz
; CHECK-NEXT: bge s0, a3, .LBB35_11 ; CHECK-NEXT: bge s3, a3, .LBB35_11
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: fcvt.l.s a2, ft0, rtz ; CHECK-NEXT: fcvt.l.s a2, ft0, rtz
; CHECK-NEXT: bge a1, a3, .LBB35_12 ; CHECK-NEXT: bge a1, a3, .LBB35_12
; CHECK-NEXT: .LBB35_4: # %entry ; CHECK-NEXT: .LBB35_4: # %entry
; CHECK-NEXT: bge a2, a3, .LBB35_13 ; CHECK-NEXT: bge a2, a3, .LBB35_13
; CHECK-NEXT: .LBB35_5: # %entry ; CHECK-NEXT: .LBB35_5: # %entry
; CHECK-NEXT: blez a2, .LBB35_14 ; CHECK-NEXT: blez a2, .LBB35_14
; CHECK-NEXT: .LBB35_6: # %entry ; CHECK-NEXT: .LBB35_6: # %entry
; CHECK-NEXT: blez a1, .LBB35_15 ; CHECK-NEXT: blez a1, .LBB35_15
; CHECK-NEXT: .LBB35_7: # %entry ; CHECK-NEXT: .LBB35_7: # %entry
; CHECK-NEXT: blez s0, .LBB35_16 ; CHECK-NEXT: blez s3, .LBB35_16
; CHECK-NEXT: .LBB35_8: # %entry ; CHECK-NEXT: .LBB35_8: # %entry
; CHECK-NEXT: bgtz a0, .LBB35_10 ; CHECK-NEXT: bgtz a0, .LBB35_10
; CHECK-NEXT: .LBB35_9: # %entry ; CHECK-NEXT: .LBB35_9: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: .LBB35_10: # %entry ; CHECK-NEXT: .LBB35_10: # %entry
; CHECK-NEXT: sw a0, 12(s3) ; CHECK-NEXT: sw a0, 12(s0)
; CHECK-NEXT: sw s0, 8(s3) ; CHECK-NEXT: sw s3, 8(s0)
; CHECK-NEXT: sw a1, 4(s3) ; CHECK-NEXT: sw a1, 4(s0)
; CHECK-NEXT: sw a2, 0(s3) ; CHECK-NEXT: sw a2, 0(s0)
; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 32(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s3, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s4, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 64 ; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB35_11: # %entry ; CHECK-NEXT: .LBB35_11: # %entry
; CHECK-NEXT: mv s0, a3 ; CHECK-NEXT: mv s3, a3
; CHECK-NEXT: fcvt.l.s a2, ft0, rtz ; CHECK-NEXT: fcvt.l.s a2, ft0, rtz
; CHECK-NEXT: blt a1, a3, .LBB35_4 ; CHECK-NEXT: blt a1, a3, .LBB35_4
; CHECK-NEXT: .LBB35_12: # %entry ; CHECK-NEXT: .LBB35_12: # %entry
; CHECK-NEXT: mv a1, a3 ; CHECK-NEXT: mv a1, a3
; CHECK-NEXT: blt a2, a3, .LBB35_5 ; CHECK-NEXT: blt a2, a3, .LBB35_5
; CHECK-NEXT: .LBB35_13: # %entry ; CHECK-NEXT: .LBB35_13: # %entry
; CHECK-NEXT: mv a2, a3 ; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: bgtz a2, .LBB35_6 ; CHECK-NEXT: bgtz a2, .LBB35_6
; CHECK-NEXT: .LBB35_14: # %entry ; CHECK-NEXT: .LBB35_14: # %entry
; CHECK-NEXT: li a2, 0 ; CHECK-NEXT: li a2, 0
; CHECK-NEXT: bgtz a1, .LBB35_7 ; CHECK-NEXT: bgtz a1, .LBB35_7
; CHECK-NEXT: .LBB35_15: # %entry ; CHECK-NEXT: .LBB35_15: # %entry
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: bgtz s0, .LBB35_8 ; CHECK-NEXT: bgtz s3, .LBB35_8
; CHECK-NEXT: .LBB35_16: # %entry ; CHECK-NEXT: .LBB35_16: # %entry
; CHECK-NEXT: li s0, 0 ; CHECK-NEXT: li s3, 0
; CHECK-NEXT: blez a0, .LBB35_9 ; CHECK-NEXT: blez a0, .LBB35_9
; CHECK-NEXT: j .LBB35_10 ; CHECK-NEXT: j .LBB35_10
entry: entry:
%conv = fptosi <4 x half> %x to <4 x i64> %conv = fptosi <4 x half> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>) %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
%spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> zeroinitializer) %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> zeroinitializer)
%conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32> %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
ret <4 x i32> %conv6 ret <4 x i32> %conv6
▲ Show 20 Lines • Show All 295 Lines • ▼ Show 20 Lines
; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 64(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 64(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s3, 56(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s3, 56(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s4, 48(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s4, 48(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s5, 40(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s5, 40(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s6, 32(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s6, 32(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s7, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s7, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s8, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s8, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s9, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: .cfi_offset s3, -40 ; CHECK-NEXT: .cfi_offset s3, -40
; CHECK-NEXT: .cfi_offset s4, -48 ; CHECK-NEXT: .cfi_offset s4, -48
; CHECK-NEXT: .cfi_offset s5, -56 ; CHECK-NEXT: .cfi_offset s5, -56
; CHECK-NEXT: .cfi_offset s6, -64 ; CHECK-NEXT: .cfi_offset s6, -64
; CHECK-NEXT: .cfi_offset s7, -72 ; CHECK-NEXT: .cfi_offset s7, -72
; CHECK-NEXT: .cfi_offset s8, -80 ; CHECK-NEXT: .cfi_offset s8, -80
; CHECK-NEXT: .cfi_offset s9, -88
; CHECK-NEXT: lhu s6, 56(a1) ; CHECK-NEXT: lhu s6, 56(a1)
; CHECK-NEXT: lhu s2, 0(a1) ; CHECK-NEXT: lhu s1, 0(a1)
; CHECK-NEXT: lhu s3, 8(a1) ; CHECK-NEXT: lhu s2, 8(a1)
; CHECK-NEXT: lhu s4, 16(a1) ; CHECK-NEXT: lhu s3, 16(a1)
; CHECK-NEXT: lhu s5, 24(a1) ; CHECK-NEXT: lhu s4, 24(a1)
; CHECK-NEXT: lhu s1, 32(a1) ; CHECK-NEXT: lhu s5, 32(a1)
; CHECK-NEXT: lhu s0, 40(a1) ; CHECK-NEXT: lhu s7, 40(a1)
; CHECK-NEXT: lhu a1, 48(a1) ; CHECK-NEXT: lhu a1, 48(a1)
; CHECK-NEXT: mv s8, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s9, a0 ; CHECK-NEXT: mv s8, a0
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s7
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s7, a0 ; CHECK-NEXT: mv s7, a0
; CHECK-NEXT: mv a0, s5 ; CHECK-NEXT: mv a0, s5
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s5, a0 ; CHECK-NEXT: mv s5, a0
; CHECK-NEXT: mv a0, s4 ; CHECK-NEXT: mv a0, s4
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s4, a0 ; CHECK-NEXT: mv s4, a0
; CHECK-NEXT: mv a0, s3 ; CHECK-NEXT: mv a0, s3
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s3, a0 ; CHECK-NEXT: mv s3, a0
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: fmv.w.x ft0, s0 ; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, s9 ; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: fcvt.l.s s9, ft0, rtz ; CHECK-NEXT: fmv.w.x ft0, s7
; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: fmv.w.x ft0, s8
; CHECK-NEXT: fcvt.l.s s7, ft0, rtz
; CHECK-NEXT: mv a0, s6 ; CHECK-NEXT: mv a0, s6
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: fcvt.l.s a0, ft0, rtz ; CHECK-NEXT: fcvt.l.s a0, ft0, rtz
; CHECK-NEXT: lui a1, 8 ; CHECK-NEXT: lui a1, 8
; CHECK-NEXT: addiw s1, a1, -1 ; CHECK-NEXT: addiw a7, a1, -1
; CHECK-NEXT: blt a0, s1, .LBB42_2 ; CHECK-NEXT: blt a0, a7, .LBB42_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a0, s1 ; CHECK-NEXT: mv a0, a7
; CHECK-NEXT: .LBB42_2: # %entry ; CHECK-NEXT: .LBB42_2: # %entry
; CHECK-NEXT: fmv.w.x ft1, s7 ; CHECK-NEXT: fmv.w.x ft1, s5
; CHECK-NEXT: flw ft0, 4(sp) # 4-byte Folded Reload ; CHECK-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: fcvt.l.s a1, ft0, rtz ; CHECK-NEXT: fcvt.l.s a1, ft0, rtz
; CHECK-NEXT: blt s9, s1, .LBB42_4 ; CHECK-NEXT: blt s7, a7, .LBB42_4
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: mv s9, s1 ; CHECK-NEXT: mv s7, a7
; CHECK-NEXT: .LBB42_4: # %entry ; CHECK-NEXT: .LBB42_4: # %entry
; CHECK-NEXT: fmv.w.x ft0, s5 ; CHECK-NEXT: fmv.w.x ft0, s4
; CHECK-NEXT: fcvt.l.s a2, ft1, rtz ; CHECK-NEXT: fcvt.l.s a2, ft1, rtz
; CHECK-NEXT: blt a1, s1, .LBB42_6 ; CHECK-NEXT: blt a1, a7, .LBB42_6
; CHECK-NEXT: # %bb.5: # %entry ; CHECK-NEXT: # %bb.5: # %entry
; CHECK-NEXT: mv a1, s1 ; CHECK-NEXT: mv a1, a7
; CHECK-NEXT: .LBB42_6: # %entry ; CHECK-NEXT: .LBB42_6: # %entry
; CHECK-NEXT: fmv.w.x ft1, s4 ; CHECK-NEXT: fmv.w.x ft1, s3
; CHECK-NEXT: fcvt.l.s a3, ft0, rtz ; CHECK-NEXT: fcvt.l.s a3, ft0, rtz
; CHECK-NEXT: blt a2, s1, .LBB42_8 ; CHECK-NEXT: blt a2, a7, .LBB42_8
; CHECK-NEXT: # %bb.7: # %entry ; CHECK-NEXT: # %bb.7: # %entry
; CHECK-NEXT: mv a2, s1 ; CHECK-NEXT: mv a2, a7
; CHECK-NEXT: .LBB42_8: # %entry ; CHECK-NEXT: .LBB42_8: # %entry
; CHECK-NEXT: fmv.w.x ft0, s3 ; CHECK-NEXT: fmv.w.x ft0, s2
; CHECK-NEXT: fcvt.l.s a4, ft1, rtz ; CHECK-NEXT: fcvt.l.s a4, ft1, rtz
; CHECK-NEXT: blt a3, s1, .LBB42_10 ; CHECK-NEXT: blt a3, a7, .LBB42_10
; CHECK-NEXT: # %bb.9: # %entry ; CHECK-NEXT: # %bb.9: # %entry
; CHECK-NEXT: mv a3, s1 ; CHECK-NEXT: mv a3, a7
; CHECK-NEXT: .LBB42_10: # %entry ; CHECK-NEXT: .LBB42_10: # %entry
; CHECK-NEXT: fmv.w.x ft1, s2 ; CHECK-NEXT: fmv.w.x ft1, s1
; CHECK-NEXT: fcvt.l.s a5, ft0, rtz ; CHECK-NEXT: fcvt.l.s a5, ft0, rtz
; CHECK-NEXT: bge a4, s1, .LBB42_23 ; CHECK-NEXT: bge a4, a7, .LBB42_23
; CHECK-NEXT: # %bb.11: # %entry ; CHECK-NEXT: # %bb.11: # %entry
; CHECK-NEXT: fcvt.l.s s0, ft1, rtz ; CHECK-NEXT: fcvt.l.s a6, ft1, rtz
; CHECK-NEXT: bge a5, s1, .LBB42_24 ; CHECK-NEXT: bge a5, a7, .LBB42_24
; CHECK-NEXT: .LBB42_12: # %entry ; CHECK-NEXT: .LBB42_12: # %entry
; CHECK-NEXT: bge s0, s1, .LBB42_25 ; CHECK-NEXT: bge a6, a7, .LBB42_25
; CHECK-NEXT: .LBB42_13: # %entry ; CHECK-NEXT: .LBB42_13: # %entry
; CHECK-NEXT: lui s1, 1048568 ; CHECK-NEXT: lui a7, 1048568
; CHECK-NEXT: bge s1, s0, .LBB42_26 ; CHECK-NEXT: bge a7, a6, .LBB42_26
; CHECK-NEXT: .LBB42_14: # %entry ; CHECK-NEXT: .LBB42_14: # %entry
; CHECK-NEXT: bge s1, a5, .LBB42_27 ; CHECK-NEXT: bge a7, a5, .LBB42_27
; CHECK-NEXT: .LBB42_15: # %entry ; CHECK-NEXT: .LBB42_15: # %entry
; CHECK-NEXT: bge s1, a4, .LBB42_28 ; CHECK-NEXT: bge a7, a4, .LBB42_28
; CHECK-NEXT: .LBB42_16: # %entry ; CHECK-NEXT: .LBB42_16: # %entry
; CHECK-NEXT: bge s1, a3, .LBB42_29 ; CHECK-NEXT: bge a7, a3, .LBB42_29
; CHECK-NEXT: .LBB42_17: # %entry ; CHECK-NEXT: .LBB42_17: # %entry
; CHECK-NEXT: bge s1, a2, .LBB42_30 ; CHECK-NEXT: bge a7, a2, .LBB42_30
; CHECK-NEXT: .LBB42_18: # %entry ; CHECK-NEXT: .LBB42_18: # %entry
; CHECK-NEXT: bge s1, a1, .LBB42_31 ; CHECK-NEXT: bge a7, a1, .LBB42_31
; CHECK-NEXT: .LBB42_19: # %entry ; CHECK-NEXT: .LBB42_19: # %entry
; CHECK-NEXT: bge s1, s9, .LBB42_32 ; CHECK-NEXT: bge a7, s7, .LBB42_32
; CHECK-NEXT: .LBB42_20: # %entry ; CHECK-NEXT: .LBB42_20: # %entry
; CHECK-NEXT: blt s1, a0, .LBB42_22 ; CHECK-NEXT: blt a7, a0, .LBB42_22
; CHECK-NEXT: .LBB42_21: # %entry ; CHECK-NEXT: .LBB42_21: # %entry
; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: .LBB42_22: # %entry ; CHECK-NEXT: .LBB42_22: # %entry
; CHECK-NEXT: sh a0, 14(s8) ; CHECK-NEXT: sh a0, 14(s0)
; CHECK-NEXT: sh s9, 12(s8) ; CHECK-NEXT: sh s7, 12(s0)
; CHECK-NEXT: sh a1, 10(s8) ; CHECK-NEXT: sh a1, 10(s0)
; CHECK-NEXT: sh a2, 8(s8) ; CHECK-NEXT: sh a2, 8(s0)
; CHECK-NEXT: sh a3, 6(s8) ; CHECK-NEXT: sh a3, 6(s0)
; CHECK-NEXT: sh a4, 4(s8) ; CHECK-NEXT: sh a4, 4(s0)
; CHECK-NEXT: sh a5, 2(s8) ; CHECK-NEXT: sh a5, 2(s0)
; CHECK-NEXT: sh s0, 0(s8) ; CHECK-NEXT: sh a6, 0(s0)
; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 80(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 72(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 72(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 64(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 64(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s3, 56(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s3, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s4, 48(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s4, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s5, 40(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s5, 40(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s6, 32(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s6, 32(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s7, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s7, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s8, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s8, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s9, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 96 ; CHECK-NEXT: addi sp, sp, 96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB42_23: # %entry ; CHECK-NEXT: .LBB42_23: # %entry
; CHECK-NEXT: mv a4, s1 ; CHECK-NEXT: mv a4, a7
; CHECK-NEXT: fcvt.l.s s0, ft1, rtz ; CHECK-NEXT: fcvt.l.s a6, ft1, rtz
; CHECK-NEXT: blt a5, s1, .LBB42_12 ; CHECK-NEXT: blt a5, a7, .LBB42_12
; CHECK-NEXT: .LBB42_24: # %entry ; CHECK-NEXT: .LBB42_24: # %entry
; CHECK-NEXT: mv a5, s1 ; CHECK-NEXT: mv a5, a7
; CHECK-NEXT: blt s0, s1, .LBB42_13 ; CHECK-NEXT: blt a6, a7, .LBB42_13
; CHECK-NEXT: .LBB42_25: # %entry ; CHECK-NEXT: .LBB42_25: # %entry
; CHECK-NEXT: mv s0, s1 ; CHECK-NEXT: mv a6, a7
; CHECK-NEXT: lui s1, 1048568 ; CHECK-NEXT: lui a7, 1048568
; CHECK-NEXT: blt s1, s0, .LBB42_14 ; CHECK-NEXT: blt a7, a6, .LBB42_14
; CHECK-NEXT: .LBB42_26: # %entry ; CHECK-NEXT: .LBB42_26: # %entry
; CHECK-NEXT: lui s0, 1048568 ; CHECK-NEXT: lui a6, 1048568
; CHECK-NEXT: blt s1, a5, .LBB42_15 ; CHECK-NEXT: blt a7, a5, .LBB42_15
; CHECK-NEXT: .LBB42_27: # %entry ; CHECK-NEXT: .LBB42_27: # %entry
; CHECK-NEXT: lui a5, 1048568 ; CHECK-NEXT: lui a5, 1048568
; CHECK-NEXT: blt s1, a4, .LBB42_16 ; CHECK-NEXT: blt a7, a4, .LBB42_16
; CHECK-NEXT: .LBB42_28: # %entry ; CHECK-NEXT: .LBB42_28: # %entry
; CHECK-NEXT: lui a4, 1048568 ; CHECK-NEXT: lui a4, 1048568
; CHECK-NEXT: blt s1, a3, .LBB42_17 ; CHECK-NEXT: blt a7, a3, .LBB42_17
; CHECK-NEXT: .LBB42_29: # %entry ; CHECK-NEXT: .LBB42_29: # %entry
; CHECK-NEXT: lui a3, 1048568 ; CHECK-NEXT: lui a3, 1048568
; CHECK-NEXT: blt s1, a2, .LBB42_18 ; CHECK-NEXT: blt a7, a2, .LBB42_18
; CHECK-NEXT: .LBB42_30: # %entry ; CHECK-NEXT: .LBB42_30: # %entry
; CHECK-NEXT: lui a2, 1048568 ; CHECK-NEXT: lui a2, 1048568
; CHECK-NEXT: blt s1, a1, .LBB42_19 ; CHECK-NEXT: blt a7, a1, .LBB42_19
; CHECK-NEXT: .LBB42_31: # %entry ; CHECK-NEXT: .LBB42_31: # %entry
; CHECK-NEXT: lui a1, 1048568 ; CHECK-NEXT: lui a1, 1048568
; CHECK-NEXT: blt s1, s9, .LBB42_20 ; CHECK-NEXT: blt a7, s7, .LBB42_20
; CHECK-NEXT: .LBB42_32: # %entry ; CHECK-NEXT: .LBB42_32: # %entry
; CHECK-NEXT: lui s9, 1048568 ; CHECK-NEXT: lui s7, 1048568
; CHECK-NEXT: bge s1, a0, .LBB42_21 ; CHECK-NEXT: bge a7, a0, .LBB42_21
; CHECK-NEXT: j .LBB42_22 ; CHECK-NEXT: j .LBB42_22
entry: entry:
%conv = fptosi <8 x half> %x to <8 x i32> %conv = fptosi <8 x half> %x to <8 x i32>
%spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>) %spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)
%spec.store.select7 = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %spec.store.select, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>) %spec.store.select7 = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %spec.store.select, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
%conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16> %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>
ret <8 x i16> %conv6 ret <8 x i16> %conv6
} }
define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) { define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) {
; CHECK-LABEL: utesth_f16i16_mm: ; CHECK-LABEL: utesth_f16i16_mm:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -96 ; CHECK-NEXT: addi sp, sp, -96
; CHECK-NEXT: .cfi_def_cfa_offset 96 ; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: sd ra, 88(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 88(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 80(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 80(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 64(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 64(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s3, 56(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s3, 56(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s4, 48(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s4, 48(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s5, 40(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s5, 40(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s6, 32(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s6, 32(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s7, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s7, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s8, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s8, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s9, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: .cfi_offset s3, -40 ; CHECK-NEXT: .cfi_offset s3, -40
; CHECK-NEXT: .cfi_offset s4, -48 ; CHECK-NEXT: .cfi_offset s4, -48
; CHECK-NEXT: .cfi_offset s5, -56 ; CHECK-NEXT: .cfi_offset s5, -56
; CHECK-NEXT: .cfi_offset s6, -64 ; CHECK-NEXT: .cfi_offset s6, -64
; CHECK-NEXT: .cfi_offset s7, -72 ; CHECK-NEXT: .cfi_offset s7, -72
; CHECK-NEXT: .cfi_offset s8, -80 ; CHECK-NEXT: .cfi_offset s8, -80
; CHECK-NEXT: .cfi_offset s9, -88
; CHECK-NEXT: lhu s5, 0(a1) ; CHECK-NEXT: lhu s5, 0(a1)
; CHECK-NEXT: lhu s2, 56(a1) ; CHECK-NEXT: lhu s1, 56(a1)
; CHECK-NEXT: lhu s3, 48(a1) ; CHECK-NEXT: lhu s2, 48(a1)
; CHECK-NEXT: lhu s4, 40(a1) ; CHECK-NEXT: lhu s3, 40(a1)
; CHECK-NEXT: lhu s6, 32(a1) ; CHECK-NEXT: lhu s4, 32(a1)
; CHECK-NEXT: lhu s7, 24(a1) ; CHECK-NEXT: lhu s6, 24(a1)
; CHECK-NEXT: lhu s1, 16(a1) ; CHECK-NEXT: lhu s7, 16(a1)
; CHECK-NEXT: lhu a1, 8(a1) ; CHECK-NEXT: lhu a1, 8(a1)
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s8, a0 ; CHECK-NEXT: mv s8, a0
; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s9, a0
; CHECK-NEXT: mv a0, s7 ; CHECK-NEXT: mv a0, s7
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s1, a0 ; CHECK-NEXT: mv s7, a0
; CHECK-NEXT: mv a0, s6 ; CHECK-NEXT: mv a0, s6
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s6, a0 ; CHECK-NEXT: mv s6, a0
; CHECK-NEXT: mv a0, s4 ; CHECK-NEXT: mv a0, s4
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s4, a0 ; CHECK-NEXT: mv s4, a0
; CHECK-NEXT: mv a0, s3 ; CHECK-NEXT: mv a0, s3
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s3, a0 ; CHECK-NEXT: mv s3, a0
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: fmv.w.x ft0, s1 ; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, s9 ; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: fcvt.lu.s s1, ft0, rtz ; CHECK-NEXT: fmv.w.x ft0, s6
; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: fmv.w.x ft0, s7
; CHECK-NEXT: fcvt.lu.s s7, ft0, rtz
; CHECK-NEXT: fmv.w.x ft0, s8 ; CHECK-NEXT: fmv.w.x ft0, s8
; CHECK-NEXT: fcvt.lu.s a0, ft0, rtz ; CHECK-NEXT: fcvt.lu.s a0, ft0, rtz
; CHECK-NEXT: sext.w s7, a0 ; CHECK-NEXT: sext.w s6, a0
; CHECK-NEXT: mv a0, s5 ; CHECK-NEXT: mv a0, s5
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: fcvt.lu.s a0, ft0, rtz ; CHECK-NEXT: fcvt.lu.s a0, ft0, rtz
; CHECK-NEXT: sext.w a6, a0 ; CHECK-NEXT: sext.w a0, a0
; CHECK-NEXT: lui a0, 16 ; CHECK-NEXT: lui a1, 16
; CHECK-NEXT: addiw a1, a0, -1 ; CHECK-NEXT: addiw a1, a1, -1
; CHECK-NEXT: bltu a6, a1, .LBB43_2 ; CHECK-NEXT: bltu a0, a1, .LBB43_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a6, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: .LBB43_2: # %entry ; CHECK-NEXT: .LBB43_2: # %entry
; CHECK-NEXT: fmv.w.x ft0, s6 ; CHECK-NEXT: fmv.w.x ft0, s4
; CHECK-NEXT: flw ft1, 4(sp) # 4-byte Folded Reload ; CHECK-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: fcvt.lu.s a0, ft1, rtz ; CHECK-NEXT: fcvt.lu.s a3, ft1, rtz
; CHECK-NEXT: sext.w a2, s1 ; CHECK-NEXT: sext.w a2, s7
; CHECK-NEXT: bltu s7, a1, .LBB43_4 ; CHECK-NEXT: bltu s6, a1, .LBB43_4
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: mv s7, a1 ; CHECK-NEXT: mv s6, a1
; CHECK-NEXT: .LBB43_4: # %entry ; CHECK-NEXT: .LBB43_4: # %entry
; CHECK-NEXT: fmv.w.x ft1, s4 ; CHECK-NEXT: fmv.w.x ft1, s3
; CHECK-NEXT: fcvt.lu.s a4, ft0, rtz ; CHECK-NEXT: fcvt.lu.s a4, ft0, rtz
; CHECK-NEXT: sext.w a3, a0 ; CHECK-NEXT: sext.w a3, a3
; CHECK-NEXT: bltu a2, a1, .LBB43_6 ; CHECK-NEXT: bltu a2, a1, .LBB43_6
; CHECK-NEXT: # %bb.5: # %entry ; CHECK-NEXT: # %bb.5: # %entry
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB43_6: # %entry ; CHECK-NEXT: .LBB43_6: # %entry
; CHECK-NEXT: fmv.w.x ft0, s3 ; CHECK-NEXT: fmv.w.x ft0, s2
; CHECK-NEXT: fcvt.lu.s a0, ft1, rtz ; CHECK-NEXT: fcvt.lu.s a5, ft1, rtz
; CHECK-NEXT: sext.w a4, a4 ; CHECK-NEXT: sext.w a4, a4
; CHECK-NEXT: bltu a3, a1, .LBB43_8 ; CHECK-NEXT: bltu a3, a1, .LBB43_8
; CHECK-NEXT: # %bb.7: # %entry ; CHECK-NEXT: # %bb.7: # %entry
; CHECK-NEXT: mv a3, a1 ; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: .LBB43_8: # %entry ; CHECK-NEXT: .LBB43_8: # %entry
; CHECK-NEXT: fmv.w.x ft1, s2 ; CHECK-NEXT: fmv.w.x ft1, s1
; CHECK-NEXT: fcvt.lu.s s1, ft0, rtz ; CHECK-NEXT: fcvt.lu.s a6, ft0, rtz
; CHECK-NEXT: sext.w a5, a0 ; CHECK-NEXT: sext.w a5, a5
; CHECK-NEXT: bltu a4, a1, .LBB43_10 ; CHECK-NEXT: bltu a4, a1, .LBB43_10
; CHECK-NEXT: # %bb.9: # %entry ; CHECK-NEXT: # %bb.9: # %entry
; CHECK-NEXT: mv a4, a1 ; CHECK-NEXT: mv a4, a1
; CHECK-NEXT: .LBB43_10: # %entry ; CHECK-NEXT: .LBB43_10: # %entry
; CHECK-NEXT: fcvt.lu.s a0, ft1, rtz ; CHECK-NEXT: fcvt.lu.s a7, ft1, rtz
; CHECK-NEXT: sext.w s1, s1 ; CHECK-NEXT: sext.w a6, a6
; CHECK-NEXT: bgeu a5, a1, .LBB43_15 ; CHECK-NEXT: bgeu a5, a1, .LBB43_15
; CHECK-NEXT: # %bb.11: # %entry ; CHECK-NEXT: # %bb.11: # %entry
; CHECK-NEXT: sext.w a0, a0 ; CHECK-NEXT: sext.w a7, a7
; CHECK-NEXT: bgeu s1, a1, .LBB43_16 ; CHECK-NEXT: bgeu a6, a1, .LBB43_16
; CHECK-NEXT: .LBB43_12: # %entry ; CHECK-NEXT: .LBB43_12: # %entry
; CHECK-NEXT: bltu a0, a1, .LBB43_14 ; CHECK-NEXT: bltu a7, a1, .LBB43_14
; CHECK-NEXT: .LBB43_13: # %entry ; CHECK-NEXT: .LBB43_13: # %entry
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a7, a1
; CHECK-NEXT: .LBB43_14: # %entry ; CHECK-NEXT: .LBB43_14: # %entry
; CHECK-NEXT: sh a0, 14(s0) ; CHECK-NEXT: sh a7, 14(s0)
; CHECK-NEXT: sh s1, 12(s0) ; CHECK-NEXT: sh a6, 12(s0)
; CHECK-NEXT: sh a5, 10(s0) ; CHECK-NEXT: sh a5, 10(s0)
; CHECK-NEXT: sh a4, 8(s0) ; CHECK-NEXT: sh a4, 8(s0)
; CHECK-NEXT: sh a3, 6(s0) ; CHECK-NEXT: sh a3, 6(s0)
; CHECK-NEXT: sh a2, 4(s0) ; CHECK-NEXT: sh a2, 4(s0)
; CHECK-NEXT: sh s7, 2(s0) ; CHECK-NEXT: sh s6, 2(s0)
; CHECK-NEXT: sh a6, 0(s0) ; CHECK-NEXT: sh a0, 0(s0)
; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 80(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 72(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 72(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 64(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 64(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s3, 56(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s3, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s4, 48(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s4, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s5, 40(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s5, 40(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s6, 32(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s6, 32(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s7, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s7, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s8, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s8, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s9, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 96 ; CHECK-NEXT: addi sp, sp, 96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB43_15: # %entry ; CHECK-NEXT: .LBB43_15: # %entry
; CHECK-NEXT: mv a5, a1 ; CHECK-NEXT: mv a5, a1
; CHECK-NEXT: sext.w a0, a0 ; CHECK-NEXT: sext.w a7, a7
; CHECK-NEXT: bltu s1, a1, .LBB43_12 ; CHECK-NEXT: bltu a6, a1, .LBB43_12
; CHECK-NEXT: .LBB43_16: # %entry ; CHECK-NEXT: .LBB43_16: # %entry
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv a6, a1
; CHECK-NEXT: bgeu a0, a1, .LBB43_13 ; CHECK-NEXT: bgeu a7, a1, .LBB43_13
; CHECK-NEXT: j .LBB43_14 ; CHECK-NEXT: j .LBB43_14
entry: entry:
%conv = fptoui <8 x half> %x to <8 x i32> %conv = fptoui <8 x half> %x to <8 x i32>
%spec.store.select = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>) %spec.store.select = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)
%conv6 = trunc <8 x i32> %spec.store.select to <8 x i16> %conv6 = trunc <8 x i32> %spec.store.select to <8 x i16>
ret <8 x i16> %conv6 ret <8 x i16> %conv6
} }
define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) { define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) {
; CHECK-LABEL: ustest_f16i16_mm: ; CHECK-LABEL: ustest_f16i16_mm:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -96 ; CHECK-NEXT: addi sp, sp, -96
; CHECK-NEXT: .cfi_def_cfa_offset 96 ; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: sd ra, 88(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 88(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 80(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 80(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 64(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 64(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s3, 56(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s3, 56(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s4, 48(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s4, 48(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s5, 40(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s5, 40(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s6, 32(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s6, 32(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s7, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s7, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s8, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s8, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s9, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: .cfi_offset s3, -40 ; CHECK-NEXT: .cfi_offset s3, -40
; CHECK-NEXT: .cfi_offset s4, -48 ; CHECK-NEXT: .cfi_offset s4, -48
; CHECK-NEXT: .cfi_offset s5, -56 ; CHECK-NEXT: .cfi_offset s5, -56
; CHECK-NEXT: .cfi_offset s6, -64 ; CHECK-NEXT: .cfi_offset s6, -64
; CHECK-NEXT: .cfi_offset s7, -72 ; CHECK-NEXT: .cfi_offset s7, -72
; CHECK-NEXT: .cfi_offset s8, -80 ; CHECK-NEXT: .cfi_offset s8, -80
; CHECK-NEXT: .cfi_offset s9, -88
; CHECK-NEXT: lhu s6, 56(a1) ; CHECK-NEXT: lhu s6, 56(a1)
; CHECK-NEXT: lhu s2, 0(a1) ; CHECK-NEXT: lhu s1, 0(a1)
; CHECK-NEXT: lhu s3, 8(a1) ; CHECK-NEXT: lhu s2, 8(a1)
; CHECK-NEXT: lhu s4, 16(a1) ; CHECK-NEXT: lhu s3, 16(a1)
; CHECK-NEXT: lhu s5, 24(a1) ; CHECK-NEXT: lhu s4, 24(a1)
; CHECK-NEXT: lhu s1, 32(a1) ; CHECK-NEXT: lhu s5, 32(a1)
; CHECK-NEXT: lhu s0, 40(a1) ; CHECK-NEXT: lhu s7, 40(a1)
; CHECK-NEXT: lhu a1, 48(a1) ; CHECK-NEXT: lhu a1, 48(a1)
; CHECK-NEXT: mv s8, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s9, a0 ; CHECK-NEXT: mv s8, a0
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s7
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s7, a0 ; CHECK-NEXT: mv s7, a0
; CHECK-NEXT: mv a0, s5 ; CHECK-NEXT: mv a0, s5
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s5, a0 ; CHECK-NEXT: mv s5, a0
; CHECK-NEXT: mv a0, s4 ; CHECK-NEXT: mv a0, s4
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s4, a0 ; CHECK-NEXT: mv s4, a0
; CHECK-NEXT: mv a0, s3 ; CHECK-NEXT: mv a0, s3
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s3, a0 ; CHECK-NEXT: mv s3, a0
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: fmv.w.x ft0, s0 ; CHECK-NEXT: mv a0, s1
; CHECK-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, s9 ; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: fcvt.l.s s9, ft0, rtz ; CHECK-NEXT: fmv.w.x ft0, s7
; CHECK-NEXT: fsw ft0, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: fmv.w.x ft0, s8
; CHECK-NEXT: fcvt.l.s s7, ft0, rtz
; CHECK-NEXT: mv a0, s6 ; CHECK-NEXT: mv a0, s6
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: fcvt.l.s a0, ft0, rtz ; CHECK-NEXT: fcvt.l.s a0, ft0, rtz
; CHECK-NEXT: lui a1, 16 ; CHECK-NEXT: lui a1, 16
; CHECK-NEXT: addiw s1, a1, -1 ; CHECK-NEXT: addiw a7, a1, -1
; CHECK-NEXT: blt a0, s1, .LBB44_2 ; CHECK-NEXT: blt a0, a7, .LBB44_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a0, s1 ; CHECK-NEXT: mv a0, a7
; CHECK-NEXT: .LBB44_2: # %entry ; CHECK-NEXT: .LBB44_2: # %entry
; CHECK-NEXT: fmv.w.x ft1, s7 ; CHECK-NEXT: fmv.w.x ft1, s5
; CHECK-NEXT: flw ft0, 4(sp) # 4-byte Folded Reload ; CHECK-NEXT: flw ft0, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: fcvt.l.s a1, ft0, rtz ; CHECK-NEXT: fcvt.l.s a1, ft0, rtz
; CHECK-NEXT: blt s9, s1, .LBB44_4 ; CHECK-NEXT: blt s7, a7, .LBB44_4
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: mv s9, s1 ; CHECK-NEXT: mv s7, a7
; CHECK-NEXT: .LBB44_4: # %entry ; CHECK-NEXT: .LBB44_4: # %entry
; CHECK-NEXT: fmv.w.x ft0, s5 ; CHECK-NEXT: fmv.w.x ft0, s4
; CHECK-NEXT: fcvt.l.s a2, ft1, rtz ; CHECK-NEXT: fcvt.l.s a2, ft1, rtz
; CHECK-NEXT: blt a1, s1, .LBB44_6 ; CHECK-NEXT: blt a1, a7, .LBB44_6
; CHECK-NEXT: # %bb.5: # %entry ; CHECK-NEXT: # %bb.5: # %entry
; CHECK-NEXT: mv a1, s1 ; CHECK-NEXT: mv a1, a7
; CHECK-NEXT: .LBB44_6: # %entry ; CHECK-NEXT: .LBB44_6: # %entry
; CHECK-NEXT: fmv.w.x ft1, s4 ; CHECK-NEXT: fmv.w.x ft1, s3
; CHECK-NEXT: fcvt.l.s a3, ft0, rtz ; CHECK-NEXT: fcvt.l.s a3, ft0, rtz
; CHECK-NEXT: blt a2, s1, .LBB44_8 ; CHECK-NEXT: blt a2, a7, .LBB44_8
; CHECK-NEXT: # %bb.7: # %entry ; CHECK-NEXT: # %bb.7: # %entry
; CHECK-NEXT: mv a2, s1 ; CHECK-NEXT: mv a2, a7
; CHECK-NEXT: .LBB44_8: # %entry ; CHECK-NEXT: .LBB44_8: # %entry
; CHECK-NEXT: fmv.w.x ft0, s3 ; CHECK-NEXT: fmv.w.x ft0, s2
; CHECK-NEXT: fcvt.l.s a4, ft1, rtz ; CHECK-NEXT: fcvt.l.s a4, ft1, rtz
; CHECK-NEXT: blt a3, s1, .LBB44_10 ; CHECK-NEXT: blt a3, a7, .LBB44_10
; CHECK-NEXT: # %bb.9: # %entry ; CHECK-NEXT: # %bb.9: # %entry
; CHECK-NEXT: mv a3, s1 ; CHECK-NEXT: mv a3, a7
; CHECK-NEXT: .LBB44_10: # %entry ; CHECK-NEXT: .LBB44_10: # %entry
; CHECK-NEXT: fmv.w.x ft1, s2 ; CHECK-NEXT: fmv.w.x ft1, s1
; CHECK-NEXT: fcvt.l.s a5, ft0, rtz ; CHECK-NEXT: fcvt.l.s a5, ft0, rtz
; CHECK-NEXT: bge a4, s1, .LBB44_23 ; CHECK-NEXT: bge a4, a7, .LBB44_23
; CHECK-NEXT: # %bb.11: # %entry ; CHECK-NEXT: # %bb.11: # %entry
; CHECK-NEXT: fcvt.l.s s0, ft1, rtz ; CHECK-NEXT: fcvt.l.s a6, ft1, rtz
; CHECK-NEXT: bge a5, s1, .LBB44_24 ; CHECK-NEXT: bge a5, a7, .LBB44_24
; CHECK-NEXT: .LBB44_12: # %entry ; CHECK-NEXT: .LBB44_12: # %entry
; CHECK-NEXT: bge s0, s1, .LBB44_25 ; CHECK-NEXT: bge a6, a7, .LBB44_25
; CHECK-NEXT: .LBB44_13: # %entry ; CHECK-NEXT: .LBB44_13: # %entry
; CHECK-NEXT: blez s0, .LBB44_26 ; CHECK-NEXT: blez a6, .LBB44_26
; CHECK-NEXT: .LBB44_14: # %entry ; CHECK-NEXT: .LBB44_14: # %entry
; CHECK-NEXT: blez a5, .LBB44_27 ; CHECK-NEXT: blez a5, .LBB44_27
; CHECK-NEXT: .LBB44_15: # %entry ; CHECK-NEXT: .LBB44_15: # %entry
; CHECK-NEXT: blez a4, .LBB44_28 ; CHECK-NEXT: blez a4, .LBB44_28
; CHECK-NEXT: .LBB44_16: # %entry ; CHECK-NEXT: .LBB44_16: # %entry
; CHECK-NEXT: blez a3, .LBB44_29 ; CHECK-NEXT: blez a3, .LBB44_29
; CHECK-NEXT: .LBB44_17: # %entry ; CHECK-NEXT: .LBB44_17: # %entry
; CHECK-NEXT: blez a2, .LBB44_30 ; CHECK-NEXT: blez a2, .LBB44_30
; CHECK-NEXT: .LBB44_18: # %entry ; CHECK-NEXT: .LBB44_18: # %entry
; CHECK-NEXT: blez a1, .LBB44_31 ; CHECK-NEXT: blez a1, .LBB44_31
; CHECK-NEXT: .LBB44_19: # %entry ; CHECK-NEXT: .LBB44_19: # %entry
; CHECK-NEXT: blez s9, .LBB44_32 ; CHECK-NEXT: blez s7, .LBB44_32
; CHECK-NEXT: .LBB44_20: # %entry ; CHECK-NEXT: .LBB44_20: # %entry
; CHECK-NEXT: bgtz a0, .LBB44_22 ; CHECK-NEXT: bgtz a0, .LBB44_22
; CHECK-NEXT: .LBB44_21: # %entry ; CHECK-NEXT: .LBB44_21: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: .LBB44_22: # %entry ; CHECK-NEXT: .LBB44_22: # %entry
; CHECK-NEXT: sh a0, 14(s8) ; CHECK-NEXT: sh a0, 14(s0)
; CHECK-NEXT: sh s9, 12(s8) ; CHECK-NEXT: sh s7, 12(s0)
; CHECK-NEXT: sh a1, 10(s8) ; CHECK-NEXT: sh a1, 10(s0)
; CHECK-NEXT: sh a2, 8(s8) ; CHECK-NEXT: sh a2, 8(s0)
; CHECK-NEXT: sh a3, 6(s8) ; CHECK-NEXT: sh a3, 6(s0)
; CHECK-NEXT: sh a4, 4(s8) ; CHECK-NEXT: sh a4, 4(s0)
; CHECK-NEXT: sh a5, 2(s8) ; CHECK-NEXT: sh a5, 2(s0)
; CHECK-NEXT: sh s0, 0(s8) ; CHECK-NEXT: sh a6, 0(s0)
; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 80(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 80(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 72(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 72(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 64(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 64(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s3, 56(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s3, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s4, 48(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s4, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s5, 40(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s5, 40(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s6, 32(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s6, 32(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s7, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s7, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s8, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s8, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s9, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 96 ; CHECK-NEXT: addi sp, sp, 96
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB44_23: # %entry ; CHECK-NEXT: .LBB44_23: # %entry
; CHECK-NEXT: mv a4, s1 ; CHECK-NEXT: mv a4, a7
; CHECK-NEXT: fcvt.l.s s0, ft1, rtz ; CHECK-NEXT: fcvt.l.s a6, ft1, rtz
; CHECK-NEXT: blt a5, s1, .LBB44_12 ; CHECK-NEXT: blt a5, a7, .LBB44_12
; CHECK-NEXT: .LBB44_24: # %entry ; CHECK-NEXT: .LBB44_24: # %entry
; CHECK-NEXT: mv a5, s1 ; CHECK-NEXT: mv a5, a7
; CHECK-NEXT: blt s0, s1, .LBB44_13 ; CHECK-NEXT: blt a6, a7, .LBB44_13
; CHECK-NEXT: .LBB44_25: # %entry ; CHECK-NEXT: .LBB44_25: # %entry
; CHECK-NEXT: mv s0, s1 ; CHECK-NEXT: mv a6, a7
; CHECK-NEXT: bgtz s0, .LBB44_14 ; CHECK-NEXT: bgtz a6, .LBB44_14
; CHECK-NEXT: .LBB44_26: # %entry ; CHECK-NEXT: .LBB44_26: # %entry
; CHECK-NEXT: li s0, 0 ; CHECK-NEXT: li a6, 0
; CHECK-NEXT: bgtz a5, .LBB44_15 ; CHECK-NEXT: bgtz a5, .LBB44_15
; CHECK-NEXT: .LBB44_27: # %entry ; CHECK-NEXT: .LBB44_27: # %entry
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: bgtz a4, .LBB44_16 ; CHECK-NEXT: bgtz a4, .LBB44_16
; CHECK-NEXT: .LBB44_28: # %entry ; CHECK-NEXT: .LBB44_28: # %entry
; CHECK-NEXT: li a4, 0 ; CHECK-NEXT: li a4, 0
; CHECK-NEXT: bgtz a3, .LBB44_17 ; CHECK-NEXT: bgtz a3, .LBB44_17
; CHECK-NEXT: .LBB44_29: # %entry ; CHECK-NEXT: .LBB44_29: # %entry
; CHECK-NEXT: li a3, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: bgtz a2, .LBB44_18 ; CHECK-NEXT: bgtz a2, .LBB44_18
; CHECK-NEXT: .LBB44_30: # %entry ; CHECK-NEXT: .LBB44_30: # %entry
; CHECK-NEXT: li a2, 0 ; CHECK-NEXT: li a2, 0
; CHECK-NEXT: bgtz a1, .LBB44_19 ; CHECK-NEXT: bgtz a1, .LBB44_19
; CHECK-NEXT: .LBB44_31: # %entry ; CHECK-NEXT: .LBB44_31: # %entry
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: bgtz s9, .LBB44_20 ; CHECK-NEXT: bgtz s7, .LBB44_20
; CHECK-NEXT: .LBB44_32: # %entry ; CHECK-NEXT: .LBB44_32: # %entry
; CHECK-NEXT: li s9, 0 ; CHECK-NEXT: li s7, 0
; CHECK-NEXT: blez a0, .LBB44_21 ; CHECK-NEXT: blez a0, .LBB44_21
; CHECK-NEXT: j .LBB44_22 ; CHECK-NEXT: j .LBB44_22
entry: entry:
%conv = fptosi <8 x half> %x to <8 x i32> %conv = fptosi <8 x half> %x to <8 x i32>
%spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>) %spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)
%spec.store.select7 = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %spec.store.select, <8 x i32> zeroinitializer) %spec.store.select7 = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %spec.store.select, <8 x i32> zeroinitializer)
%conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16> %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>
ret <8 x i16> %conv6 ret <8 x i16> %conv6
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; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __fixunsdfti@plt ; CHECK-NEXT: call __fixunsdfti@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv s1, a1
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __fixunsdfti@plt ; CHECK-NEXT: call __fixunsdfti@plt
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: mv a3, a1 ; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: beqz a3, .LBB46_2 ; CHECK-NEXT: beqz a3, .LBB46_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB46_2: # %entry ; CHECK-NEXT: .LBB46_2: # %entry
; CHECK-NEXT: li a4, 1 ; CHECK-NEXT: li a4, 1
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: bne a3, a4, .LBB46_7 ; CHECK-NEXT: bne a3, a4, .LBB46_7
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: bne s1, a1, .LBB46_8 ; CHECK-NEXT: bne s1, a1, .LBB46_8
; CHECK-NEXT: .LBB46_4: # %entry ; CHECK-NEXT: .LBB46_4: # %entry
; CHECK-NEXT: beq s1, a4, .LBB46_6 ; CHECK-NEXT: beq s1, a4, .LBB46_6
; CHECK-NEXT: .LBB46_5: # %entry ; CHECK-NEXT: .LBB46_5: # %entry
; CHECK-NEXT: mv a1, s2 ; CHECK-NEXT: mv a1, s0
; CHECK-NEXT: .LBB46_6: # %entry ; CHECK-NEXT: .LBB46_6: # %entry
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB46_7: # %entry ; CHECK-NEXT: .LBB46_7: # %entry
; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: beq s1, a1, .LBB46_4 ; CHECK-NEXT: beq s1, a1, .LBB46_4
; CHECK-NEXT: .LBB46_8: # %entry ; CHECK-NEXT: .LBB46_8: # %entry
; CHECK-NEXT: mv s2, a1 ; CHECK-NEXT: mv s0, a1
; CHECK-NEXT: bne s1, a4, .LBB46_5 ; CHECK-NEXT: bne s1, a4, .LBB46_5
; CHECK-NEXT: j .LBB46_6 ; CHECK-NEXT: j .LBB46_6
entry: entry:
%conv = fptoui <2 x double> %x to <2 x i128> %conv = fptoui <2 x double> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>) %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
%conv6 = trunc <2 x i128> %spec.store.select to <2 x i64> %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
ret <2 x i64> %conv6 ret <2 x i64> %conv6
} }
define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) {
; CHECK-LABEL: ustest_f64i64_mm: ; CHECK-LABEL: ustest_f64i64_mm:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -32 ; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s0, a1 ; CHECK-NEXT: mv s2, a1
; CHECK-NEXT: call __fixdfti@plt ; CHECK-NEXT: call __fixdfti@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv s1, a1
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __fixdfti@plt ; CHECK-NEXT: call __fixdfti@plt
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: li a5, 1 ; CHECK-NEXT: li a5, 1
; CHECK-NEXT: mv a3, a1 ; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: bgtz a1, .LBB47_12 ; CHECK-NEXT: bgtz a1, .LBB47_12
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a4, s1 ; CHECK-NEXT: mv a4, s1
; CHECK-NEXT: bgtz s1, .LBB47_13 ; CHECK-NEXT: bgtz s1, .LBB47_13
Show All 36 Lines
; CHECK-NEXT: .LBB47_14: # %entry ; CHECK-NEXT: .LBB47_14: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: beq a2, a5, .LBB47_4 ; CHECK-NEXT: beq a2, a5, .LBB47_4
; CHECK-NEXT: .LBB47_15: # %entry ; CHECK-NEXT: .LBB47_15: # %entry
; CHECK-NEXT: mv a1, a0 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: blez s1, .LBB47_5 ; CHECK-NEXT: blez s1, .LBB47_5
; CHECK-NEXT: .LBB47_16: # %entry ; CHECK-NEXT: .LBB47_16: # %entry
; CHECK-NEXT: li s2, 0 ; CHECK-NEXT: li s0, 0
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: beq s1, a5, .LBB47_6 ; CHECK-NEXT: beq s1, a5, .LBB47_6
; CHECK-NEXT: .LBB47_17: # %entry ; CHECK-NEXT: .LBB47_17: # %entry
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s0
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: bgtz a4, .LBB47_7 ; CHECK-NEXT: bgtz a4, .LBB47_7
; CHECK-NEXT: .LBB47_18: # %entry ; CHECK-NEXT: .LBB47_18: # %entry
; CHECK-NEXT: li a2, 0 ; CHECK-NEXT: li a2, 0
; CHECK-NEXT: beqz a4, .LBB47_8 ; CHECK-NEXT: beqz a4, .LBB47_8
; CHECK-NEXT: .LBB47_19: # %entry ; CHECK-NEXT: .LBB47_19: # %entry
; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
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; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __fixunssfti@plt ; CHECK-NEXT: call __fixunssfti@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv s1, a1
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __fixunssfti@plt ; CHECK-NEXT: call __fixunssfti@plt
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: mv a3, a1 ; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: beqz a3, .LBB49_2 ; CHECK-NEXT: beqz a3, .LBB49_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB49_2: # %entry ; CHECK-NEXT: .LBB49_2: # %entry
; CHECK-NEXT: li a4, 1 ; CHECK-NEXT: li a4, 1
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: bne a3, a4, .LBB49_7 ; CHECK-NEXT: bne a3, a4, .LBB49_7
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: bne s1, a1, .LBB49_8 ; CHECK-NEXT: bne s1, a1, .LBB49_8
; CHECK-NEXT: .LBB49_4: # %entry ; CHECK-NEXT: .LBB49_4: # %entry
; CHECK-NEXT: beq s1, a4, .LBB49_6 ; CHECK-NEXT: beq s1, a4, .LBB49_6
; CHECK-NEXT: .LBB49_5: # %entry ; CHECK-NEXT: .LBB49_5: # %entry
; CHECK-NEXT: mv a1, s2 ; CHECK-NEXT: mv a1, s0
; CHECK-NEXT: .LBB49_6: # %entry ; CHECK-NEXT: .LBB49_6: # %entry
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB49_7: # %entry ; CHECK-NEXT: .LBB49_7: # %entry
; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: beq s1, a1, .LBB49_4 ; CHECK-NEXT: beq s1, a1, .LBB49_4
; CHECK-NEXT: .LBB49_8: # %entry ; CHECK-NEXT: .LBB49_8: # %entry
; CHECK-NEXT: mv s2, a1 ; CHECK-NEXT: mv s0, a1
; CHECK-NEXT: bne s1, a4, .LBB49_5 ; CHECK-NEXT: bne s1, a4, .LBB49_5
; CHECK-NEXT: j .LBB49_6 ; CHECK-NEXT: j .LBB49_6
entry: entry:
%conv = fptoui <2 x float> %x to <2 x i128> %conv = fptoui <2 x float> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>) %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
%conv6 = trunc <2 x i128> %spec.store.select to <2 x i64> %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
ret <2 x i64> %conv6 ret <2 x i64> %conv6
} }
define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) {
; CHECK-LABEL: ustest_f32i64_mm: ; CHECK-LABEL: ustest_f32i64_mm:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -32 ; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s0, a1 ; CHECK-NEXT: mv s2, a1
; CHECK-NEXT: call __fixsfti@plt ; CHECK-NEXT: call __fixsfti@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv s1, a1
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __fixsfti@plt ; CHECK-NEXT: call __fixsfti@plt
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: li a5, 1 ; CHECK-NEXT: li a5, 1
; CHECK-NEXT: mv a3, a1 ; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: bgtz a1, .LBB50_12 ; CHECK-NEXT: bgtz a1, .LBB50_12
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a4, s1 ; CHECK-NEXT: mv a4, s1
; CHECK-NEXT: bgtz s1, .LBB50_13 ; CHECK-NEXT: bgtz s1, .LBB50_13
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; CHECK-NEXT: .LBB50_14: # %entry ; CHECK-NEXT: .LBB50_14: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: beq a2, a5, .LBB50_4 ; CHECK-NEXT: beq a2, a5, .LBB50_4
; CHECK-NEXT: .LBB50_15: # %entry ; CHECK-NEXT: .LBB50_15: # %entry
; CHECK-NEXT: mv a1, a0 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: blez s1, .LBB50_5 ; CHECK-NEXT: blez s1, .LBB50_5
; CHECK-NEXT: .LBB50_16: # %entry ; CHECK-NEXT: .LBB50_16: # %entry
; CHECK-NEXT: li s2, 0 ; CHECK-NEXT: li s0, 0
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: beq s1, a5, .LBB50_6 ; CHECK-NEXT: beq s1, a5, .LBB50_6
; CHECK-NEXT: .LBB50_17: # %entry ; CHECK-NEXT: .LBB50_17: # %entry
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s0
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: bgtz a4, .LBB50_7 ; CHECK-NEXT: bgtz a4, .LBB50_7
; CHECK-NEXT: .LBB50_18: # %entry ; CHECK-NEXT: .LBB50_18: # %entry
; CHECK-NEXT: li a2, 0 ; CHECK-NEXT: li a2, 0
; CHECK-NEXT: beqz a4, .LBB50_8 ; CHECK-NEXT: beqz a4, .LBB50_8
; CHECK-NEXT: .LBB50_19: # %entry ; CHECK-NEXT: .LBB50_19: # %entry
; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
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; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __fixunssfti@plt ; CHECK-NEXT: call __fixunssfti@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv s1, a1
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __fixunssfti@plt ; CHECK-NEXT: call __fixunssfti@plt
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: mv a3, a1 ; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: beqz a3, .LBB52_2 ; CHECK-NEXT: beqz a3, .LBB52_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: .LBB52_2: # %entry ; CHECK-NEXT: .LBB52_2: # %entry
; CHECK-NEXT: li a4, 1 ; CHECK-NEXT: li a4, 1
; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: bne a3, a4, .LBB52_7 ; CHECK-NEXT: bne a3, a4, .LBB52_7
; CHECK-NEXT: # %bb.3: # %entry ; CHECK-NEXT: # %bb.3: # %entry
; CHECK-NEXT: bne s1, a1, .LBB52_8 ; CHECK-NEXT: bne s1, a1, .LBB52_8
; CHECK-NEXT: .LBB52_4: # %entry ; CHECK-NEXT: .LBB52_4: # %entry
; CHECK-NEXT: beq s1, a4, .LBB52_6 ; CHECK-NEXT: beq s1, a4, .LBB52_6
; CHECK-NEXT: .LBB52_5: # %entry ; CHECK-NEXT: .LBB52_5: # %entry
; CHECK-NEXT: mv a1, s2 ; CHECK-NEXT: mv a1, s0
; CHECK-NEXT: .LBB52_6: # %entry ; CHECK-NEXT: .LBB52_6: # %entry
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB52_7: # %entry ; CHECK-NEXT: .LBB52_7: # %entry
; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: beq s1, a1, .LBB52_4 ; CHECK-NEXT: beq s1, a1, .LBB52_4
; CHECK-NEXT: .LBB52_8: # %entry ; CHECK-NEXT: .LBB52_8: # %entry
; CHECK-NEXT: mv s2, a1 ; CHECK-NEXT: mv s0, a1
; CHECK-NEXT: bne s1, a4, .LBB52_5 ; CHECK-NEXT: bne s1, a4, .LBB52_5
; CHECK-NEXT: j .LBB52_6 ; CHECK-NEXT: j .LBB52_6
entry: entry:
%conv = fptoui <2 x half> %x to <2 x i128> %conv = fptoui <2 x half> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>) %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
%conv6 = trunc <2 x i128> %spec.store.select to <2 x i64> %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
ret <2 x i64> %conv6 ret <2 x i64> %conv6
} }
define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) {
; CHECK-LABEL: ustest_f16i64_mm: ; CHECK-LABEL: ustest_f16i64_mm:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -32 ; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32 ; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s0, a1 ; CHECK-NEXT: mv s2, a1
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __fixsfti@plt ; CHECK-NEXT: call __fixsfti@plt
; CHECK-NEXT: mv s2, a0 ; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: mv s1, a1 ; CHECK-NEXT: mv s1, a1
; CHECK-NEXT: mv a0, s0 ; CHECK-NEXT: mv a0, s2
; CHECK-NEXT: call __gnu_h2f_ieee@plt ; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: call __fixsfti@plt ; CHECK-NEXT: call __fixsfti@plt
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: li a5, 1 ; CHECK-NEXT: li a5, 1
; CHECK-NEXT: mv a3, a1 ; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: bgtz a1, .LBB53_12 ; CHECK-NEXT: bgtz a1, .LBB53_12
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: mv a4, s1 ; CHECK-NEXT: mv a4, s1
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; CHECK-NEXT: .LBB53_14: # %entry ; CHECK-NEXT: .LBB53_14: # %entry
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: beq a2, a5, .LBB53_4 ; CHECK-NEXT: beq a2, a5, .LBB53_4
; CHECK-NEXT: .LBB53_15: # %entry ; CHECK-NEXT: .LBB53_15: # %entry
; CHECK-NEXT: mv a1, a0 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: blez s1, .LBB53_5 ; CHECK-NEXT: blez s1, .LBB53_5
; CHECK-NEXT: .LBB53_16: # %entry ; CHECK-NEXT: .LBB53_16: # %entry
; CHECK-NEXT: li s2, 0 ; CHECK-NEXT: li s0, 0
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: beq s1, a5, .LBB53_6 ; CHECK-NEXT: beq s1, a5, .LBB53_6
; CHECK-NEXT: .LBB53_17: # %entry ; CHECK-NEXT: .LBB53_17: # %entry
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s0
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: bgtz a4, .LBB53_7 ; CHECK-NEXT: bgtz a4, .LBB53_7
; CHECK-NEXT: .LBB53_18: # %entry ; CHECK-NEXT: .LBB53_18: # %entry
; CHECK-NEXT: li a2, 0 ; CHECK-NEXT: li a2, 0
; CHECK-NEXT: beqz a4, .LBB53_8 ; CHECK-NEXT: beqz a4, .LBB53_8
; CHECK-NEXT: .LBB53_19: # %entry ; CHECK-NEXT: .LBB53_19: # %entry
; CHECK-NEXT: mv a0, a2 ; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a2, a1
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llvm/test/CodeGen/RISCV/half-arith.ll

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; ;
; RV32I-LABEL: fadd_s: ; RV32I-LABEL: fadd_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0 ; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fadd_s: ; RV64I-LABEL: fadd_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0 ; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
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; ;
; RV32I-LABEL: fsub_s: ; RV32I-LABEL: fsub_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0 ; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __subsf3@plt ; RV32I-NEXT: call __subsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fsub_s: ; RV64I-LABEL: fsub_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0 ; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __subsf3@plt ; RV64I-NEXT: call __subsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
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; ;
; RV32I-LABEL: fmul_s: ; RV32I-LABEL: fmul_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0 ; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __mulsf3@plt ; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fmul_s: ; RV64I-LABEL: fmul_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0 ; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __mulsf3@plt ; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
Show All 17 Lines
; ;
; RV32I-LABEL: fdiv_s: ; RV32I-LABEL: fdiv_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0 ; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __divsf3@plt ; RV32I-NEXT: call __divsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fdiv_s: ; RV64I-LABEL: fdiv_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0 ; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __divsf3@plt ; RV64I-NEXT: call __divsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 183 Lines • ▼ Show 20 Lines
; RV32I-LABEL: fsgnjn_s: ; RV32I-LABEL: fsgnjn_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s3, a0, -1
; RV32I-NEXT: and a0, s2, s0 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s3, s0 ; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lui a1, 1048568 ; RV32I-NEXT: lui a1, 1048568
; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: slli a1, s2, 17 ; RV32I-NEXT: slli a1, s1, 17
; RV32I-NEXT: srli a1, a1, 17 ; RV32I-NEXT: srli a1, a1, 17
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fsgnjn_s: ; RV64I-LABEL: fsgnjn_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s3, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s3, a0, -1
; RV64I-NEXT: and a0, s2, s0 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s3, s0 ; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: lui a1, 1048568 ; RV64I-NEXT: lui a1, 1048568
; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: slli a1, s2, 49 ; RV64I-NEXT: slli a1, s1, 49
; RV64I-NEXT: srli a1, a1, 49 ; RV64I-NEXT: srli a1, a1, 49
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
Show All 25 Lines
; ;
; RV32I-LABEL: fabs_s: ; RV32I-LABEL: fabs_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s1, a1, -1 ; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s1 ; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fabs_s: ; RV64I-LABEL: fabs_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s1, a1, -1 ; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s1 ; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: slli a0, a0, 33 ; RV64I-NEXT: slli a0, a0, 33
; RV64I-NEXT: srli a0, a0, 33 ; RV64I-NEXT: srli a0, a0, 33
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
Show All 20 Lines
; ;
; RV32I-LABEL: fmin_s: ; RV32I-LABEL: fmin_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0 ; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call fminf@plt ; RV32I-NEXT: call fminf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fmin_s: ; RV64I-LABEL: fmin_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0 ; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call fminf@plt ; RV64I-NEXT: call fminf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
Show All 19 Lines
; ;
; RV32I-LABEL: fmax_s: ; RV32I-LABEL: fmax_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0 ; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call fmaxf@plt ; RV32I-NEXT: call fmaxf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fmax_s: ; RV64I-LABEL: fmax_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0 ; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call fmaxf@plt ; RV64I-NEXT: call fmaxf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
Show All 20 Lines
; RV32I-LABEL: fmadd_s: ; RV32I-LABEL: fmadd_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a2 ; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s3, a1, -1
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s1, s0 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0 ; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call fmaf@plt ; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fmadd_s: ; RV64I-LABEL: fmadd_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s1, s0 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0 ; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a1, s1 ; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call fmaf@plt ; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
Show All 21 Lines
; RV32I-LABEL: fmsub_s: ; RV32I-LABEL: fmsub_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s3, a0, -1
; RV32I-NEXT: and a0, a2, s0 ; RV32I-NEXT: and a0, a2, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s1, s0 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: and a0, s2, s0
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s4, s0 ; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: and a0, s2, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call fmaf@plt ; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fmsub_s: ; RV64I-LABEL: fmsub_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s3, a0, -1
; RV64I-NEXT: and a0, a2, s0 ; RV64I-NEXT: and a0, a2, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s1, s0 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: and a0, s2, s0
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s4, s0 ; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s2, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s1 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call fmaf@plt ; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%c_ = fadd half 0.0, %c ; avoid negation using xor %c_ = fadd half 0.0, %c ; avoid negation using xor
%negc = fsub half -0.0, %c_ %negc = fsub half -0.0, %c_
%1 = call half @llvm.fma.f16(half %a, half %b, half %negc) %1 = call half @llvm.fma.f16(half %a, half %b, half %negc)
ret half %1 ret half %1
} }
Show All 18 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s1, a1, -1 ; RV32I-NEXT: addi s3, a1, -1
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s3, s1 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s4, s1 ; RV32I-NEXT: and a0, s2, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: lui s4, 524288 ; RV32I-NEXT: lui s4, 524288
; RV32I-NEXT: xor a0, a0, s4 ; RV32I-NEXT: xor a0, a0, s4
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s0, s1 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: xor a0, a0, s4 ; RV32I-NEXT: xor a0, a0, s4
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s1 ; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s3, s1
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: and a0, s4, s1 ; RV32I-NEXT: and a0, s2, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call fmaf@plt ; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmadd_s: ; RV64I-LABEL: fnmadd_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s3, a2 ; RV64I-NEXT: mv s1, a2
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s1, a1, -1 ; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s3, s1 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s4, s1 ; RV64I-NEXT: and a0, s2, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: lui s4, 524288 ; RV64I-NEXT: lui s4, 524288
; RV64I-NEXT: xor a0, a0, s4 ; RV64I-NEXT: xor a0, a0, s4
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s0, s1 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: xor a0, a0, s4 ; RV64I-NEXT: xor a0, a0, s4
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s1 ; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s3, s1
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s4, s1 ; RV64I-NEXT: and a0, s2, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call fmaf@plt ; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
Show All 28 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a2 ; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s1, a0, -1 ; RV32I-NEXT: addi s3, a0, -1
; RV32I-NEXT: and a0, a1, s1 ; RV32I-NEXT: and a0, a1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s3, s1 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s4, s1 ; RV32I-NEXT: and a0, s2, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: lui s4, 524288 ; RV32I-NEXT: lui s4, 524288
; RV32I-NEXT: xor a0, a0, s4 ; RV32I-NEXT: xor a0, a0, s4
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s0, s1 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: xor a0, a0, s4 ; RV32I-NEXT: xor a0, a0, s4
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s1 ; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s3, s1
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: and a0, s4, s1 ; RV32I-NEXT: and a0, s2, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call fmaf@plt ; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmadd_s_2: ; RV64I-LABEL: fnmadd_s_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s3, a2 ; RV64I-NEXT: mv s1, a2
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s1, a0, -1 ; RV64I-NEXT: addiw s3, a0, -1
; RV64I-NEXT: and a0, a1, s1 ; RV64I-NEXT: and a0, a1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s3, s1 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s4, s1 ; RV64I-NEXT: and a0, s2, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: lui s4, 524288 ; RV64I-NEXT: lui s4, 524288
; RV64I-NEXT: xor a0, a0, s4 ; RV64I-NEXT: xor a0, a0, s4
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s0, s1 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: xor a0, a0, s4 ; RV64I-NEXT: xor a0, a0, s4
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s1 ; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s3, s1
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s4, s1 ; RV64I-NEXT: and a0, s2, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call fmaf@plt ; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
Show All 25 Lines
; RV32I-LABEL: fnmsub_s: ; RV32I-LABEL: fnmsub_s:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s2, a2
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s3, a1, -1
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s1, s0 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: and a0, s2, s0
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s4, s0 ; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: and a0, s2, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: call fmaf@plt ; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmsub_s: ; RV64I-LABEL: fnmsub_s:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a2
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s1, s0 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: and a0, s2, s0
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s4, s0 ; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s2, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, s3 ; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: call fmaf@plt ; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a_ = fadd half 0.0, %a %a_ = fadd half 0.0, %a
%nega = fsub half -0.0, %a_ %nega = fsub half -0.0, %a_
%1 = call half @llvm.fma.f16(half %nega, half %b, half %c) %1 = call half @llvm.fma.f16(half %nega, half %b, half %c)
ret half %1 ret half %1
} }
Show All 15 Lines
; RV32I-LABEL: fnmsub_s_2: ; RV32I-LABEL: fnmsub_s_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s2, a2
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s3, a0, -1
; RV32I-NEXT: and a0, a1, s0 ; RV32I-NEXT: and a0, a1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s1, s0 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: and a0, s2, s0
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s4, s0 ; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: and a0, s2, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: call fmaf@plt ; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmsub_s_2: ; RV64I-LABEL: fnmsub_s_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a2
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s3, a0, -1
; RV64I-NEXT: and a0, a1, s0 ; RV64I-NEXT: and a0, a1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s1, s0 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: and a0, s2, s0
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s4, s0 ; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s2, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: call fmaf@plt ; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%b_ = fadd half 0.0, %b %b_ = fadd half 0.0, %b
%negb = fsub half -0.0, %b_ %negb = fsub half -0.0, %b_
%1 = call half @llvm.fma.f16(half %a, half %negb, half %c) %1 = call half @llvm.fma.f16(half %a, half %negb, half %c)
ret half %1 ret half %1
} }
Show All 11 Lines
; RV32I-LABEL: fmadd_s_contract: ; RV32I-LABEL: fmadd_s_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a2 ; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s1, a1, -1 ; RV32I-NEXT: addi s3, a1, -1
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s3, s1 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __mulsf3@plt ; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s1 ; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: and a0, s0, s1 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fmadd_s_contract: ; RV64I-LABEL: fmadd_s_contract:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s3, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s1, a1, -1 ; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s3, s1 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __mulsf3@plt ; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s1 ; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s0, s1 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
Show All 21 Lines
; RV32I-LABEL: fmsub_s_contract: ; RV32I-LABEL: fmsub_s_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 16 ; RV32I-NEXT: lui a0, 16
; RV32I-NEXT: addi s0, a0, -1 ; RV32I-NEXT: addi s3, a0, -1
; RV32I-NEXT: and a0, a2, s0 ; RV32I-NEXT: and a0, a2, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s1, s0 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s3, s0 ; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __mulsf3@plt ; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: and a0, s2, s0 ; RV32I-NEXT: and a0, s2, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __subsf3@plt ; RV32I-NEXT: call __subsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fmsub_s_contract: ; RV64I-LABEL: fmsub_s_contract:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s3, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 16 ; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw s0, a0, -1 ; RV64I-NEXT: addiw s3, a0, -1
; RV64I-NEXT: and a0, a2, s0 ; RV64I-NEXT: and a0, a2, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s1, s0 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s3, s0 ; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __mulsf3@plt ; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s2, s0 ; RV64I-NEXT: and a0, s2, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __subsf3@plt ; RV64I-NEXT: call __subsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
Show All 26 Lines
; RV32I-LABEL: fnmadd_s_contract: ; RV32I-LABEL: fnmadd_s_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s2, a2 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s1, a1, -1 ; RV32I-NEXT: addi s3, a1, -1
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s0, s1 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s1 ; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s3, s1
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: and a0, s4, s1 ; RV32I-NEXT: and a0, s2, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __mulsf3@plt ; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: xor a0, a0, a1 ; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s1 ; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: and a0, s0, s1 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __subsf3@plt ; RV32I-NEXT: call __subsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmadd_s_contract: ; RV64I-LABEL: fnmadd_s_contract:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s2, a2 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s1, a1, -1 ; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s0, s1 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s1 ; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s3, s1
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s4, s1 ; RV64I-NEXT: and a0, s2, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __mulsf3@plt ; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s1 ; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s0, s1 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __subsf3@plt ; RV64I-NEXT: call __subsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a_ = fadd half 0.0, %a ; avoid negation using xor %a_ = fadd half 0.0, %a ; avoid negation using xor
%b_ = fadd half 0.0, %b ; avoid negation using xor %b_ = fadd half 0.0, %b ; avoid negation using xor
%c_ = fadd half 0.0, %c ; avoid negation using xor %c_ = fadd half 0.0, %c ; avoid negation using xor
%1 = fmul contract half %a_, %b_ %1 = fmul contract half %a_, %b_
%2 = fneg half %1 %2 = fneg half %1
%3 = fsub contract half %2, %c_ %3 = fsub contract half %2, %c_
Show All 20 Lines
; RV32I-LABEL: fnmsub_s_contract: ; RV32I-LABEL: fnmsub_s_contract:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a2 ; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s3, a1, -1
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s1, s0 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s3, s0 ; RV32I-NEXT: and a0, s2, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s1, s0 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __mulsf3@plt ; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0 ; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: and a0, s1, s0 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __subsf3@plt ; RV32I-NEXT: call __subsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fnmsub_s_contract: ; RV64I-LABEL: fnmsub_s_contract:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s1, s0 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s3, s0 ; RV64I-NEXT: and a0, s2, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s1, s0 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __mulsf3@plt ; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0 ; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s1, s0 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __subsf3@plt ; RV64I-NEXT: call __subsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%a_ = fadd half 0.0, %a ; avoid negation using xor %a_ = fadd half 0.0, %a ; avoid negation using xor
%b_ = fadd half 0.0, %b ; avoid negation using xor %b_ = fadd half 0.0, %b ; avoid negation using xor
%1 = fmul contract half %a_, %b_ %1 = fmul contract half %a_, %b_
%2 = fsub contract half %c, %1 %2 = fsub contract half %c, %1
ret half %2 ret half %2
} }

llvm/test/CodeGen/RISCV/half-convert.ll

Show First 20 Lines • Show All 330 Lines • ▼ Show 20 Lines
; RV32I: # %bb.0: # %start ; RV32I: # %bb.0: # %start
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s2, a1, -1 ; RV32I-NEXT: addi s0, a1, -1
; RV32I-NEXT: and a0, a0, s2 ; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2@plt ; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __fixunssfsi@plt ; RV32I-NEXT: call __fixunssfsi@plt
; RV32I-NEXT: li s3, 0 ; RV32I-NEXT: li s3, 0
; RV32I-NEXT: bltz s0, .LBB3_2 ; RV32I-NEXT: bltz s2, .LBB3_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: .LBB3_2: # %start ; RV32I-NEXT: .LBB3_2: # %start
; RV32I-NEXT: lui a0, 292864 ; RV32I-NEXT: lui a0, 292864
; RV32I-NEXT: addi a1, a0, -256 ; RV32I-NEXT: addi a1, a0, -256
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: bgtz a0, .LBB3_4 ; RV32I-NEXT: bgtz a0, .LBB3_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s2, s3 ; RV32I-NEXT: mv s0, s3
; RV32I-NEXT: .LBB3_4: # %start ; RV32I-NEXT: .LBB3_4: # %start
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_ui_h_sat: ; RV64I-LABEL: fcvt_ui_h_sat:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s2, a1, -1 ; RV64I-NEXT: addiw s0, a1, -1
; RV64I-NEXT: and a0, a0, s2 ; RV64I-NEXT: and a0, a0, s0
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: li a1, 0 ; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __gesf2@plt ; RV64I-NEXT: call __gesf2@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __fixunssfdi@plt ; RV64I-NEXT: call __fixunssfdi@plt
; RV64I-NEXT: li s3, 0 ; RV64I-NEXT: li s3, 0
; RV64I-NEXT: bltz s0, .LBB3_2 ; RV64I-NEXT: bltz s2, .LBB3_2
; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: .LBB3_2: # %start ; RV64I-NEXT: .LBB3_2: # %start
; RV64I-NEXT: lui a0, 292864 ; RV64I-NEXT: lui a0, 292864
; RV64I-NEXT: addiw a1, a0, -256 ; RV64I-NEXT: addiw a1, a0, -256
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: call __gtsf2@plt
; RV64I-NEXT: bgtz a0, .LBB3_4 ; RV64I-NEXT: bgtz a0, .LBB3_4
; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: mv s2, s3 ; RV64I-NEXT: mv s0, s3
; RV64I-NEXT: .LBB3_4: # %start ; RV64I-NEXT: .LBB3_4: # %start
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
start: start:
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; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2@plt ; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixunssfdi@plt ; RV32I-NEXT: call __fixunssfdi@plt
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: li s5, 0 ; RV32I-NEXT: li s5, 0
; RV32I-NEXT: bltz s1, .LBB12_2 ; RV32I-NEXT: bltz s2, .LBB12_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: .LBB12_2: # %start ; RV32I-NEXT: .LBB12_2: # %start
; RV32I-NEXT: lui a0, 391168 ; RV32I-NEXT: lui a0, 391168
; RV32I-NEXT: addi s1, a0, -1 ; RV32I-NEXT: addi s4, a0, -1
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: li s2, -1
; RV32I-NEXT: li s3, -1 ; RV32I-NEXT: li s3, -1
; RV32I-NEXT: li s4, -1
; RV32I-NEXT: bgtz a0, .LBB12_4 ; RV32I-NEXT: bgtz a0, .LBB12_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s4, s5 ; RV32I-NEXT: mv s3, s5
; RV32I-NEXT: .LBB12_4: # %start ; RV32I-NEXT: .LBB12_4: # %start
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2@plt ; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: li s5, 0 ; RV32I-NEXT: li s5, 0
; RV32I-NEXT: bltz a0, .LBB12_6 ; RV32I-NEXT: bltz a0, .LBB12_6
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s5, s2 ; RV32I-NEXT: mv s5, s1
; RV32I-NEXT: .LBB12_6: # %start ; RV32I-NEXT: .LBB12_6: # %start
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: bgtz a0, .LBB12_8 ; RV32I-NEXT: bgtz a0, .LBB12_8
; RV32I-NEXT: # %bb.7: # %start ; RV32I-NEXT: # %bb.7: # %start
; RV32I-NEXT: mv s3, s5 ; RV32I-NEXT: mv s2, s5
; RV32I-NEXT: .LBB12_8: # %start ; RV32I-NEXT: .LBB12_8: # %start
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
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; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui a1, 815104 ; RV32I-NEXT: lui a1, 815104
; RV32I-NEXT: call __gesf2@plt ; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixsfsi@plt ; RV32I-NEXT: call __fixsfsi@plt
; RV32I-NEXT: li s1, 0 ; RV32I-NEXT: li s2, 0
; RV32I-NEXT: lui s3, 1048568 ; RV32I-NEXT: lui s3, 1048568
; RV32I-NEXT: bltz s2, .LBB32_2 ; RV32I-NEXT: bltz s1, .LBB32_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: .LBB32_2: # %start ; RV32I-NEXT: .LBB32_2: # %start
; RV32I-NEXT: lui a0, 290816 ; RV32I-NEXT: lui a0, 290816
; RV32I-NEXT: addi a1, a0, -512 ; RV32I-NEXT: addi a1, a0, -512
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: bge s1, a0, .LBB32_4 ; RV32I-NEXT: bge s2, a0, .LBB32_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: lui a0, 8 ; RV32I-NEXT: lui a0, 8
; RV32I-NEXT: addi s3, a0, -1 ; RV32I-NEXT: addi s3, a0, -1
; RV32I-NEXT: .LBB32_4: # %start ; RV32I-NEXT: .LBB32_4: # %start
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __unordsf2@plt ; RV32I-NEXT: call __unordsf2@plt
; RV32I-NEXT: bne a0, s1, .LBB32_6 ; RV32I-NEXT: bne a0, s2, .LBB32_6
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s1, s3 ; RV32I-NEXT: mv s2, s3
; RV32I-NEXT: .LBB32_6: # %start ; RV32I-NEXT: .LBB32_6: # %start
; RV32I-NEXT: slli a0, s1, 16 ; RV32I-NEXT: slli a0, s2, 16
; RV32I-NEXT: srai a0, a0, 16 ; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_w_s_sat_i16: ; RV64I-LABEL: fcvt_w_s_sat_i16:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 815104 ; RV64I-NEXT: lui a1, 815104
; RV64I-NEXT: call __gesf2@plt ; RV64I-NEXT: call __gesf2@plt
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi@plt ; RV64I-NEXT: call __fixsfdi@plt
; RV64I-NEXT: li s1, 0 ; RV64I-NEXT: li s2, 0
; RV64I-NEXT: lui s3, 1048568 ; RV64I-NEXT: lui s3, 1048568
; RV64I-NEXT: bltz s2, .LBB32_2 ; RV64I-NEXT: bltz s1, .LBB32_2
; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: .LBB32_2: # %start ; RV64I-NEXT: .LBB32_2: # %start
; RV64I-NEXT: lui a0, 290816 ; RV64I-NEXT: lui a0, 290816
; RV64I-NEXT: addiw a1, a0, -512 ; RV64I-NEXT: addiw a1, a0, -512
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: call __gtsf2@plt
; RV64I-NEXT: bge s1, a0, .LBB32_4 ; RV64I-NEXT: bge s2, a0, .LBB32_4
; RV64I-NEXT: # %bb.3: ; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: lui a0, 8 ; RV64I-NEXT: lui a0, 8
; RV64I-NEXT: addiw s3, a0, -1 ; RV64I-NEXT: addiw s3, a0, -1
; RV64I-NEXT: .LBB32_4: # %start ; RV64I-NEXT: .LBB32_4: # %start
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unordsf2@plt ; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: bne a0, s1, .LBB32_6 ; RV64I-NEXT: bne a0, s2, .LBB32_6
; RV64I-NEXT: # %bb.5: # %start ; RV64I-NEXT: # %bb.5: # %start
; RV64I-NEXT: mv s1, s3 ; RV64I-NEXT: mv s2, s3
; RV64I-NEXT: .LBB32_6: # %start ; RV64I-NEXT: .LBB32_6: # %start
; RV64I-NEXT: slli a0, s1, 48 ; RV64I-NEXT: slli a0, s2, 48
; RV64I-NEXT: srai a0, a0, 48 ; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
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; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui a1, 798720 ; RV32I-NEXT: lui a1, 798720
; RV32I-NEXT: call __gesf2@plt ; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixsfsi@plt ; RV32I-NEXT: call __fixsfsi@plt
; RV32I-NEXT: li s1, 0 ; RV32I-NEXT: li s2, 0
; RV32I-NEXT: li s3, -128 ; RV32I-NEXT: li s3, -128
; RV32I-NEXT: bltz s2, .LBB36_2 ; RV32I-NEXT: bltz s1, .LBB36_2
; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: .LBB36_2: # %start ; RV32I-NEXT: .LBB36_2: # %start
; RV32I-NEXT: lui a1, 274400 ; RV32I-NEXT: lui a1, 274400
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: li s2, 127 ; RV32I-NEXT: li s1, 127
; RV32I-NEXT: blt s1, a0, .LBB36_4 ; RV32I-NEXT: blt s2, a0, .LBB36_4
; RV32I-NEXT: # %bb.3: # %start ; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s2, s3 ; RV32I-NEXT: mv s1, s3
; RV32I-NEXT: .LBB36_4: # %start ; RV32I-NEXT: .LBB36_4: # %start
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __unordsf2@plt ; RV32I-NEXT: call __unordsf2@plt
; RV32I-NEXT: bne a0, s1, .LBB36_6 ; RV32I-NEXT: bne a0, s2, .LBB36_6
; RV32I-NEXT: # %bb.5: # %start ; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s1, s2 ; RV32I-NEXT: mv s2, s1
; RV32I-NEXT: .LBB36_6: # %start ; RV32I-NEXT: .LBB36_6: # %start
; RV32I-NEXT: slli a0, s1, 24 ; RV32I-NEXT: slli a0, s2, 24
; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fcvt_w_s_sat_i8: ; RV64I-LABEL: fcvt_w_s_sat_i8:
; RV64I: # %bb.0: # %start ; RV64I: # %bb.0: # %start
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 798720 ; RV64I-NEXT: lui a1, 798720
; RV64I-NEXT: call __gesf2@plt ; RV64I-NEXT: call __gesf2@plt
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi@plt ; RV64I-NEXT: call __fixsfdi@plt
; RV64I-NEXT: li s1, 0 ; RV64I-NEXT: li s2, 0
; RV64I-NEXT: li s3, -128 ; RV64I-NEXT: li s3, -128
; RV64I-NEXT: bltz s2, .LBB36_2 ; RV64I-NEXT: bltz s1, .LBB36_2
; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: .LBB36_2: # %start ; RV64I-NEXT: .LBB36_2: # %start
; RV64I-NEXT: lui a1, 274400 ; RV64I-NEXT: lui a1, 274400
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: call __gtsf2@plt
; RV64I-NEXT: li s2, 127 ; RV64I-NEXT: li s1, 127
; RV64I-NEXT: blt s1, a0, .LBB36_4 ; RV64I-NEXT: blt s2, a0, .LBB36_4
; RV64I-NEXT: # %bb.3: # %start ; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: mv s2, s3 ; RV64I-NEXT: mv s1, s3
; RV64I-NEXT: .LBB36_4: # %start ; RV64I-NEXT: .LBB36_4: # %start
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unordsf2@plt ; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: bne a0, s1, .LBB36_6 ; RV64I-NEXT: bne a0, s2, .LBB36_6
; RV64I-NEXT: # %bb.5: # %start ; RV64I-NEXT: # %bb.5: # %start
; RV64I-NEXT: mv s1, s2 ; RV64I-NEXT: mv s2, s1
; RV64I-NEXT: .LBB36_6: # %start ; RV64I-NEXT: .LBB36_6: # %start
; RV64I-NEXT: slli a0, s1, 56 ; RV64I-NEXT: slli a0, s2, 56
; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
▲ Show 20 Lines • Show All 177 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/half-intrinsics.ll

Show First 20 Lines • Show All 392 Lines • ▼ Show 20 Lines
; RV32I-LABEL: sincos_f16: ; RV32I-LABEL: sincos_f16:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s1, a1, -1 ; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: call sinf@plt ; RV32I-NEXT: call sinf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call cosf@plt ; RV32I-NEXT: call cosf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: and a0, s2, s1 ; RV32I-NEXT: and a0, s1, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s0, s1 ; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: sincos_f16: ; RV64I-LABEL: sincos_f16:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s1, a1, -1 ; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: call sinf@plt ; RV64I-NEXT: call sinf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call cosf@plt ; RV64I-NEXT: call cosf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s2, s1 ; RV64I-NEXT: and a0, s1, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s0, s1 ; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; ;
; RV32I-LABEL: pow_f16: ; RV32I-LABEL: pow_f16:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0 ; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call powf@plt ; RV32I-NEXT: call powf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: pow_f16: ; RV64I-LABEL: pow_f16:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0 ; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call powf@plt ; RV64I-NEXT: call powf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 410 Lines • ▼ Show 20 Lines
; RV32I-LABEL: fma_f16: ; RV32I-LABEL: fma_f16:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a2 ; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s3, a1, -1
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s1, s0 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0 ; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call fmaf@plt ; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fma_f16: ; RV64I-LABEL: fma_f16:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s1, s0 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0 ; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a1, s1 ; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call fmaf@plt ; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
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; RV32I-LABEL: fmuladd_f16: ; RV32I-LABEL: fmuladd_f16:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a2 ; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s1, a1, -1 ; RV32I-NEXT: addi s3, a1, -1
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s3, s1 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __mulsf3@plt ; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s1 ; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: and a0, s0, s1 ; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: fmuladd_f16: ; RV64I-LABEL: fmuladd_f16:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a2 ; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s3, a1 ; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s1, a1, -1 ; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s3, s1 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __mulsf3@plt ; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s1 ; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: and a0, s0, s1 ; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, s2 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
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; ;
; RV32I-LABEL: minnum_f16: ; RV32I-LABEL: minnum_f16:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0 ; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call fminf@plt ; RV32I-NEXT: call fminf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: minnum_f16: ; RV64I-LABEL: minnum_f16:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0 ; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call fminf@plt ; RV64I-NEXT: call fminf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
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; ;
; RV32I-LABEL: maxnum_f16: ; RV32I-LABEL: maxnum_f16:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1 ; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0 ; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call fmaxf@plt ; RV32I-NEXT: call fmaxf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: maxnum_f16: ; RV64I-LABEL: maxnum_f16:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1 ; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0 ; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call fmaxf@plt ; RV64I-NEXT: call fmaxf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 599 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/mul.ll

Show First 20 Lines • Show All 1,135 Lines • ▼ Show 20 Lines
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = mul i64 %a, -3840 %1 = mul i64 %a, -3840
ret i64 %1 ret i64 %1
} }
define i128 @muli128_m3840(i128 %a) nounwind { define i128 @muli128_m3840(i128 %a) nounwind {
; RV32I-LABEL: muli128_m3840: ; RV32I-LABEL: muli128_m3840:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 4(a1) ; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a3, 8(a1) ; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw a4, 0(a1) ; RV32I-NEXT: lw a6, 0(a1)
; RV32I-NEXT: lw a1, 12(a1) ; RV32I-NEXT: lw a5, 12(a1)
; RV32I-NEXT: srli a6, a2, 20
; RV32I-NEXT: slli a5, a3, 12
; RV32I-NEXT: or a6, a5, a6
; RV32I-NEXT: srli a7, a2, 24
; RV32I-NEXT: slli a5, a3, 8
; RV32I-NEXT: or a7, a5, a7
; RV32I-NEXT: sltu t0, a7, a6
; RV32I-NEXT: srli t1, a3, 20
; RV32I-NEXT: slli a5, a1, 12
; RV32I-NEXT: or a5, a5, t1
; RV32I-NEXT: srli a3, a3, 24
; RV32I-NEXT: slli a1, a1, 8
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: sub t2, a1, a5
; RV32I-NEXT: srli a1, a4, 20 ; RV32I-NEXT: srli a1, a4, 20
; RV32I-NEXT: slli a3, a2, 12 ; RV32I-NEXT: slli a2, a3, 12
; RV32I-NEXT: or a3, a3, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: srli a1, a4, 24 ; RV32I-NEXT: srli a2, a4, 24
; RV32I-NEXT: slli a2, a2, 8 ; RV32I-NEXT: slli a7, a3, 8
; RV32I-NEXT: or a5, a2, a1 ; RV32I-NEXT: or a2, a7, a2
; RV32I-NEXT: slli t1, a4, 12 ; RV32I-NEXT: sltu t0, a2, a1
; RV32I-NEXT: slli t3, a4, 8 ; RV32I-NEXT: srli a7, a3, 20
; RV32I-NEXT: sltu t4, t3, t1 ; RV32I-NEXT: slli t1, a5, 12
; RV32I-NEXT: sub t0, t2, t0 ; RV32I-NEXT: or a7, t1, a7
; RV32I-NEXT: mv a2, t4 ; RV32I-NEXT: srli a3, a3, 24
; RV32I-NEXT: slli a5, a5, 8
; RV32I-NEXT: or a3, a5, a3
; RV32I-NEXT: sub t1, a3, a7
; RV32I-NEXT: srli a3, a6, 20
; RV32I-NEXT: slli a5, a4, 12
; RV32I-NEXT: or a3, a5, a3
; RV32I-NEXT: srli a5, a6, 24
; RV32I-NEXT: slli a4, a4, 8
; RV32I-NEXT: or a5, a4, a5
; RV32I-NEXT: slli a4, a6, 12
; RV32I-NEXT: slli a6, a6, 8
; RV32I-NEXT: sltu a7, a6, a4
; RV32I-NEXT: sub t0, t1, t0
; RV32I-NEXT: mv t1, a7
; RV32I-NEXT: beq a5, a3, .LBB30_2 ; RV32I-NEXT: beq a5, a3, .LBB30_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a2, a5, a3 ; RV32I-NEXT: sltu t1, a5, a3
; RV32I-NEXT: .LBB30_2: ; RV32I-NEXT: .LBB30_2:
; RV32I-NEXT: sub a1, a7, a6 ; RV32I-NEXT: sub a1, a2, a1
; RV32I-NEXT: sltu a4, a1, a2 ; RV32I-NEXT: sltu a2, a1, t1
; RV32I-NEXT: sub a4, t0, a4 ; RV32I-NEXT: sub a2, t0, a2
; RV32I-NEXT: sub a1, a1, a2 ; RV32I-NEXT: sub a1, a1, t1
; RV32I-NEXT: sub a2, a5, a3 ; RV32I-NEXT: sub a3, a5, a3
; RV32I-NEXT: sub a2, a2, t4 ; RV32I-NEXT: sub a3, a3, a7
; RV32I-NEXT: sub a3, t3, t1 ; RV32I-NEXT: sub a4, a6, a4
; RV32I-NEXT: sw a3, 0(a0) ; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: sw a2, 4(a0) ; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: sw a1, 8(a0) ; RV32I-NEXT: sw a1, 8(a0)
; RV32I-NEXT: sw a4, 12(a0) ; RV32I-NEXT: sw a2, 12(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: muli128_m3840: ; RV32IM-LABEL: muli128_m3840:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s1, 8(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s2, 4(sp) # 4-byte Folded Spill ; RV32IM-NEXT: lw a2, 12(a1)
; RV32IM-NEXT: lw a6, 12(a1) ; RV32IM-NEXT: lw a3, 8(a1)
; RV32IM-NEXT: lw a7, 8(a1)
; RV32IM-NEXT: lw a4, 0(a1) ; RV32IM-NEXT: lw a4, 0(a1)
; RV32IM-NEXT: lw a1, 4(a1) ; RV32IM-NEXT: lw a1, 4(a1)
; RV32IM-NEXT: lui a5, 1048575 ; RV32IM-NEXT: lui a5, 1048575
; RV32IM-NEXT: addi a5, a5, 256 ; RV32IM-NEXT: addi a5, a5, 256
; RV32IM-NEXT: mulhu a2, a4, a5 ; RV32IM-NEXT: mulhu a6, a4, a5
; RV32IM-NEXT: mul a3, a1, a5 ; RV32IM-NEXT: mul a7, a1, a5
; RV32IM-NEXT: add a2, a3, a2 ; RV32IM-NEXT: add a6, a7, a6
; RV32IM-NEXT: sltu t0, a2, a3 ; RV32IM-NEXT: sltu a7, a6, a7
; RV32IM-NEXT: mulhu a3, a1, a5 ; RV32IM-NEXT: mulhu t0, a1, a5
; RV32IM-NEXT: add t5, a3, t0 ; RV32IM-NEXT: add a7, t0, a7
; RV32IM-NEXT: sub t0, a2, a4 ; RV32IM-NEXT: sub a6, a6, a4
; RV32IM-NEXT: neg t4, a4 ; RV32IM-NEXT: neg t0, a4
; RV32IM-NEXT: sltu t1, t0, t4 ; RV32IM-NEXT: sltu t1, a6, t0
; RV32IM-NEXT: li t2, -1 ; RV32IM-NEXT: li t2, -1
; RV32IM-NEXT: mulhu t3, a4, t2 ; RV32IM-NEXT: mulhu t3, a4, t2
; RV32IM-NEXT: add a2, t3, t1 ; RV32IM-NEXT: add t1, t3, t1
; RV32IM-NEXT: add t1, t5, a2 ; RV32IM-NEXT: add t1, a7, t1
; RV32IM-NEXT: sub a3, t1, a1 ; RV32IM-NEXT: sub t4, t1, a1
; RV32IM-NEXT: mul a2, a7, a5 ; RV32IM-NEXT: mul t5, a3, a5
; RV32IM-NEXT: sub a2, a2, a4 ; RV32IM-NEXT: sub t5, t5, a4
; RV32IM-NEXT: add t6, a3, a2 ; RV32IM-NEXT: add t6, t4, t5
; RV32IM-NEXT: sltu s2, t6, a3 ; RV32IM-NEXT: sltu s0, t6, t4
; RV32IM-NEXT: neg s1, a1 ; RV32IM-NEXT: neg s1, a1
; RV32IM-NEXT: sltu a3, a3, s1 ; RV32IM-NEXT: sltu t4, t4, s1
; RV32IM-NEXT: sltu s1, t1, t5 ; RV32IM-NEXT: sltu a7, t1, a7
; RV32IM-NEXT: mulhu s0, a1, t2 ; RV32IM-NEXT: mulhu t1, a1, t2
; RV32IM-NEXT: add s1, s0, s1 ; RV32IM-NEXT: add a7, t1, a7
; RV32IM-NEXT: add a3, s1, a3 ; RV32IM-NEXT: add a7, a7, t4
; RV32IM-NEXT: sltu a2, a2, t4 ; RV32IM-NEXT: sltu t0, t5, t0
; RV32IM-NEXT: mul s1, a6, a5 ; RV32IM-NEXT: mul a2, a2, a5
; RV32IM-NEXT: mulhu s0, a7, a5 ; RV32IM-NEXT: mulhu t1, a3, a5
; RV32IM-NEXT: sub s0, s0, a7 ; RV32IM-NEXT: sub a3, t1, a3
; RV32IM-NEXT: add s1, s0, s1 ; RV32IM-NEXT: add a2, a3, a2
; RV32IM-NEXT: sub s0, t3, a4 ; RV32IM-NEXT: sub a3, t3, a4
; RV32IM-NEXT: sub a1, s0, a1 ; RV32IM-NEXT: sub a1, a3, a1
; RV32IM-NEXT: add a1, a1, s1
; RV32IM-NEXT: add a1, a1, a2 ; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: add a1, a3, a1 ; RV32IM-NEXT: add a1, a1, t0
; RV32IM-NEXT: add a1, a1, s2 ; RV32IM-NEXT: add a1, a7, a1
; RV32IM-NEXT: add a1, a1, s0
; RV32IM-NEXT: mul a2, a4, a5 ; RV32IM-NEXT: mul a2, a4, a5
; RV32IM-NEXT: sw a2, 0(a0) ; RV32IM-NEXT: sw a2, 0(a0)
; RV32IM-NEXT: sw t0, 4(a0) ; RV32IM-NEXT: sw a6, 4(a0)
; RV32IM-NEXT: sw t6, 8(a0) ; RV32IM-NEXT: sw t6, 8(a0)
; RV32IM-NEXT: sw a1, 12(a0) ; RV32IM-NEXT: sw a1, 12(a0)
; RV32IM-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s1, 8(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: muli128_m3840: ; RV64I-LABEL: muli128_m3840:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a2, a0, 52 ; RV64I-NEXT: srli a2, a0, 52
; RV64I-NEXT: slli a3, a1, 12 ; RV64I-NEXT: slli a3, a1, 12
; RV64I-NEXT: or a2, a3, a2 ; RV64I-NEXT: or a2, a3, a2
Show All 21 Lines; RV64IM-NEXT: ret
%1 = mul i128 %a, -3840 %1 = mul i128 %a, -3840
ret i128 %1 ret i128 %1
} }
define i128 @muli128_m63(i128 %a) nounwind { define i128 @muli128_m63(i128 %a) nounwind {
; RV32I-LABEL: muli128_m63: ; RV32I-LABEL: muli128_m63:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a1) ; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: lw t0, 12(a1) ; RV32I-NEXT: lw a5, 12(a1)
; RV32I-NEXT: lw a4, 8(a1) ; RV32I-NEXT: lw a7, 8(a1)
; RV32I-NEXT: lw a3, 4(a1) ; RV32I-NEXT: lw a3, 4(a1)
; RV32I-NEXT: slli a6, a2, 6 ; RV32I-NEXT: slli a1, a2, 6
; RV32I-NEXT: sltu a7, a2, a6 ; RV32I-NEXT: sltu a4, a2, a1
; RV32I-NEXT: srli a1, a2, 26 ; RV32I-NEXT: srli a6, a2, 26
; RV32I-NEXT: slli a5, a3, 6 ; RV32I-NEXT: slli t0, a3, 6
; RV32I-NEXT: or t2, a5, a1 ; RV32I-NEXT: or a6, t0, a6
; RV32I-NEXT: mv t3, a7 ; RV32I-NEXT: mv t0, a4
; RV32I-NEXT: beq a3, t2, .LBB31_2 ; RV32I-NEXT: beq a3, a6, .LBB31_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu t3, a3, t2 ; RV32I-NEXT: sltu t0, a3, a6
; RV32I-NEXT: .LBB31_2: ; RV32I-NEXT: .LBB31_2:
; RV32I-NEXT: srli t1, a3, 26 ; RV32I-NEXT: srli t1, a3, 26
; RV32I-NEXT: slli a1, a4, 6 ; RV32I-NEXT: slli t2, a7, 6
; RV32I-NEXT: or a1, a1, t1 ; RV32I-NEXT: or t1, t2, t1
; RV32I-NEXT: sub a5, a4, a1 ; RV32I-NEXT: sub t2, a7, t1
; RV32I-NEXT: sltu t1, a5, t3 ; RV32I-NEXT: sltu t3, t2, t0
; RV32I-NEXT: sltu t4, a4, a1 ; RV32I-NEXT: sltu t1, a7, t1
; RV32I-NEXT: srli a4, a4, 26 ; RV32I-NEXT: srli a7, a7, 26
; RV32I-NEXT: slli a1, t0, 6 ; RV32I-NEXT: slli t4, a5, 6
; RV32I-NEXT: or a1, a1, a4 ; RV32I-NEXT: or a7, t4, a7
; RV32I-NEXT: sub a1, t0, a1 ; RV32I-NEXT: sub a5, a5, a7
; RV32I-NEXT: sub a1, a1, t4 ; RV32I-NEXT: sub a5, a5, t1
; RV32I-NEXT: sub a1, a1, t1 ; RV32I-NEXT: sub a5, a5, t3
; RV32I-NEXT: sub a4, a5, t3 ; RV32I-NEXT: sub a7, t2, t0
; RV32I-NEXT: sub a3, a3, t2 ; RV32I-NEXT: sub a3, a3, a6
; RV32I-NEXT: sub a3, a3, a7 ; RV32I-NEXT: sub a3, a3, a4
; RV32I-NEXT: sub a2, a2, a6 ; RV32I-NEXT: sub a1, a2, a1
; RV32I-NEXT: sw a2, 0(a0) ; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw a3, 4(a0) ; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: sw a4, 8(a0) ; RV32I-NEXT: sw a7, 8(a0)
; RV32I-NEXT: sw a1, 12(a0) ; RV32I-NEXT: sw a5, 12(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: muli128_m63: ; RV32IM-LABEL: muli128_m63:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s1, 8(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32IM-NEXT: lw a7, 12(a1) ; RV32IM-NEXT: lw a2, 12(a1)
; RV32IM-NEXT: lw a3, 0(a1) ; RV32IM-NEXT: lw a3, 0(a1)
; RV32IM-NEXT: lw a4, 4(a1) ; RV32IM-NEXT: lw a4, 4(a1)
; RV32IM-NEXT: lw t5, 8(a1) ; RV32IM-NEXT: lw a1, 8(a1)
; RV32IM-NEXT: li a6, -63 ; RV32IM-NEXT: li a5, -63
; RV32IM-NEXT: mulhu a5, a3, a6 ; RV32IM-NEXT: mulhu a6, a3, a5
; RV32IM-NEXT: slli a2, a4, 6 ; RV32IM-NEXT: slli a7, a4, 6
; RV32IM-NEXT: sub a2, a2, a4 ; RV32IM-NEXT: sub a7, a7, a4
; RV32IM-NEXT: sub a5, a5, a2 ; RV32IM-NEXT: sub a6, a6, a7
; RV32IM-NEXT: neg a2, a2 ; RV32IM-NEXT: neg a7, a7
; RV32IM-NEXT: sltu t0, a5, a2 ; RV32IM-NEXT: sltu a7, a6, a7
; RV32IM-NEXT: mulhu a2, a4, a6 ; RV32IM-NEXT: mulhu t0, a4, a5
; RV32IM-NEXT: add t4, a2, t0 ; RV32IM-NEXT: add a7, t0, a7
; RV32IM-NEXT: sub t0, a5, a3 ; RV32IM-NEXT: sub a6, a6, a3
; RV32IM-NEXT: neg t1, a3 ; RV32IM-NEXT: neg t0, a3
; RV32IM-NEXT: sltu a5, t0, t1 ; RV32IM-NEXT: sltu t1, a6, t0
; RV32IM-NEXT: li t2, -1 ; RV32IM-NEXT: li t2, -1
; RV32IM-NEXT: mulhu t3, a3, t2 ; RV32IM-NEXT: mulhu t3, a3, t2
; RV32IM-NEXT: add a5, t3, a5 ; RV32IM-NEXT: add t1, t3, t1
; RV32IM-NEXT: add a5, t4, a5 ; RV32IM-NEXT: add t1, a7, t1
; RV32IM-NEXT: sub a2, a5, a4 ; RV32IM-NEXT: sub t4, t1, a4
; RV32IM-NEXT: slli a1, t5, 6 ; RV32IM-NEXT: slli t5, a1, 6
; RV32IM-NEXT: sub a1, a1, t5 ; RV32IM-NEXT: sub t5, t5, a1
; RV32IM-NEXT: add a1, a1, a3 ; RV32IM-NEXT: add t5, t5, a3
; RV32IM-NEXT: sub t6, a2, a1 ; RV32IM-NEXT: sub t6, t4, t5
; RV32IM-NEXT: sltu s0, t6, a2 ; RV32IM-NEXT: sltu s0, t6, t4
; RV32IM-NEXT: neg s1, a4 ; RV32IM-NEXT: neg s1, a4
; RV32IM-NEXT: sltu a2, a2, s1 ; RV32IM-NEXT: sltu t4, t4, s1
; RV32IM-NEXT: sltu a5, a5, t4 ; RV32IM-NEXT: sltu a7, t1, a7
; RV32IM-NEXT: mulhu s1, a4, t2 ; RV32IM-NEXT: mulhu t1, a4, t2
; RV32IM-NEXT: add a5, s1, a5 ; RV32IM-NEXT: add a7, t1, a7
; RV32IM-NEXT: add a2, a5, a2 ; RV32IM-NEXT: add a7, a7, t4
; RV32IM-NEXT: slli a5, a7, 6 ; RV32IM-NEXT: slli t1, a2, 6
; RV32IM-NEXT: sub a5, a7, a5 ; RV32IM-NEXT: sub a2, a2, t1
; RV32IM-NEXT: mulhu s1, t5, a6 ; RV32IM-NEXT: mulhu a5, a1, a5
; RV32IM-NEXT: sub s1, s1, t5 ; RV32IM-NEXT: sub a1, a5, a1
; RV32IM-NEXT: add a5, s1, a5 ; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: sub s1, t3, a3 ; RV32IM-NEXT: sub a2, t3, a3
; RV32IM-NEXT: sub a4, s1, a4 ; RV32IM-NEXT: sub a2, a2, a4
; RV32IM-NEXT: add a4, a4, a5
; RV32IM-NEXT: neg a1, a1
; RV32IM-NEXT: sltu a1, a1, t1
; RV32IM-NEXT: add a1, a4, a1
; RV32IM-NEXT: add a1, a2, a1 ; RV32IM-NEXT: add a1, a2, a1
; RV32IM-NEXT: neg a2, t5
; RV32IM-NEXT: sltu a2, a2, t0
; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: add a1, a7, a1
; RV32IM-NEXT: add a1, a1, s0 ; RV32IM-NEXT: add a1, a1, s0
; RV32IM-NEXT: slli a2, a3, 6 ; RV32IM-NEXT: slli a2, a3, 6
; RV32IM-NEXT: sub a2, a3, a2 ; RV32IM-NEXT: sub a2, a3, a2
; RV32IM-NEXT: sw a2, 0(a0) ; RV32IM-NEXT: sw a2, 0(a0)
; RV32IM-NEXT: sw t0, 4(a0) ; RV32IM-NEXT: sw a6, 4(a0)
; RV32IM-NEXT: sw t6, 8(a0) ; RV32IM-NEXT: sw t6, 8(a0)
; RV32IM-NEXT: sw a1, 12(a0) ; RV32IM-NEXT: sw a1, 12(a0)
; RV32IM-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s1, 8(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: muli128_m63: ; RV64I-LABEL: muli128_m63:
Show All 33 Lines
; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s9, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s9, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a3 ; RV32I-NEXT: mv s2, a3
; RV32I-NEXT: mv s5, a2 ; RV32I-NEXT: mv s3, a2
; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: srai s4, a3, 31 ; RV32I-NEXT: srai s4, a3, 31
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt ; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: mv a2, s5 ; RV32I-NEXT: mv a2, s3
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt ; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: add s1, a0, s1 ; RV32I-NEXT: add s5, a0, s5
; RV32I-NEXT: sltu a0, s1, a0 ; RV32I-NEXT: sltu a0, s5, a0
; RV32I-NEXT: add s7, a1, a0 ; RV32I-NEXT: add s7, a1, a0
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt ; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: add a2, a0, s1 ; RV32I-NEXT: add a2, a0, s5
; RV32I-NEXT: sltu a0, a2, a0 ; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: add s8, s7, a0 ; RV32I-NEXT: add s8, s7, a0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: mv a2, s2
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt ; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: mv s9, a0 ; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: mv s6, a1 ; RV32I-NEXT: mv s6, a1
; RV32I-NEXT: add s1, a0, s8 ; RV32I-NEXT: add s9, a0, s8
; RV32I-NEXT: mv a0, s5 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt ; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s5, a1 ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s4 ; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: mv a2, s3 ; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __muldi3@plt ; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: add a3, a0, s0 ; RV32I-NEXT: add a3, a0, s2
; RV32I-NEXT: add a2, s1, a3 ; RV32I-NEXT: add a2, s9, a3
; RV32I-NEXT: sltu a4, a2, s1 ; RV32I-NEXT: sltu a4, a2, s9
; RV32I-NEXT: sltu a5, s1, s9 ; RV32I-NEXT: sltu a5, s9, s5
; RV32I-NEXT: sltu s1, s8, s7 ; RV32I-NEXT: sltu a6, s8, s7
; RV32I-NEXT: add s1, s6, s1 ; RV32I-NEXT: add a6, s6, a6
; RV32I-NEXT: add a5, s1, a5 ; RV32I-NEXT: add a5, a6, a5
; RV32I-NEXT: add a1, a1, s5 ; RV32I-NEXT: add a1, a1, s3
; RV32I-NEXT: sltu a0, a3, a0 ; RV32I-NEXT: sltu a0, a3, a0
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: add a0, a5, a0 ; RV32I-NEXT: add a0, a5, a0
; RV32I-NEXT: add a1, a0, a4 ; RV32I-NEXT: add a1, a0, a4
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: mulhsu_i64: ; RV32IM-LABEL: mulhsu_i64:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: srai a7, a3, 31 ; RV32IM-NEXT: srai a4, a3, 31
; RV32IM-NEXT: mulhu a6, a0, a2 ; RV32IM-NEXT: mulhu a5, a0, a2
; RV32IM-NEXT: mul a5, a1, a2 ; RV32IM-NEXT: mul a6, a1, a2
; RV32IM-NEXT: add a4, a5, a6 ; RV32IM-NEXT: add a5, a6, a5
; RV32IM-NEXT: sltu a5, a4, a5 ; RV32IM-NEXT: sltu a6, a5, a6
; RV32IM-NEXT: mulhu a2, a1, a2 ; RV32IM-NEXT: mulhu a2, a1, a2
; RV32IM-NEXT: add a6, a2, a5 ; RV32IM-NEXT: add a6, a2, a6
; RV32IM-NEXT: mul a2, a0, a3 ; RV32IM-NEXT: mul a2, a0, a3
; RV32IM-NEXT: add a4, a2, a4 ; RV32IM-NEXT: add a5, a2, a5
; RV32IM-NEXT: sltu a2, a4, a2 ; RV32IM-NEXT: sltu a2, a5, a2
; RV32IM-NEXT: mulhu a4, a0, a3 ; RV32IM-NEXT: mulhu a5, a0, a3
; RV32IM-NEXT: add a2, a4, a2 ; RV32IM-NEXT: add a2, a5, a2
; RV32IM-NEXT: add a4, a6, a2 ; RV32IM-NEXT: add a5, a6, a2
; RV32IM-NEXT: mul a5, a1, a3 ; RV32IM-NEXT: mul a7, a1, a3
; RV32IM-NEXT: add a2, a5, a4 ; RV32IM-NEXT: add t0, a7, a5
; RV32IM-NEXT: mul t1, a7, a0 ; RV32IM-NEXT: mul t1, a4, a0
; RV32IM-NEXT: add t0, a2, t1 ; RV32IM-NEXT: add a2, t0, t1
; RV32IM-NEXT: sltu t2, t0, a2 ; RV32IM-NEXT: sltu t2, a2, t0
; RV32IM-NEXT: sltu a2, a2, a5 ; RV32IM-NEXT: sltu a7, t0, a7
; RV32IM-NEXT: sltu a4, a4, a6 ; RV32IM-NEXT: sltu a5, a5, a6
; RV32IM-NEXT: mulhu a3, a1, a3 ; RV32IM-NEXT: mulhu a3, a1, a3
; RV32IM-NEXT: add a3, a3, a4 ; RV32IM-NEXT: add a3, a3, a5
; RV32IM-NEXT: add a2, a3, a2 ; RV32IM-NEXT: add a3, a3, a7
; RV32IM-NEXT: mul a1, a7, a1 ; RV32IM-NEXT: mul a1, a4, a1
; RV32IM-NEXT: mulhu a0, a7, a0 ; RV32IM-NEXT: mulhu a0, a4, a0
; RV32IM-NEXT: add a0, a0, a1 ; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: add a0, a0, t1 ; RV32IM-NEXT: add a0, a0, t1
; RV32IM-NEXT: add a0, a2, a0 ; RV32IM-NEXT: add a0, a3, a0
; RV32IM-NEXT: add a1, a0, t2 ; RV32IM-NEXT: add a1, a0, t2
; RV32IM-NEXT: mv a0, t0 ; RV32IM-NEXT: mv a0, a2
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: mulhsu_i64: ; RV64I-LABEL: mulhsu_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, a1 ; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: srai a3, a1, 63 ; RV64I-NEXT: srai a3, a1, 63
Show All 19 Lines

llvm/test/CodeGen/RISCV/remat.ll

Show All 31 Lines
; RV32I-NEXT: sw s4, 40(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 36(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 32(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s6, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s7, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s8, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s9, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s9, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s10, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s10, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s11, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui s6, %hi(a) ; RV32I-NEXT: lui s0, %hi(a)
; RV32I-NEXT: lw a0, %lo(a)(s6) ; RV32I-NEXT: lw a0, %lo(a)(s0)
; RV32I-NEXT: beqz a0, .LBB0_11 ; RV32I-NEXT: beqz a0, .LBB0_11
; RV32I-NEXT: # %bb.1: # %for.body.preheader ; RV32I-NEXT: # %bb.1: # %for.body.preheader
; RV32I-NEXT: lui s2, %hi(l) ; RV32I-NEXT: lui s1, %hi(l)
; RV32I-NEXT: lui s3, %hi(k) ; RV32I-NEXT: lui s2, %hi(k)
; RV32I-NEXT: lui s4, %hi(j) ; RV32I-NEXT: lui s3, %hi(j)
; RV32I-NEXT: lui s5, %hi(i) ; RV32I-NEXT: lui s4, %hi(i)
; RV32I-NEXT: lui s1, %hi(d) ; RV32I-NEXT: lui s5, %hi(d)
; RV32I-NEXT: lui s0, %hi(e) ; RV32I-NEXT: lui s6, %hi(e)
; RV32I-NEXT: lui s7, %hi(f) ; RV32I-NEXT: lui s7, %hi(f)
; RV32I-NEXT: lui s8, %hi(g) ; RV32I-NEXT: lui s8, %hi(g)
; RV32I-NEXT: lui s9, %hi(h) ; RV32I-NEXT: lui s9, %hi(h)
; RV32I-NEXT: lui s10, %hi(c) ; RV32I-NEXT: lui s10, %hi(c)
; RV32I-NEXT: lui s11, %hi(b) ; RV32I-NEXT: lui s11, %hi(b)
; RV32I-NEXT: j .LBB0_3 ; RV32I-NEXT: j .LBB0_3
; RV32I-NEXT: .LBB0_2: # %for.inc ; RV32I-NEXT: .LBB0_2: # %for.inc
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(a)(s6) ; RV32I-NEXT: lw a0, %lo(a)(s0)
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: sw a0, %lo(a)(s6) ; RV32I-NEXT: sw a0, %lo(a)(s0)
; RV32I-NEXT: beqz a0, .LBB0_11 ; RV32I-NEXT: beqz a0, .LBB0_11
; RV32I-NEXT: .LBB0_3: # %for.body ; RV32I-NEXT: .LBB0_3: # %for.body
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: lw a1, %lo(l)(s2) ; RV32I-NEXT: lw a1, %lo(l)(s1)
; RV32I-NEXT: beqz a1, .LBB0_5 ; RV32I-NEXT: beqz a1, .LBB0_5
; RV32I-NEXT: # %bb.4: # %if.then ; RV32I-NEXT: # %bb.4: # %if.then
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a1, %lo(b)(s11) ; RV32I-NEXT: lw a1, %lo(b)(s11)
; RV32I-NEXT: lw a2, %lo(c)(s10) ; RV32I-NEXT: lw a2, %lo(c)(s10)
; RV32I-NEXT: lw a3, %lo(d)(s1) ; RV32I-NEXT: lw a3, %lo(d)(s5)
; RV32I-NEXT: lw a4, %lo(e)(s0) ; RV32I-NEXT: lw a4, %lo(e)(s6)
; RV32I-NEXT: li a5, 32 ; RV32I-NEXT: li a5, 32
; RV32I-NEXT: call foo@plt ; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .LBB0_5: # %if.end ; RV32I-NEXT: .LBB0_5: # %if.end
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(k)(s3) ; RV32I-NEXT: lw a0, %lo(k)(s2)
; RV32I-NEXT: beqz a0, .LBB0_7 ; RV32I-NEXT: beqz a0, .LBB0_7
; RV32I-NEXT: # %bb.6: # %if.then3 ; RV32I-NEXT: # %bb.6: # %if.then3
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(b)(s11) ; RV32I-NEXT: lw a0, %lo(b)(s11)
; RV32I-NEXT: lw a1, %lo(c)(s10) ; RV32I-NEXT: lw a1, %lo(c)(s10)
; RV32I-NEXT: lw a2, %lo(d)(s1) ; RV32I-NEXT: lw a2, %lo(d)(s5)
; RV32I-NEXT: lw a3, %lo(e)(s0) ; RV32I-NEXT: lw a3, %lo(e)(s6)
; RV32I-NEXT: lw a4, %lo(f)(s7) ; RV32I-NEXT: lw a4, %lo(f)(s7)
; RV32I-NEXT: li a5, 64 ; RV32I-NEXT: li a5, 64
; RV32I-NEXT: call foo@plt ; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .LBB0_7: # %if.end5 ; RV32I-NEXT: .LBB0_7: # %if.end5
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(j)(s4) ; RV32I-NEXT: lw a0, %lo(j)(s3)
; RV32I-NEXT: beqz a0, .LBB0_9 ; RV32I-NEXT: beqz a0, .LBB0_9
; RV32I-NEXT: # %bb.8: # %if.then7 ; RV32I-NEXT: # %bb.8: # %if.then7
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(c)(s10) ; RV32I-NEXT: lw a0, %lo(c)(s10)
; RV32I-NEXT: lw a1, %lo(d)(s1) ; RV32I-NEXT: lw a1, %lo(d)(s5)
; RV32I-NEXT: lw a2, %lo(e)(s0) ; RV32I-NEXT: lw a2, %lo(e)(s6)
; RV32I-NEXT: lw a3, %lo(f)(s7) ; RV32I-NEXT: lw a3, %lo(f)(s7)
; RV32I-NEXT: lw a4, %lo(g)(s8) ; RV32I-NEXT: lw a4, %lo(g)(s8)
; RV32I-NEXT: li a5, 32 ; RV32I-NEXT: li a5, 32
; RV32I-NEXT: call foo@plt ; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .LBB0_9: # %if.end9 ; RV32I-NEXT: .LBB0_9: # %if.end9
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(i)(s5) ; RV32I-NEXT: lw a0, %lo(i)(s4)
; RV32I-NEXT: beqz a0, .LBB0_2 ; RV32I-NEXT: beqz a0, .LBB0_2
; RV32I-NEXT: # %bb.10: # %if.then11 ; RV32I-NEXT: # %bb.10: # %if.then11
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1 ; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(d)(s1) ; RV32I-NEXT: lw a0, %lo(d)(s5)
; RV32I-NEXT: lw a1, %lo(e)(s0) ; RV32I-NEXT: lw a1, %lo(e)(s6)
; RV32I-NEXT: lw a2, %lo(f)(s7) ; RV32I-NEXT: lw a2, %lo(f)(s7)
; RV32I-NEXT: lw a3, %lo(g)(s8) ; RV32I-NEXT: lw a3, %lo(g)(s8)
; RV32I-NEXT: lw a4, %lo(h)(s9) ; RV32I-NEXT: lw a4, %lo(h)(s9)
; RV32I-NEXT: li a5, 32 ; RV32I-NEXT: li a5, 32
; RV32I-NEXT: call foo@plt ; RV32I-NEXT: call foo@plt
; RV32I-NEXT: j .LBB0_2 ; RV32I-NEXT: j .LBB0_2
; RV32I-NEXT: .LBB0_11: # %for.end ; RV32I-NEXT: .LBB0_11: # %for.end
; RV32I-NEXT: li a0, 1 ; RV32I-NEXT: li a0, 1
▲ Show 20 Lines • Show All 88 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll

Show All 13 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16 ; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s1, a1, -1 ; RV32I-NEXT: addi s2, a1, -1
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s0, s1 ; RV32I-NEXT: and a0, s0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __addsf3@plt ; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: call __gnu_h2f_ieee@plt ; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __divsf3@plt ; RV32I-NEXT: call __divsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt ; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: half_test: ; RV64I-LABEL: half_test:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32 ; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16 ; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s1, a1, -1 ; RV64I-NEXT: addiw s2, a1, -1
; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s0, s1 ; RV64I-NEXT: and a0, s0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __addsf3@plt ; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: call __gnu_h2f_ieee@plt ; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, s0 ; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __divsf3@plt ; RV64I-NEXT: call __divsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt ; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32 ; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = fadd half %a, %b %1 = fadd half %a, %b
%2 = fdiv half %1, %b %2 = fdiv half %1, %b
ret half %2 ret half %2
} }

llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

Show First 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a3, a2, 5 ; RV32I-NEXT: srli a3, a2, 5
; RV32I-NEXT: andi a3, a3, 1 ; RV32I-NEXT: andi a3, a3, 1
; RV32I-NEXT: mv a4, a1 ; RV32I-NEXT: mv a4, a1
; RV32I-NEXT: bnez a3, .LBB7_2 ; RV32I-NEXT: bnez a3, .LBB7_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: .LBB7_2: ; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: sll a6, a4, a2 ; RV32I-NEXT: sll a5, a4, a2
; RV32I-NEXT: bnez a3, .LBB7_4 ; RV32I-NEXT: bnez a3, .LBB7_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB7_4: ; RV32I-NEXT: .LBB7_4:
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: not a5, a2 ; RV32I-NEXT: not a6, a2
; RV32I-NEXT: srl a1, a1, a5 ; RV32I-NEXT: srl a1, a1, a6
; RV32I-NEXT: or a3, a6, a1 ; RV32I-NEXT: or a3, a5, a1
; RV32I-NEXT: sll a0, a0, a2 ; RV32I-NEXT: sll a0, a0, a2
; RV32I-NEXT: srli a1, a4, 1 ; RV32I-NEXT: srli a1, a4, 1
; RV32I-NEXT: srl a1, a1, a5 ; RV32I-NEXT: srl a1, a1, a6
; RV32I-NEXT: or a1, a0, a1 ; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBB-LABEL: rol_i64: ; RV32ZBB-LABEL: rol_i64:
; RV32ZBB: # %bb.0: ; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: srli a3, a2, 5 ; RV32ZBB-NEXT: srli a3, a2, 5
; RV32ZBB-NEXT: andi a3, a3, 1 ; RV32ZBB-NEXT: andi a3, a3, 1
; RV32ZBB-NEXT: mv a4, a1 ; RV32ZBB-NEXT: mv a4, a1
; RV32ZBB-NEXT: bnez a3, .LBB7_2 ; RV32ZBB-NEXT: bnez a3, .LBB7_2
; RV32ZBB-NEXT: # %bb.1: ; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: mv a4, a0 ; RV32ZBB-NEXT: mv a4, a0
; RV32ZBB-NEXT: .LBB7_2: ; RV32ZBB-NEXT: .LBB7_2:
; RV32ZBB-NEXT: sll a6, a4, a2 ; RV32ZBB-NEXT: sll a5, a4, a2
; RV32ZBB-NEXT: bnez a3, .LBB7_4 ; RV32ZBB-NEXT: bnez a3, .LBB7_4
; RV32ZBB-NEXT: # %bb.3: ; RV32ZBB-NEXT: # %bb.3:
; RV32ZBB-NEXT: mv a0, a1 ; RV32ZBB-NEXT: mv a0, a1
; RV32ZBB-NEXT: .LBB7_4: ; RV32ZBB-NEXT: .LBB7_4:
; RV32ZBB-NEXT: srli a1, a0, 1 ; RV32ZBB-NEXT: srli a1, a0, 1
; RV32ZBB-NEXT: not a5, a2 ; RV32ZBB-NEXT: not a6, a2
; RV32ZBB-NEXT: srl a1, a1, a5 ; RV32ZBB-NEXT: srl a1, a1, a6
; RV32ZBB-NEXT: or a3, a6, a1 ; RV32ZBB-NEXT: or a3, a5, a1
; RV32ZBB-NEXT: sll a0, a0, a2 ; RV32ZBB-NEXT: sll a0, a0, a2
; RV32ZBB-NEXT: srli a1, a4, 1 ; RV32ZBB-NEXT: srli a1, a4, 1
; RV32ZBB-NEXT: srl a1, a1, a5 ; RV32ZBB-NEXT: srl a1, a1, a6
; RV32ZBB-NEXT: or a1, a0, a1 ; RV32ZBB-NEXT: or a1, a0, a1
; RV32ZBB-NEXT: mv a0, a3 ; RV32ZBB-NEXT: mv a0, a3
; RV32ZBB-NEXT: ret ; RV32ZBB-NEXT: ret
; ;
; RV32ZBP-LABEL: rol_i64: ; RV32ZBP-LABEL: rol_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: srli a3, a2, 5 ; RV32ZBP-NEXT: srli a3, a2, 5
; RV32ZBP-NEXT: andi a3, a3, 1 ; RV32ZBP-NEXT: andi a3, a3, 1
; RV32ZBP-NEXT: mv a4, a1 ; RV32ZBP-NEXT: mv a4, a1
; RV32ZBP-NEXT: bnez a3, .LBB7_2 ; RV32ZBP-NEXT: bnez a3, .LBB7_2
; RV32ZBP-NEXT: # %bb.1: ; RV32ZBP-NEXT: # %bb.1:
; RV32ZBP-NEXT: mv a4, a0 ; RV32ZBP-NEXT: mv a4, a0
; RV32ZBP-NEXT: .LBB7_2: ; RV32ZBP-NEXT: .LBB7_2:
; RV32ZBP-NEXT: sll a6, a4, a2 ; RV32ZBP-NEXT: sll a5, a4, a2
; RV32ZBP-NEXT: bnez a3, .LBB7_4 ; RV32ZBP-NEXT: bnez a3, .LBB7_4
; RV32ZBP-NEXT: # %bb.3: ; RV32ZBP-NEXT: # %bb.3:
; RV32ZBP-NEXT: mv a0, a1 ; RV32ZBP-NEXT: mv a0, a1
; RV32ZBP-NEXT: .LBB7_4: ; RV32ZBP-NEXT: .LBB7_4:
; RV32ZBP-NEXT: srli a1, a0, 1 ; RV32ZBP-NEXT: srli a1, a0, 1
; RV32ZBP-NEXT: not a5, a2 ; RV32ZBP-NEXT: not a6, a2
; RV32ZBP-NEXT: srl a1, a1, a5 ; RV32ZBP-NEXT: srl a1, a1, a6
; RV32ZBP-NEXT: or a3, a6, a1 ; RV32ZBP-NEXT: or a3, a5, a1
; RV32ZBP-NEXT: sll a0, a0, a2 ; RV32ZBP-NEXT: sll a0, a0, a2
; RV32ZBP-NEXT: srli a1, a4, 1 ; RV32ZBP-NEXT: srli a1, a4, 1
; RV32ZBP-NEXT: srl a1, a1, a5 ; RV32ZBP-NEXT: srl a1, a1, a6
; RV32ZBP-NEXT: or a1, a0, a1 ; RV32ZBP-NEXT: or a1, a0, a1
; RV32ZBP-NEXT: mv a0, a3 ; RV32ZBP-NEXT: mv a0, a3
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%or = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %b) %or = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %b)
ret i64 %or ret i64 %or
} }
declare i32 @llvm.fshr.i32(i32, i32, i32) declare i32 @llvm.fshr.i32(i32, i32, i32)
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llvm/test/CodeGen/RISCV/rv32zbb.ll

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; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: srli a0, a1, 1 ; RV32I-NEXT: srli a0, a1, 1
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 8 ; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: srli a1, a0, 16
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s5, a2, 1365 ; RV32I-NEXT: addi s4, a2, 1365
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s1, a1, 819 ; RV32I-NEXT: addi s5, a1, 819
; RV32I-NEXT: and a1, a0, s1 ; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s6, a1, -241 ; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s0, a1, 257 ; RV32I-NEXT: addi s3, a1, 257
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: srli a0, s4, 1 ; RV32I-NEXT: srli a0, s2, 1
; RV32I-NEXT: or a0, s4, a0 ; RV32I-NEXT: or a0, s2, a0
; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 8 ; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: srli a1, a0, 16
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a0, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s1 ; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s1 ; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: bnez s3, .LBB1_2 ; RV32I-NEXT: bnez s0, .LBB1_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32 ; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB1_3 ; RV32I-NEXT: j .LBB1_3
; RV32I-NEXT: .LBB1_2: ; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: srli a0, s2, 24 ; RV32I-NEXT: srli a0, s1, 24
; RV32I-NEXT: .LBB1_3: ; RV32I-NEXT: .LBB1_3:
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
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; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1 ; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: not a1, s4 ; RV32I-NEXT: not a1, s2
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s5, a2, 1365 ; RV32I-NEXT: addi s4, a2, 1365
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819 ; RV32I-NEXT: addi s5, a1, 819
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s6, a1, -241 ; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257 ; RV32I-NEXT: addi s3, a1, 257
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a0, s3, -1 ; RV32I-NEXT: addi a0, s1, -1
; RV32I-NEXT: not a1, s3 ; RV32I-NEXT: not a1, s1
; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, s5 ; RV32I-NEXT: and a1, a1, s4
; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s5
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s5
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6 ; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: bnez s4, .LBB3_2 ; RV32I-NEXT: bnez s2, .LBB3_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: addi a0, a0, 32 ; RV32I-NEXT: addi a0, a0, 32
; RV32I-NEXT: j .LBB3_3 ; RV32I-NEXT: j .LBB3_3
; RV32I-NEXT: .LBB3_2: ; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: srli a0, s2, 24 ; RV32I-NEXT: srli a0, s0, 24
; RV32I-NEXT: .LBB3_3: ; RV32I-NEXT: .LBB3_3:
; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
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; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: srli a0, a1, 1 ; RV32I-NEXT: srli a0, a1, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s3, a2, 1365 ; RV32I-NEXT: addi s2, a2, 1365
; RV32I-NEXT: and a0, a0, s3 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: sub a0, a1, a0 ; RV32I-NEXT: sub a0, a1, a0
; RV32I-NEXT: lui a1, 209715 ; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi s0, a1, 819 ; RV32I-NEXT: addi s3, a1, 819
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s3
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 61681 ; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s4, a1, -241 ; RV32I-NEXT: addi s4, a1, -241
; RV32I-NEXT: and a0, a0, s4 ; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257 ; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli s5, a0, 24 ; RV32I-NEXT: srli s5, a0, 24
; RV32I-NEXT: srli a0, s2, 1 ; RV32I-NEXT: srli a0, s0, 1
; RV32I-NEXT: and a0, a0, s3 ; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: sub a0, s2, a0 ; RV32I-NEXT: sub a0, s0, a0
; RV32I-NEXT: and a1, a0, s0 ; RV32I-NEXT: and a1, a0, s3
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s4 ; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3@plt ; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: add a0, a0, s5 ; RV32I-NEXT: add a0, a0, s5
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llvm/test/CodeGen/RISCV/rv32zbp.ll

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define i64 @gorc1_i64(i64 %a) nounwind { define i64 @gorc1_i64(i64 %a) nounwind {
; RV32I-LABEL: gorc1_i64: ; RV32I-LABEL: gorc1_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 1 ; RV32I-NEXT: slli a2, a0, 1
; RV32I-NEXT: slli a3, a1, 1 ; RV32I-NEXT: slli a3, a1, 1
; RV32I-NEXT: lui a4, 699051 ; RV32I-NEXT: lui a4, 699051
; RV32I-NEXT: addi a4, a4, -1366 ; RV32I-NEXT: addi a4, a4, -1366
; RV32I-NEXT: and a6, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 1 ; RV32I-NEXT: srli a4, a1, 1
; RV32I-NEXT: srli a5, a0, 1 ; RV32I-NEXT: srli a5, a0, 1
; RV32I-NEXT: lui a3, 349525 ; RV32I-NEXT: lui a6, 349525
; RV32I-NEXT: addi a3, a3, 1365 ; RV32I-NEXT: addi a6, a6, 1365
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: gorc1_i64: ; RV32ZBP-LABEL: gorc1_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.p a0, a0 ; RV32ZBP-NEXT: orc.p a0, a0
; RV32ZBP-NEXT: orc.p a1, a1 ; RV32ZBP-NEXT: orc.p a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i64 %a, 1 %and = shl i64 %a, 1
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define i64 @gorc2_i64(i64 %a) nounwind { define i64 @gorc2_i64(i64 %a) nounwind {
; RV32I-LABEL: gorc2_i64: ; RV32I-LABEL: gorc2_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 2 ; RV32I-NEXT: slli a2, a0, 2
; RV32I-NEXT: slli a3, a1, 2 ; RV32I-NEXT: slli a3, a1, 2
; RV32I-NEXT: lui a4, 838861 ; RV32I-NEXT: lui a4, 838861
; RV32I-NEXT: addi a4, a4, -820 ; RV32I-NEXT: addi a4, a4, -820
; RV32I-NEXT: and a6, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 2 ; RV32I-NEXT: srli a4, a1, 2
; RV32I-NEXT: srli a5, a0, 2 ; RV32I-NEXT: srli a5, a0, 2
; RV32I-NEXT: lui a3, 209715 ; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a3, a3, 819 ; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: gorc2_i64: ; RV32ZBP-LABEL: gorc2_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.n a0, a0 ; RV32ZBP-NEXT: orc2.n a0, a0
; RV32ZBP-NEXT: orc2.n a1, a1 ; RV32ZBP-NEXT: orc2.n a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i64 %a, 2 %and = shl i64 %a, 2
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define i64 @gorc3_i64(i64 %a) nounwind { define i64 @gorc3_i64(i64 %a) nounwind {
; RV32I-LABEL: gorc3_i64: ; RV32I-LABEL: gorc3_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a1, 1 ; RV32I-NEXT: slli a2, a1, 1
; RV32I-NEXT: slli a3, a0, 1 ; RV32I-NEXT: slli a3, a0, 1
; RV32I-NEXT: lui a4, 699051 ; RV32I-NEXT: lui a4, 699051
; RV32I-NEXT: addi a4, a4, -1366 ; RV32I-NEXT: addi a4, a4, -1366
; RV32I-NEXT: and a6, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a0, 1 ; RV32I-NEXT: srli a4, a0, 1
; RV32I-NEXT: srli a5, a1, 1 ; RV32I-NEXT: srli a5, a1, 1
; RV32I-NEXT: lui a3, 349525 ; RV32I-NEXT: lui a6, 349525
; RV32I-NEXT: addi a3, a3, 1365 ; RV32I-NEXT: addi a6, a6, 1365
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a0, a3, a0 ; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a1, a5, a1 ; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a6 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: slli a2, a0, 2 ; RV32I-NEXT: slli a2, a0, 2
; RV32I-NEXT: slli a3, a1, 2 ; RV32I-NEXT: slli a3, a1, 2
; RV32I-NEXT: lui a4, 838861 ; RV32I-NEXT: lui a4, 838861
; RV32I-NEXT: addi a4, a4, -820 ; RV32I-NEXT: addi a4, a4, -820
; RV32I-NEXT: and a6, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 2 ; RV32I-NEXT: srli a4, a1, 2
; RV32I-NEXT: srli a5, a0, 2 ; RV32I-NEXT: srli a5, a0, 2
; RV32I-NEXT: lui a3, 209715 ; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a3, a3, 819 ; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: gorc3_i64: ; RV32ZBP-LABEL: gorc3_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.n a0, a0 ; RV32ZBP-NEXT: orc.n a0, a0
; RV32ZBP-NEXT: orc.n a1, a1 ; RV32ZBP-NEXT: orc.n a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
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define i64 @gorc4_i64(i64 %a) nounwind { define i64 @gorc4_i64(i64 %a) nounwind {
; RV32I-LABEL: gorc4_i64: ; RV32I-LABEL: gorc4_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 4 ; RV32I-NEXT: slli a2, a0, 4
; RV32I-NEXT: slli a3, a1, 4 ; RV32I-NEXT: slli a3, a1, 4
; RV32I-NEXT: lui a4, 986895 ; RV32I-NEXT: lui a4, 986895
; RV32I-NEXT: addi a4, a4, 240 ; RV32I-NEXT: addi a4, a4, 240
; RV32I-NEXT: and a6, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 4 ; RV32I-NEXT: srli a4, a1, 4
; RV32I-NEXT: srli a5, a0, 4 ; RV32I-NEXT: srli a5, a0, 4
; RV32I-NEXT: lui a3, 61681 ; RV32I-NEXT: lui a6, 61681
; RV32I-NEXT: addi a3, a3, -241 ; RV32I-NEXT: addi a6, a6, -241
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: gorc4_i64: ; RV32ZBP-LABEL: gorc4_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc4.b a0, a0 ; RV32ZBP-NEXT: orc4.b a0, a0
; RV32ZBP-NEXT: orc4.b a1, a1 ; RV32ZBP-NEXT: orc4.b a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i64 %a, 4 %and = shl i64 %a, 4
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define i64 @gorc5_i64(i64 %a) nounwind { define i64 @gorc5_i64(i64 %a) nounwind {
; RV32I-LABEL: gorc5_i64: ; RV32I-LABEL: gorc5_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a1, 1 ; RV32I-NEXT: slli a2, a1, 1
; RV32I-NEXT: slli a3, a0, 1 ; RV32I-NEXT: slli a3, a0, 1
; RV32I-NEXT: lui a4, 699051 ; RV32I-NEXT: lui a4, 699051
; RV32I-NEXT: addi a4, a4, -1366 ; RV32I-NEXT: addi a4, a4, -1366
; RV32I-NEXT: and a6, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a0, 1 ; RV32I-NEXT: srli a4, a0, 1
; RV32I-NEXT: srli a5, a1, 1 ; RV32I-NEXT: srli a5, a1, 1
; RV32I-NEXT: lui a3, 349525 ; RV32I-NEXT: lui a6, 349525
; RV32I-NEXT: addi a3, a3, 1365 ; RV32I-NEXT: addi a6, a6, 1365
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a0, a3, a0 ; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a1, a5, a1 ; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a6 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: slli a2, a0, 4 ; RV32I-NEXT: slli a2, a0, 4
; RV32I-NEXT: slli a3, a1, 4 ; RV32I-NEXT: slli a3, a1, 4
; RV32I-NEXT: lui a4, 986895 ; RV32I-NEXT: lui a4, 986895
; RV32I-NEXT: addi a4, a4, 240 ; RV32I-NEXT: addi a4, a4, 240
; RV32I-NEXT: and a6, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 4 ; RV32I-NEXT: srli a4, a1, 4
; RV32I-NEXT: srli a5, a0, 4 ; RV32I-NEXT: srli a5, a0, 4
; RV32I-NEXT: lui a3, 61681 ; RV32I-NEXT: lui a6, 61681
; RV32I-NEXT: addi a3, a3, -241 ; RV32I-NEXT: addi a6, a6, -241
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: gorc5_i64: ; RV32ZBP-LABEL: gorc5_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: gorci a0, a0, 5 ; RV32ZBP-NEXT: gorci a0, a0, 5
; RV32ZBP-NEXT: gorci a1, a1, 5 ; RV32ZBP-NEXT: gorci a1, a1, 5
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
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define i64 @gorc6_i64(i64 %a) nounwind { define i64 @gorc6_i64(i64 %a) nounwind {
; RV32I-LABEL: gorc6_i64: ; RV32I-LABEL: gorc6_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a1, 2 ; RV32I-NEXT: slli a2, a1, 2
; RV32I-NEXT: slli a3, a0, 2 ; RV32I-NEXT: slli a3, a0, 2
; RV32I-NEXT: lui a4, 838861 ; RV32I-NEXT: lui a4, 838861
; RV32I-NEXT: addi a4, a4, -820 ; RV32I-NEXT: addi a4, a4, -820
; RV32I-NEXT: and a6, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a0, 2 ; RV32I-NEXT: srli a4, a0, 2
; RV32I-NEXT: srli a5, a1, 2 ; RV32I-NEXT: srli a5, a1, 2
; RV32I-NEXT: lui a3, 209715 ; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a3, a3, 819 ; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a0, a3, a0 ; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a1, a5, a1 ; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a6 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: slli a2, a0, 4 ; RV32I-NEXT: slli a2, a0, 4
; RV32I-NEXT: slli a3, a1, 4 ; RV32I-NEXT: slli a3, a1, 4
; RV32I-NEXT: lui a4, 986895 ; RV32I-NEXT: lui a4, 986895
; RV32I-NEXT: addi a4, a4, 240 ; RV32I-NEXT: addi a4, a4, 240
; RV32I-NEXT: and a6, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 4 ; RV32I-NEXT: srli a4, a1, 4
; RV32I-NEXT: srli a5, a0, 4 ; RV32I-NEXT: srli a5, a0, 4
; RV32I-NEXT: lui a3, 61681 ; RV32I-NEXT: lui a6, 61681
; RV32I-NEXT: addi a3, a3, -241 ; RV32I-NEXT: addi a6, a6, -241
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: gorc6_i64: ; RV32ZBP-LABEL: gorc6_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.b a0, a0 ; RV32ZBP-NEXT: orc2.b a0, a0
; RV32ZBP-NEXT: orc2.b a1, a1 ; RV32ZBP-NEXT: orc2.b a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 2 %and1 = shl i64 %a, 2
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define i64 @gorc7_i64(i64 %a) nounwind { define i64 @gorc7_i64(i64 %a) nounwind {
; RV32I-LABEL: gorc7_i64: ; RV32I-LABEL: gorc7_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 1 ; RV32I-NEXT: slli a2, a0, 1
; RV32I-NEXT: slli a3, a1, 1 ; RV32I-NEXT: slli a3, a1, 1
; RV32I-NEXT: lui a4, 699051 ; RV32I-NEXT: lui a4, 699051
; RV32I-NEXT: addi a4, a4, -1366 ; RV32I-NEXT: addi a4, a4, -1366
; RV32I-NEXT: and a6, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 1 ; RV32I-NEXT: srli a4, a1, 1
; RV32I-NEXT: srli a5, a0, 1 ; RV32I-NEXT: srli a5, a0, 1
; RV32I-NEXT: lui a3, 349525 ; RV32I-NEXT: lui a6, 349525
; RV32I-NEXT: addi a3, a3, 1365 ; RV32I-NEXT: addi a6, a6, 1365
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: slli a2, a1, 2 ; RV32I-NEXT: slli a2, a1, 2
; RV32I-NEXT: slli a3, a0, 2 ; RV32I-NEXT: slli a3, a0, 2
; RV32I-NEXT: lui a4, 838861 ; RV32I-NEXT: lui a4, 838861
; RV32I-NEXT: addi a4, a4, -820 ; RV32I-NEXT: addi a4, a4, -820
; RV32I-NEXT: and a6, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a0, 2 ; RV32I-NEXT: srli a4, a0, 2
; RV32I-NEXT: srli a5, a1, 2 ; RV32I-NEXT: srli a5, a1, 2
; RV32I-NEXT: lui a3, 209715 ; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a3, a3, 819 ; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a0, a3, a0 ; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a1, a5, a1 ; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a6 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: slli a2, a0, 4 ; RV32I-NEXT: slli a2, a0, 4
; RV32I-NEXT: slli a3, a1, 4 ; RV32I-NEXT: slli a3, a1, 4
; RV32I-NEXT: lui a4, 986895 ; RV32I-NEXT: lui a4, 986895
; RV32I-NEXT: addi a4, a4, 240 ; RV32I-NEXT: addi a4, a4, 240
; RV32I-NEXT: and a6, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 4 ; RV32I-NEXT: srli a4, a1, 4
; RV32I-NEXT: srli a5, a0, 4 ; RV32I-NEXT: srli a5, a0, 4
; RV32I-NEXT: lui a3, 61681 ; RV32I-NEXT: lui a6, 61681
; RV32I-NEXT: addi a3, a3, -241 ; RV32I-NEXT: addi a6, a6, -241
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: gorc7_i64: ; RV32ZBP-LABEL: gorc7_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.b a0, a0 ; RV32ZBP-NEXT: orc.b a0, a0
; RV32ZBP-NEXT: orc.b a1, a1 ; RV32ZBP-NEXT: orc.b a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
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define i64 @gorc8_i64(i64 %a) nounwind { define i64 @gorc8_i64(i64 %a) nounwind {
; RV32I-LABEL: gorc8_i64: ; RV32I-LABEL: gorc8_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 8 ; RV32I-NEXT: slli a2, a0, 8
; RV32I-NEXT: slli a3, a1, 8 ; RV32I-NEXT: slli a3, a1, 8
; RV32I-NEXT: lui a4, 1044496 ; RV32I-NEXT: lui a4, 1044496
; RV32I-NEXT: addi a4, a4, -256 ; RV32I-NEXT: addi a4, a4, -256
; RV32I-NEXT: and a6, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 8 ; RV32I-NEXT: srli a4, a1, 8
; RV32I-NEXT: srli a5, a0, 8 ; RV32I-NEXT: srli a5, a0, 8
; RV32I-NEXT: lui a3, 4080 ; RV32I-NEXT: lui a6, 4080
; RV32I-NEXT: addi a3, a3, 255 ; RV32I-NEXT: addi a6, a6, 255
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: gorc8_i64: ; RV32ZBP-LABEL: gorc8_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc8.h a0, a0 ; RV32ZBP-NEXT: orc8.h a0, a0
; RV32ZBP-NEXT: orc8.h a1, a1 ; RV32ZBP-NEXT: orc8.h a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = shl i64 %a, 8 %and = shl i64 %a, 8
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; gorc2, gorc2 -> gorc2 ; gorc2, gorc2 -> gorc2
define i64 @gorc2b_i64(i64 %a) nounwind { define i64 @gorc2b_i64(i64 %a) nounwind {
; RV32I-LABEL: gorc2b_i64: ; RV32I-LABEL: gorc2b_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a1, 2 ; RV32I-NEXT: slli a2, a1, 2
; RV32I-NEXT: slli a3, a0, 2 ; RV32I-NEXT: slli a3, a0, 2
; RV32I-NEXT: lui a4, 838861 ; RV32I-NEXT: lui a4, 838861
; RV32I-NEXT: addi a4, a4, -820 ; RV32I-NEXT: addi a4, a4, -820
; RV32I-NEXT: and a6, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a7, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a5, a0, 2 ; RV32I-NEXT: srli a5, a0, 2
; RV32I-NEXT: srli a3, a1, 2 ; RV32I-NEXT: srli a6, a1, 2
; RV32I-NEXT: lui a2, 209715 ; RV32I-NEXT: lui a7, 209715
; RV32I-NEXT: addi a2, a2, 819 ; RV32I-NEXT: addi a7, a7, 819
; RV32I-NEXT: and a3, a3, a2 ; RV32I-NEXT: and a6, a6, a7
; RV32I-NEXT: and a5, a5, a2 ; RV32I-NEXT: and a5, a5, a7
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a6, a1
; RV32I-NEXT: or a1, a1, a7 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a6 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: slli a3, a0, 2 ; RV32I-NEXT: slli a2, a0, 2
; RV32I-NEXT: slli a5, a1, 2 ; RV32I-NEXT: slli a3, a1, 2
; RV32I-NEXT: and a6, a5, a4
; RV32I-NEXT: and a3, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 2 ; RV32I-NEXT: srli a4, a1, 2
; RV32I-NEXT: srli a5, a0, 2 ; RV32I-NEXT: srli a5, a0, 2
; RV32I-NEXT: and a5, a5, a2 ; RV32I-NEXT: and a5, a5, a7
; RV32I-NEXT: and a2, a4, a2 ; RV32I-NEXT: and a4, a4, a7
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: gorc2b_i64: ; RV32ZBP-LABEL: gorc2b_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc2.n a0, a0 ; RV32ZBP-NEXT: orc2.n a0, a0
; RV32ZBP-NEXT: orc2.n a1, a1 ; RV32ZBP-NEXT: orc2.n a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 2 %and1 = shl i64 %a, 2
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; gorc1, gorc2, gorc1 -> gorc2 ; gorc1, gorc2, gorc1 -> gorc2
define i64 @gorc3b_i64(i64 %a) nounwind { define i64 @gorc3b_i64(i64 %a) nounwind {
; RV32I-LABEL: gorc3b_i64: ; RV32I-LABEL: gorc3b_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a0, 1 ; RV32I-NEXT: slli a2, a0, 1
; RV32I-NEXT: slli a3, a1, 1 ; RV32I-NEXT: slli a3, a1, 1
; RV32I-NEXT: lui a4, 699051 ; RV32I-NEXT: lui a4, 699051
; RV32I-NEXT: addi a4, a4, -1366 ; RV32I-NEXT: addi a4, a4, -1366
; RV32I-NEXT: and a6, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a7, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a5, a1, 1 ; RV32I-NEXT: srli a5, a1, 1
; RV32I-NEXT: srli a3, a0, 1 ; RV32I-NEXT: srli a6, a0, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a7, 349525
; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: addi a7, a7, 1365
; RV32I-NEXT: and a3, a3, a2 ; RV32I-NEXT: and a6, a6, a7
; RV32I-NEXT: and a5, a5, a2 ; RV32I-NEXT: and a5, a5, a7
; RV32I-NEXT: or a1, a5, a1 ; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: or a0, a3, a0 ; RV32I-NEXT: or a0, a6, a0
; RV32I-NEXT: or a0, a0, a7 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: slli a6, a1, 2 ; RV32I-NEXT: slli a2, a1, 2
; RV32I-NEXT: slli a5, a0, 2 ; RV32I-NEXT: slli a3, a0, 2
; RV32I-NEXT: lui a3, 838861 ; RV32I-NEXT: lui a5, 838861
; RV32I-NEXT: addi a3, a3, -820 ; RV32I-NEXT: addi a5, a5, -820
; RV32I-NEXT: and a7, a5, a3
; RV32I-NEXT: and a6, a6, a3
; RV32I-NEXT: srli t0, a0, 2
; RV32I-NEXT: srli a3, a1, 2
; RV32I-NEXT: lui a5, 209715
; RV32I-NEXT: addi a5, a5, 819
; RV32I-NEXT: and a3, a3, a5 ; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: and a5, t0, a5 ; RV32I-NEXT: and a2, a2, a5
; RV32I-NEXT: srli a5, a0, 2
; RV32I-NEXT: srli a6, a1, 2
; RV32I-NEXT: lui t0, 209715
; RV32I-NEXT: addi t0, t0, 819
; RV32I-NEXT: and a6, a6, t0
; RV32I-NEXT: and a5, a5, t0
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a6, a1
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a7 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: slli a3, a0, 1 ; RV32I-NEXT: slli a2, a0, 1
; RV32I-NEXT: slli a5, a1, 1 ; RV32I-NEXT: slli a3, a1, 1
; RV32I-NEXT: and a6, a5, a4
; RV32I-NEXT: and a3, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a4, a1, 1 ; RV32I-NEXT: srli a4, a1, 1
; RV32I-NEXT: srli a5, a0, 1 ; RV32I-NEXT: srli a5, a0, 1
; RV32I-NEXT: and a5, a5, a2 ; RV32I-NEXT: and a5, a5, a7
; RV32I-NEXT: and a2, a4, a2 ; RV32I-NEXT: and a4, a4, a7
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: gorc3b_i64: ; RV32ZBP-LABEL: gorc3b_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: orc.n a0, a0 ; RV32ZBP-NEXT: orc.n a0, a0
; RV32ZBP-NEXT: orc.n a1, a1 ; RV32ZBP-NEXT: orc.n a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
▲ Show 20 Lines • Show All 821 Lines • ▼ Show 20 Lines
; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: srli a1, a1, 1 ; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: lui a5, 349525 ; RV32I-NEXT: lui a5, 349525
; RV32I-NEXT: addi a5, a5, 1365 ; RV32I-NEXT: addi a5, a5, 1365
; RV32I-NEXT: and a1, a1, a5 ; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: and a0, a0, a5 ; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: slli a6, a1, 2 ; RV32I-NEXT: slli a2, a1, 2
; RV32I-NEXT: slli a3, a0, 2 ; RV32I-NEXT: slli a3, a0, 2
; RV32I-NEXT: lui a2, 838861 ; RV32I-NEXT: lui a6, 838861
; RV32I-NEXT: addi a2, a2, -820 ; RV32I-NEXT: addi a6, a6, -820
; RV32I-NEXT: and a7, a3, a2 ; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: and a2, a6, a2 ; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: srli a1, a1, 2 ; RV32I-NEXT: srli a1, a1, 2
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: lui a3, 209715 ; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a3, a3, 819 ; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a6
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: or a0, a7, a0 ; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: slli a2, a0, 1 ; RV32I-NEXT: slli a2, a0, 1
; RV32I-NEXT: slli a3, a1, 1 ; RV32I-NEXT: slli a3, a1, 1
; RV32I-NEXT: and a3, a3, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: srli a1, a1, 1 ; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: and a1, a1, a5 ; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: and a0, a0, a5 ; RV32I-NEXT: and a0, a0, a5
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; RV32I-NEXT: srli a1, a1, 1 ; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: lui a5, 349525 ; RV32I-NEXT: lui a5, 349525
; RV32I-NEXT: addi a5, a5, 1365 ; RV32I-NEXT: addi a5, a5, 1365
; RV32I-NEXT: and a0, a0, a5 ; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: and a1, a1, a5 ; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: or a0, a3, a0 ; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: slli a6, a0, 2 ; RV32I-NEXT: slli a2, a0, 2
; RV32I-NEXT: slli a3, a1, 2 ; RV32I-NEXT: slli a3, a1, 2
; RV32I-NEXT: lui a2, 838861 ; RV32I-NEXT: lui a6, 838861
; RV32I-NEXT: addi a2, a2, -820 ; RV32I-NEXT: addi a6, a6, -820
; RV32I-NEXT: and a7, a3, a2 ; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: and a6, a6, a2 ; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: srli a1, a1, 2 ; RV32I-NEXT: srli a1, a1, 2
; RV32I-NEXT: lui a3, 209715 ; RV32I-NEXT: lui a7, 209715
; RV32I-NEXT: addi a3, a3, 819 ; RV32I-NEXT: addi a7, a7, 819
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a7
; RV32I-NEXT: or t0, a6, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a7, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: slli a6, a1, 1 ; RV32I-NEXT: slli a2, a1, 1
; RV32I-NEXT: slli a0, t0, 1 ; RV32I-NEXT: slli a3, a0, 1
; RV32I-NEXT: and a7, a0, a4 ; RV32I-NEXT: and a3, a3, a4
; RV32I-NEXT: and a4, a6, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: srli a1, a1, 1 ; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: srli a0, t0, 1 ; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: and a0, a0, a5 ; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: and a1, a1, a5 ; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: or a1, a4, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: or a0, a7, a0 ; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: slli a4, a0, 2 ; RV32I-NEXT: slli a2, a0, 2
; RV32I-NEXT: slli a5, a1, 2 ; RV32I-NEXT: slli a3, a1, 2
; RV32I-NEXT: and a5, a5, a2 ; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: and a2, a4, a2 ; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: srli a1, a1, 2 ; RV32I-NEXT: srli a1, a1, 2
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a7
; RV32I-NEXT: or a0, a2, a0 ; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: or a1, a5, a1 ; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: grev0_i64: ; RV32ZBP-LABEL: grev0_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and1 = shl i64 %a, 1 %and1 = shl i64 %a, 1
%shl1 = and i64 %and1, -6148914691236517206 %shl1 = and i64 %and1, -6148914691236517206
%and1b = lshr i64 %a, 1 %and1b = lshr i64 %a, 1
▲ Show 20 Lines • Show All 280 Lines • ▼ Show 20 Lines
declare i64 @llvm.bitreverse.i64(i64) declare i64 @llvm.bitreverse.i64(i64)
define i64 @bitreverse_i64(i64 %a) nounwind { define i64 @bitreverse_i64(i64 %a) nounwind {
; RV32I-LABEL: bitreverse_i64: ; RV32I-LABEL: bitreverse_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a2, a1, 8 ; RV32I-NEXT: srli a2, a1, 8
; RV32I-NEXT: lui a3, 16 ; RV32I-NEXT: lui a3, 16
; RV32I-NEXT: addi a7, a3, -256 ; RV32I-NEXT: addi a3, a3, -256
; RV32I-NEXT: and a2, a2, a7 ; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: srli a4, a1, 24 ; RV32I-NEXT: srli a4, a1, 24
; RV32I-NEXT: or a2, a2, a4 ; RV32I-NEXT: or a2, a2, a4
; RV32I-NEXT: slli a4, a1, 8 ; RV32I-NEXT: slli a4, a1, 8
; RV32I-NEXT: lui a6, 4080 ; RV32I-NEXT: lui a5, 4080
; RV32I-NEXT: and a4, a4, a6 ; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: or a1, a1, a4 ; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: srli a2, a1, 4 ; RV32I-NEXT: srli a2, a1, 4
; RV32I-NEXT: lui a4, 61681 ; RV32I-NEXT: lui a4, 61681
; RV32I-NEXT: addi a4, a4, -241 ; RV32I-NEXT: addi a4, a4, -241
; RV32I-NEXT: and a2, a2, a4 ; RV32I-NEXT: and a2, a2, a4
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: slli a1, a1, 4 ; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: srli a2, a1, 2 ; RV32I-NEXT: srli a2, a1, 2
; RV32I-NEXT: lui a5, 209715 ; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a5, a5, 819 ; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a2, a2, a5 ; RV32I-NEXT: and a2, a2, a6
; RV32I-NEXT: and a1, a1, a5 ; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: slli a1, a1, 2 ; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: srli a2, a1, 1 ; RV32I-NEXT: srli a2, a1, 1
; RV32I-NEXT: lui a3, 349525 ; RV32I-NEXT: lui a7, 349525
; RV32I-NEXT: addi a3, a3, 1365 ; RV32I-NEXT: addi a7, a7, 1365
; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: and a2, a2, a7
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: or t0, a2, a1 ; RV32I-NEXT: or a2, a2, a1
; RV32I-NEXT: srli a1, a0, 8 ; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: and a1, a1, a7 ; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: srli a2, a0, 24 ; RV32I-NEXT: srli a3, a0, 24
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: slli a2, a0, 8 ; RV32I-NEXT: slli a3, a0, 8
; RV32I-NEXT: and a2, a2, a6 ; RV32I-NEXT: and a3, a3, a5
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: slli a0, a0, 4 ; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: srli a1, a0, 2
; RV32I-NEXT: and a1, a1, a5 ; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: and a0, a0, a5 ; RV32I-NEXT: and a0, a0, a6
; RV32I-NEXT: slli a0, a0, 2 ; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a7
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a1, a1, a0 ; RV32I-NEXT: or a1, a1, a0
; RV32I-NEXT: mv a0, t0 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: bitreverse_i64: ; RV32ZBP-LABEL: bitreverse_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev a2, a1 ; RV32ZBP-NEXT: rev a2, a1
; RV32ZBP-NEXT: rev a1, a0 ; RV32ZBP-NEXT: rev a1, a0
; RV32ZBP-NEXT: mv a0, a2 ; RV32ZBP-NEXT: mv a0, a2
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines; RV32ZBP-NEXT: ret
ret i32 %2 ret i32 %2
} }
define i64 @bitreverse_bswap_i64(i64 %a) { define i64 @bitreverse_bswap_i64(i64 %a) {
; RV32I-LABEL: bitreverse_bswap_i64: ; RV32I-LABEL: bitreverse_bswap_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a3, a1, 8 ; RV32I-NEXT: srli a3, a1, 8
; RV32I-NEXT: lui a2, 16 ; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a7, a2, -256 ; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a3, a3, a7 ; RV32I-NEXT: and a3, a3, a2
; RV32I-NEXT: srli a4, a1, 24 ; RV32I-NEXT: srli a4, a1, 24
; RV32I-NEXT: or a4, a3, a4 ; RV32I-NEXT: or a4, a3, a4
; RV32I-NEXT: slli a5, a1, 8 ; RV32I-NEXT: slli a5, a1, 8
; RV32I-NEXT: lui a6, 4080 ; RV32I-NEXT: lui a3, 4080
; RV32I-NEXT: and a5, a5, a6 ; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: or a1, a1, a5 ; RV32I-NEXT: or a1, a1, a5
; RV32I-NEXT: or a1, a1, a4 ; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: srli a4, a1, 4 ; RV32I-NEXT: srli a4, a1, 4
; RV32I-NEXT: lui a5, 61681 ; RV32I-NEXT: lui a5, 61681
; RV32I-NEXT: addi a5, a5, -241 ; RV32I-NEXT: addi a5, a5, -241
; RV32I-NEXT: and a4, a4, a5 ; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: and a1, a1, a5 ; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: slli a1, a1, 4 ; RV32I-NEXT: slli a1, a1, 4
; RV32I-NEXT: or a1, a4, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a4, a1, 2 ; RV32I-NEXT: srli a4, a1, 2
; RV32I-NEXT: lui a3, 209715 ; RV32I-NEXT: lui a6, 209715
; RV32I-NEXT: addi a3, a3, 819 ; RV32I-NEXT: addi a6, a6, 819
; RV32I-NEXT: and a4, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: slli a1, a1, 2 ; RV32I-NEXT: slli a1, a1, 2
; RV32I-NEXT: or a1, a4, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a4, a1, 1 ; RV32I-NEXT: srli a4, a1, 1
; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: lui a7, 349525
; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: addi a7, a7, 1365
; RV32I-NEXT: and a4, a4, a2 ; RV32I-NEXT: and a4, a4, a7
; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: or a1, a4, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: srli a4, a0, 8 ; RV32I-NEXT: srli a4, a0, 8
; RV32I-NEXT: and t0, a4, a7 ; RV32I-NEXT: and a4, a4, a2
; RV32I-NEXT: srli a4, a0, 24 ; RV32I-NEXT: srli t0, a0, 24
; RV32I-NEXT: or t0, t0, a4 ; RV32I-NEXT: or a4, a4, t0
; RV32I-NEXT: slli a4, a0, 8 ; RV32I-NEXT: slli t0, a0, 8
; RV32I-NEXT: and a4, a4, a6 ; RV32I-NEXT: and t0, t0, a3
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: or a0, a0, t0 ; RV32I-NEXT: or a0, a0, t0
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: srli a4, a0, 4 ; RV32I-NEXT: srli a4, a0, 4
; RV32I-NEXT: and a4, a4, a5 ; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: and a0, a0, a5 ; RV32I-NEXT: and a0, a0, a5
; RV32I-NEXT: slli a0, a0, 4 ; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: or a0, a4, a0 ; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: srli a4, a0, 2 ; RV32I-NEXT: srli a4, a0, 2
; RV32I-NEXT: and a4, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a0, a0, a6
; RV32I-NEXT: slli a0, a0, 2 ; RV32I-NEXT: slli a0, a0, 2
; RV32I-NEXT: or a0, a4, a0 ; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: srli a3, a0, 1 ; RV32I-NEXT: srli a4, a0, 1
; RV32I-NEXT: and a3, a3, a2 ; RV32I-NEXT: and a4, a4, a7
; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a0, a0, a7
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: or a0, a3, a0 ; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: srli a2, a0, 8 ; RV32I-NEXT: srli a4, a0, 8
; RV32I-NEXT: and a2, a2, a7 ; RV32I-NEXT: and a4, a4, a2
; RV32I-NEXT: srli a3, a0, 24 ; RV32I-NEXT: srli a5, a0, 24
; RV32I-NEXT: or a2, a2, a3 ; RV32I-NEXT: or a4, a4, a5
; RV32I-NEXT: slli a3, a0, 8 ; RV32I-NEXT: slli a5, a0, 8
; RV32I-NEXT: and a3, a3, a6 ; RV32I-NEXT: and a5, a5, a3
; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a5
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: srli a2, a1, 8 ; RV32I-NEXT: srli a4, a1, 8
; RV32I-NEXT: and a2, a2, a7 ; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: srli a3, a1, 24 ; RV32I-NEXT: srli a4, a1, 24
; RV32I-NEXT: or a2, a2, a3 ; RV32I-NEXT: or a2, a2, a4
; RV32I-NEXT: slli a3, a1, 8 ; RV32I-NEXT: slli a4, a1, 8
; RV32I-NEXT: and a3, a3, a6 ; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: or a1, a1, a3 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: bitreverse_bswap_i64: ; RV32ZBP-LABEL: bitreverse_bswap_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: rev.b a0, a0 ; RV32ZBP-NEXT: rev.b a0, a0
Show All 36 Lines; RV32ZBP-NEXT: ret
ret i32 %or3 ret i32 %or3
} }
define i64 @shfl1_i64(i64 %a, i64 %b) nounwind { define i64 @shfl1_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: shfl1_i64: ; RV32I-LABEL: shfl1_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 629146 ; RV32I-NEXT: lui a2, 629146
; RV32I-NEXT: addi a2, a2, -1639 ; RV32I-NEXT: addi a2, a2, -1639
; RV32I-NEXT: and a6, a0, a2 ; RV32I-NEXT: and a3, a0, a2
; RV32I-NEXT: and a2, a1, a2 ; RV32I-NEXT: and a2, a1, a2
; RV32I-NEXT: slli a4, a1, 1 ; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: slli a5, a0, 1 ; RV32I-NEXT: slli a5, a0, 1
; RV32I-NEXT: lui a3, 279620 ; RV32I-NEXT: lui a6, 279620
; RV32I-NEXT: addi a3, a3, 1092 ; RV32I-NEXT: addi a6, a6, 1092
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a2, a2, a3 ; RV32I-NEXT: or a2, a2, a4
; RV32I-NEXT: or a3, a6, a5 ; RV32I-NEXT: or a3, a3, a5
; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: srli a1, a1, 1 ; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: lui a4, 139810 ; RV32I-NEXT: lui a4, 139810
; RV32I-NEXT: addi a4, a4, 546 ; RV32I-NEXT: addi a4, a4, 546
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: or a0, a3, a0 ; RV32I-NEXT: or a0, a3, a0
; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: or a1, a2, a1
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines; RV32ZBP-NEXT: ret
ret i32 %or3 ret i32 %or3
} }
define i64 @shfl2_i64(i64 %a, i64 %b) nounwind { define i64 @shfl2_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: shfl2_i64: ; RV32I-LABEL: shfl2_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 801852 ; RV32I-NEXT: lui a2, 801852
; RV32I-NEXT: addi a2, a2, 963 ; RV32I-NEXT: addi a2, a2, 963
; RV32I-NEXT: and a6, a0, a2 ; RV32I-NEXT: and a3, a0, a2
; RV32I-NEXT: and a2, a1, a2 ; RV32I-NEXT: and a2, a1, a2
; RV32I-NEXT: slli a4, a1, 2 ; RV32I-NEXT: slli a4, a1, 2
; RV32I-NEXT: slli a5, a0, 2 ; RV32I-NEXT: slli a5, a0, 2
; RV32I-NEXT: lui a3, 197379 ; RV32I-NEXT: lui a6, 197379
; RV32I-NEXT: addi a3, a3, 48 ; RV32I-NEXT: addi a6, a6, 48
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: or a2, a2, a3 ; RV32I-NEXT: or a2, a2, a4
; RV32I-NEXT: or a3, a6, a5 ; RV32I-NEXT: or a3, a3, a5
; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: srli a0, a0, 2
; RV32I-NEXT: srli a1, a1, 2 ; RV32I-NEXT: srli a1, a1, 2
; RV32I-NEXT: lui a4, 49345 ; RV32I-NEXT: lui a4, 49345
; RV32I-NEXT: addi a4, a4, -1012 ; RV32I-NEXT: addi a4, a4, -1012
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a4
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a4
; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines; RV32ZBP-NEXT: ret
ret i32 %or3 ret i32 %or3
} }
define i64 @shfl4_i64(i64 %a, i64 %b) nounwind { define i64 @shfl4_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: shfl4_i64: ; RV32I-LABEL: shfl4_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 983295 ; RV32I-NEXT: lui a2, 983295
; RV32I-NEXT: addi a2, a2, 15 ; RV32I-NEXT: addi a2, a2, 15
; RV32I-NEXT: and a6, a1, a2 ; RV32I-NEXT: and a3, a1, a2
; RV32I-NEXT: and a2, a0, a2 ; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: slli a4, a1, 4 ; RV32I-NEXT: slli a4, a1, 4
; RV32I-NEXT: slli a5, a0, 4 ; RV32I-NEXT: slli a5, a0, 4
; RV32I-NEXT: lui a3, 61441 ; RV32I-NEXT: lui a6, 61441
; RV32I-NEXT: addi a3, a3, -256 ; RV32I-NEXT: addi a6, a6, -256
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: srli a1, a1, 4 ; RV32I-NEXT: srli a1, a1, 4
; RV32I-NEXT: srli a0, a0, 4 ; RV32I-NEXT: srli a0, a0, 4
; RV32I-NEXT: lui a4, 3840 ; RV32I-NEXT: lui a6, 3840
; RV32I-NEXT: addi a4, a4, 240 ; RV32I-NEXT: addi a6, a6, 240
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a6
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: or a1, a3, a1 ; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: or a0, a5, a0 ; RV32I-NEXT: or a0, a5, a0
; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a6 ; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: shfl4_i64: ; RV32ZBP-LABEL: shfl4_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip4.h a0, a0 ; RV32ZBP-NEXT: zip4.h a0, a0
; RV32ZBP-NEXT: zip4.h a1, a1 ; RV32ZBP-NEXT: zip4.h a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
%and = and i64 %a, -1148435428713435121 %and = and i64 %a, -1148435428713435121
Show All 37 Lines; RV32ZBP-NEXT: ret
ret i32 %or3 ret i32 %or3
} }
define i64 @shfl8_i64(i64 %a, i64 %b) nounwind { define i64 @shfl8_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: shfl8_i64: ; RV32I-LABEL: shfl8_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 1044480 ; RV32I-NEXT: lui a2, 1044480
; RV32I-NEXT: addi a2, a2, 255 ; RV32I-NEXT: addi a2, a2, 255
; RV32I-NEXT: and a6, a0, a2 ; RV32I-NEXT: and a3, a0, a2
; RV32I-NEXT: and a2, a1, a2 ; RV32I-NEXT: and a2, a1, a2
; RV32I-NEXT: slli a4, a0, 8 ; RV32I-NEXT: slli a4, a0, 8
; RV32I-NEXT: slli a5, a1, 8 ; RV32I-NEXT: slli a5, a1, 8
; RV32I-NEXT: lui a3, 4080 ; RV32I-NEXT: lui a6, 4080
; RV32I-NEXT: and a5, a5, a3 ; RV32I-NEXT: and a5, a5, a6
; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: srli a1, a1, 8 ; RV32I-NEXT: srli a1, a1, 8
; RV32I-NEXT: srli a0, a0, 8 ; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: lui a4, 16 ; RV32I-NEXT: lui a6, 16
; RV32I-NEXT: addi a4, a4, -256 ; RV32I-NEXT: addi a6, a6, -256
; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: and a0, a0, a6
; RV32I-NEXT: and a1, a1, a4 ; RV32I-NEXT: and a1, a1, a6
; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: or a0, a0, a6 ; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: or a0, a3, a0 ; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: or a1, a5, a1 ; RV32I-NEXT: or a1, a5, a1
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBP-LABEL: shfl8_i64: ; RV32ZBP-LABEL: shfl8_i64:
; RV32ZBP: # %bb.0: ; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zip8 a0, a0 ; RV32ZBP-NEXT: zip8 a0, a0
; RV32ZBP-NEXT: zip8 a1, a1 ; RV32ZBP-NEXT: zip8 a1, a1
; RV32ZBP-NEXT: ret ; RV32ZBP-NEXT: ret
▲ Show 20 Lines • Show All 207 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv32zbt.ll

Show First 20 Lines • Show All 335 Lines • ▼ Show 20 Lines
; extensions introduce instructions that can match more efficiently this pattern. ; extensions introduce instructions that can match more efficiently this pattern.
declare i64 @llvm.fshl.i64(i64, i64, i64) declare i64 @llvm.fshl.i64(i64, i64, i64)
define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: fshl_i64: ; RV32I-LABEL: fshl_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: srli a5, a4, 5 ; RV32I-NEXT: srli a5, a4, 5
; RV32I-NEXT: andi a5, a5, 1 ; RV32I-NEXT: andi a6, a5, 1
; RV32I-NEXT: mv a6, a3 ; RV32I-NEXT: mv a5, a3
; RV32I-NEXT: bnez a5, .LBB13_2 ; RV32I-NEXT: bnez a6, .LBB13_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a6, a0 ; RV32I-NEXT: mv a5, a0
; RV32I-NEXT: .LBB13_2: ; RV32I-NEXT: .LBB13_2:
; RV32I-NEXT: sll a7, a6, a4 ; RV32I-NEXT: sll a7, a5, a4
; RV32I-NEXT: bnez a5, .LBB13_4 ; RV32I-NEXT: bnez a6, .LBB13_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: .LBB13_4: ; RV32I-NEXT: .LBB13_4:
; RV32I-NEXT: srli a2, a2, 1 ; RV32I-NEXT: srli a2, a2, 1
; RV32I-NEXT: not a3, a4 ; RV32I-NEXT: not a3, a4
; RV32I-NEXT: srl a2, a2, a3 ; RV32I-NEXT: srl a2, a2, a3
; RV32I-NEXT: or a2, a7, a2 ; RV32I-NEXT: or a2, a7, a2
; RV32I-NEXT: bnez a5, .LBB13_6 ; RV32I-NEXT: bnez a6, .LBB13_6
; RV32I-NEXT: # %bb.5: ; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB13_6: ; RV32I-NEXT: .LBB13_6:
; RV32I-NEXT: sll a0, a0, a4 ; RV32I-NEXT: sll a0, a0, a4
; RV32I-NEXT: srli a1, a6, 1 ; RV32I-NEXT: srli a1, a5, 1
; RV32I-NEXT: srl a1, a1, a3 ; RV32I-NEXT: srl a1, a1, a3
; RV32I-NEXT: or a1, a0, a1 ; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: fshl_i64: ; RV32ZBT-LABEL: fshl_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: srli a5, a4, 5 ; RV32ZBT-NEXT: srli a5, a4, 5
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @fshr_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: fshr_i64: ; RV32I-LABEL: fshr_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: andi a5, a4, 32 ; RV32I-NEXT: andi a5, a4, 32
; RV32I-NEXT: beqz a5, .LBB15_2 ; RV32I-NEXT: beqz a5, .LBB15_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: .LBB15_2: ; RV32I-NEXT: .LBB15_2:
; RV32I-NEXT: srl a6, a2, a4 ; RV32I-NEXT: srl a2, a2, a4
; RV32I-NEXT: beqz a5, .LBB15_4 ; RV32I-NEXT: beqz a5, .LBB15_4
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a3, a0 ; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: .LBB15_4: ; RV32I-NEXT: .LBB15_4:
; RV32I-NEXT: slli a7, a3, 1 ; RV32I-NEXT: slli a7, a3, 1
; RV32I-NEXT: not t0, a4 ; RV32I-NEXT: not a6, a4
; RV32I-NEXT: sll a2, a7, t0 ; RV32I-NEXT: sll a7, a7, a6
; RV32I-NEXT: or a6, a2, a6 ; RV32I-NEXT: or a2, a7, a2
; RV32I-NEXT: srl a3, a3, a4 ; RV32I-NEXT: srl a3, a3, a4
; RV32I-NEXT: beqz a5, .LBB15_6 ; RV32I-NEXT: beqz a5, .LBB15_6
; RV32I-NEXT: # %bb.5: ; RV32I-NEXT: # %bb.5:
; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: .LBB15_6: ; RV32I-NEXT: .LBB15_6:
; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: sll a0, a0, t0 ; RV32I-NEXT: sll a0, a0, a6
; RV32I-NEXT: or a1, a0, a3 ; RV32I-NEXT: or a1, a0, a3
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32ZBT-LABEL: fshr_i64: ; RV32ZBT-LABEL: fshr_i64:
; RV32ZBT: # %bb.0: ; RV32ZBT: # %bb.0:
; RV32ZBT-NEXT: andi a5, a4, 32 ; RV32ZBT-NEXT: andi a5, a4, 32
; RV32ZBT-NEXT: cmov a6, a5, a0, a3 ; RV32ZBT-NEXT: cmov a6, a5, a0, a3
; RV32ZBT-NEXT: cmov a2, a5, a3, a2 ; RV32ZBT-NEXT: cmov a2, a5, a3, a2
; RV32ZBT-NEXT: andi a3, a4, 31 ; RV32ZBT-NEXT: andi a3, a4, 31
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv64i-complex-float.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
; The complex floating value will be returned by a single register for LP64 ABI. ; The complex floating value will be returned by a single register for LP64 ABI.
; The test case check that the real part returned by __addsf3 will be ; The test case check that the real part returned by __addsf3 will be
; cleared upper bits by shifts to avoid corrupting the imaginary part. ; cleared upper bits by shifts to avoid corrupting the imaginary part.
define i64 @complex_float_add(i64 %a.coerce, i64 %b.coerce) nounwind { define i64 @complex_float_add(i64 %a.coerce, i64 %b.coerce) nounwind {
; CHECK-LABEL: complex_float_add: ; CHECK-LABEL: complex_float_add:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -32 ; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: srli s2, a0, 32 ; CHECK-NEXT: srli s0, a0, 32
; CHECK-NEXT: srli s1, a1, 32 ; CHECK-NEXT: srli s1, a1, 32
; CHECK-NEXT: call __addsf3@plt ; CHECK-NEXT: call __addsf3@plt
; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: mv a0, s2 ; CHECK-NEXT: mv a0, s0
; CHECK-NEXT: mv a1, s1 ; CHECK-NEXT: mv a1, s1
; CHECK-NEXT: call __addsf3@plt ; CHECK-NEXT: call __addsf3@plt
; CHECK-NEXT: slli a0, a0, 32 ; CHECK-NEXT: slli a0, a0, 32
; CHECK-NEXT: slli a1, s0, 32 ; CHECK-NEXT: slli a1, s2, 32
; CHECK-NEXT: srli a1, a1, 32 ; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: or a0, a0, a1 ; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret ; CHECK-NEXT: ret
Show All 21 Lines

llvm/test/CodeGen/RISCV/rv64zbp.ll

Show First 20 Lines • Show All 2,402 Lines • ▼ Show 20 Lines; RV64ZBP-NEXT: ret
%2 = call i32 @llvm.bswap.i32(i32 %1) %2 = call i32 @llvm.bswap.i32(i32 %1)
ret i32 %2 ret i32 %2
} }
define i64 @bitreverse_bswap_i64(i64 %a) { define i64 @bitreverse_bswap_i64(i64 %a) {
; RV64I-LABEL: bitreverse_bswap_i64: ; RV64I-LABEL: bitreverse_bswap_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a0, 24 ; RV64I-NEXT: srli a1, a0, 24
; RV64I-NEXT: lui a6, 4080 ; RV64I-NEXT: lui a2, 4080
; RV64I-NEXT: and a1, a1, a6 ; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a3, a0, 8 ; RV64I-NEXT: srli a3, a0, 8
; RV64I-NEXT: li a4, 255 ; RV64I-NEXT: li a4, 255
; RV64I-NEXT: slli a7, a4, 24 ; RV64I-NEXT: slli a5, a4, 24
; RV64I-NEXT: and a3, a3, a7 ; RV64I-NEXT: and a3, a3, a5
; RV64I-NEXT: or a1, a3, a1 ; RV64I-NEXT: or a1, a3, a1
; RV64I-NEXT: srli a3, a0, 40 ; RV64I-NEXT: srli a3, a0, 40
; RV64I-NEXT: lui a2, 16 ; RV64I-NEXT: lui a6, 16
; RV64I-NEXT: addiw a2, a2, -256 ; RV64I-NEXT: addiw a6, a6, -256
; RV64I-NEXT: and a3, a3, a2 ; RV64I-NEXT: and a3, a3, a6
; RV64I-NEXT: srli a5, a0, 56 ; RV64I-NEXT: srli a7, a0, 56
; RV64I-NEXT: or a3, a3, a5 ; RV64I-NEXT: or a3, a3, a7
; RV64I-NEXT: or a1, a1, a3 ; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: slli a3, a0, 24 ; RV64I-NEXT: slli a3, a0, 24
; RV64I-NEXT: slli t0, a4, 40 ; RV64I-NEXT: slli a7, a4, 40
; RV64I-NEXT: and a3, a3, t0 ; RV64I-NEXT: and a3, a3, a7
; RV64I-NEXT: srliw a5, a0, 24 ; RV64I-NEXT: srliw t0, a0, 24
; RV64I-NEXT: slli a5, a5, 32 ; RV64I-NEXT: slli t0, t0, 32
; RV64I-NEXT: or a3, a3, a5 ; RV64I-NEXT: or a3, a3, t0
; RV64I-NEXT: slli a5, a0, 40 ; RV64I-NEXT: slli t0, a0, 40
; RV64I-NEXT: slli a4, a4, 48 ; RV64I-NEXT: slli a4, a4, 48
; RV64I-NEXT: and a5, a5, a4 ; RV64I-NEXT: and t0, t0, a4
; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, a5 ; RV64I-NEXT: or a0, a0, t0
; RV64I-NEXT: lui a5, %hi(.LCPI68_0) ; RV64I-NEXT: lui t0, %hi(.LCPI68_0)
; RV64I-NEXT: ld a5, %lo(.LCPI68_0)(a5) ; RV64I-NEXT: ld t0, %lo(.LCPI68_0)(t0)
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: and a1, a1, a5 ; RV64I-NEXT: and a1, a1, t0
; RV64I-NEXT: and a0, a0, a5 ; RV64I-NEXT: and a0, a0, t0
; RV64I-NEXT: lui a3, %hi(.LCPI68_1) ; RV64I-NEXT: lui a3, %hi(.LCPI68_1)
; RV64I-NEXT: ld a3, %lo(.LCPI68_1)(a3) ; RV64I-NEXT: ld a3, %lo(.LCPI68_1)(a3)
; RV64I-NEXT: slli a0, a0, 4 ; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: lui a3, %hi(.LCPI68_2) ; RV64I-NEXT: lui a3, %hi(.LCPI68_2)
; RV64I-NEXT: ld a3, %lo(.LCPI68_2)(a3) ; RV64I-NEXT: ld a3, %lo(.LCPI68_2)(a3)
; RV64I-NEXT: slli a0, a0, 2 ; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a0, a0, a3
; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: srli a1, a0, 40 ; RV64I-NEXT: srli a1, a0, 40
; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a1, a1, a6
; RV64I-NEXT: srli a2, a0, 56 ; RV64I-NEXT: srli a3, a0, 56
; RV64I-NEXT: or a1, a1, a2 ; RV64I-NEXT: or a1, a1, a3
; RV64I-NEXT: srli a2, a0, 24 ; RV64I-NEXT: srli a3, a0, 24
; RV64I-NEXT: and a2, a2, a6 ; RV64I-NEXT: and a2, a3, a2
; RV64I-NEXT: srli a3, a0, 8 ; RV64I-NEXT: srli a3, a0, 8
; RV64I-NEXT: and a3, a3, a7 ; RV64I-NEXT: and a3, a3, a5
; RV64I-NEXT: or a2, a3, a2 ; RV64I-NEXT: or a2, a3, a2
; RV64I-NEXT: or a1, a2, a1 ; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: slli a2, a0, 24 ; RV64I-NEXT: slli a2, a0, 24
; RV64I-NEXT: and a2, a2, t0 ; RV64I-NEXT: and a2, a2, a7
; RV64I-NEXT: srliw a3, a0, 24 ; RV64I-NEXT: srliw a3, a0, 24
; RV64I-NEXT: slli a3, a3, 32 ; RV64I-NEXT: slli a3, a3, 32
; RV64I-NEXT: or a2, a2, a3 ; RV64I-NEXT: or a2, a2, a3
; RV64I-NEXT: slli a3, a0, 40 ; RV64I-NEXT: slli a3, a0, 40
; RV64I-NEXT: and a3, a3, a4 ; RV64I-NEXT: and a3, a3, a4
; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: or a0, a0, a2
▲ Show 20 Lines • Show All 493 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll

Show First 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; CHECK-LABEL: ret_split_nxv128i32: ; CHECK-LABEL: ret_split_nxv128i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 5 ; CHECK-NEXT: slli a2, a2, 5
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a6, a2, 3 ; CHECK-NEXT: slli a3, a2, 3
; CHECK-NEXT: add a4, a1, a6 ; CHECK-NEXT: add a4, a1, a3
; CHECK-NEXT: vl8re32.v v8, (a4) ; CHECK-NEXT: vl8re32.v v8, (a4)
; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: csrr a4, vlenb
; CHECK-NEXT: li a4, 24 ; CHECK-NEXT: li a5, 24
; CHECK-NEXT: mul a3, a3, a4 ; CHECK-NEXT: mul a4, a4, a5
; CHECK-NEXT: add a3, sp, a3 ; CHECK-NEXT: add a4, sp, a4
; CHECK-NEXT: addi a3, a3, 16 ; CHECK-NEXT: addi a4, a4, 16
; CHECK-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; CHECK-NEXT: slli a7, a2, 4 ; CHECK-NEXT: slli a4, a2, 4
; CHECK-NEXT: add a5, a1, a7 ; CHECK-NEXT: add a5, a1, a4
; CHECK-NEXT: vl8re32.v v8, (a5) ; CHECK-NEXT: vl8re32.v v8, (a5)
; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: slli a3, a3, 4 ; CHECK-NEXT: slli a5, a5, 4
; CHECK-NEXT: add a3, sp, a3 ; CHECK-NEXT: add a5, sp, a5
; CHECK-NEXT: addi a3, a3, 16 ; CHECK-NEXT: addi a5, a5, 16
; CHECK-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
; CHECK-NEXT: li a5, 24 ; CHECK-NEXT: li a5, 24
; CHECK-NEXT: mul t1, a2, a5
; CHECK-NEXT: add a3, a1, t1
; CHECK-NEXT: vl8re32.v v8, (a3)
; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a3, a3, 3
; CHECK-NEXT: add a3, sp, a3
; CHECK-NEXT: addi a3, a3, 16
; CHECK-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; CHECK-NEXT: slli t3, a2, 5
; CHECK-NEXT: add a4, a1, t3
; CHECK-NEXT: vl8re32.v v8, (a4)
; CHECK-NEXT: addi a3, sp, 16
; CHECK-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; CHECK-NEXT: li a4, 40
; CHECK-NEXT: mul a4, a2, a4
; CHECK-NEXT: add t0, a1, a4
; CHECK-NEXT: li a5, 48
; CHECK-NEXT: mul a5, a2, a5 ; CHECK-NEXT: mul a5, a2, a5
; CHECK-NEXT: add t2, a1, a5 ; CHECK-NEXT: add a6, a1, a5
; CHECK-NEXT: li a3, 56 ; CHECK-NEXT: vl8re32.v v8, (a6)
; CHECK-NEXT: mul a2, a2, a3 ; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: add a3, a1, a2 ; CHECK-NEXT: slli a6, a6, 3
; CHECK-NEXT: add a6, sp, a6
; CHECK-NEXT: addi a6, a6, 16
; CHECK-NEXT: vs8r.v v8, (a6) # Unknown-size Folded Spill
; CHECK-NEXT: slli a6, a2, 5
; CHECK-NEXT: add a7, a1, a6
; CHECK-NEXT: vl8re32.v v8, (a7)
; CHECK-NEXT: addi a7, sp, 16
; CHECK-NEXT: vs8r.v v8, (a7) # Unknown-size Folded Spill
; CHECK-NEXT: li a7, 40
; CHECK-NEXT: mul a7, a2, a7
; CHECK-NEXT: add t0, a1, a7
; CHECK-NEXT: li t1, 48
; CHECK-NEXT: mul t1, a2, t1
; CHECK-NEXT: add t2, a1, t1
; CHECK-NEXT: li t3, 56
; CHECK-NEXT: mul a2, a2, t3
; CHECK-NEXT: add t3, a1, a2
; CHECK-NEXT: vl8re32.v v8, (a1) ; CHECK-NEXT: vl8re32.v v8, (a1)
; CHECK-NEXT: vl8re32.v v0, (t0) ; CHECK-NEXT: vl8re32.v v0, (t0)
; CHECK-NEXT: vl8re32.v v16, (a3) ; CHECK-NEXT: vl8re32.v v16, (t3)
; CHECK-NEXT: vl8re32.v v24, (t2) ; CHECK-NEXT: vl8re32.v v24, (t2)
; CHECK-NEXT: vs8r.v v8, (a0) ; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: add a1, a0, a2 ; CHECK-NEXT: add a1, a0, a2
; CHECK-NEXT: vs8r.v v16, (a1) ; CHECK-NEXT: vs8r.v v16, (a1)
; CHECK-NEXT: add a1, a0, a5 ; CHECK-NEXT: add a1, a0, t1
; CHECK-NEXT: vs8r.v v24, (a1) ; CHECK-NEXT: vs8r.v v24, (a1)
; CHECK-NEXT: add a1, a0, a4 ; CHECK-NEXT: add a1, a0, a7
; CHECK-NEXT: vs8r.v v0, (a1) ; CHECK-NEXT: vs8r.v v0, (a1)
; CHECK-NEXT: add a1, a0, t3 ; CHECK-NEXT: add a1, a0, a6
; CHECK-NEXT: addi a2, sp, 16 ; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vl8re8.v v8, (a2) # Unknown-size Folded Reload ; CHECK-NEXT: vl8re8.v v8, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vs8r.v v8, (a1) ; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: add a1, a0, t1 ; CHECK-NEXT: add a1, a0, a5
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8re8.v v8, (a2) # Unknown-size Folded Reload ; CHECK-NEXT: vl8re8.v v8, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vs8r.v v8, (a1) ; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: add a1, a0, a7 ; CHECK-NEXT: add a1, a0, a4
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4 ; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8re8.v v8, (a2) # Unknown-size Folded Reload ; CHECK-NEXT: vl8re8.v v8, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vs8r.v v8, (a1) ; CHECK-NEXT: vs8r.v v8, (a1)
; CHECK-NEXT: add a0, a0, a6 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a2, 24 ; CHECK-NEXT: li a2, 24
; CHECK-NEXT: mul a1, a1, a2 ; CHECK-NEXT: mul a1, a1, a2
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vs8r.v v8, (a0) ; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
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llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll

; RUN: opt %s -S -riscv-gather-scatter-lowering -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=256 | FileCheck %s ; RUN: opt %s -S -riscv-gather-scatter-lowering -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=256 | FileCheck %s
craig.topperUnsubmitted
Done
ReplyInline Actions

Drop this line. the test is generated by both update_llc_test_checks.py and update_test_checks.py. Having the comment at the top prevents the opposite script from being able to run on the file.

craig.topper: Drop this line. the test is generated by both update_llc_test_checks.py and update_test_checks.
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=256 | FileCheck %s --check-prefix=CHECK-ASM ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+experimental-v -riscv-v-vector-bits-min=256 | FileCheck %s --check-prefix=CHECK-ASM
%struct.foo = type { i32, i32, i32, i32 } %struct.foo = type { i32, i32, i32, i32 }
; void gather(signed char * __restrict A, signed char * __restrict B) { ; void gather(signed char * __restrict A, signed char * __restrict B) {
; for (int i = 0; i != 1024; ++i) ; for (int i = 0; i != 1024; ++i)
; A[i] += B[i * 5]; ; A[i] += B[i * 5];
; } ; }
Show All 17 Lines
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; CHECK-NEXT: br i1 [[TMP5]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]] ; CHECK-NEXT: br i1 [[TMP5]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]]
; CHECK: for.cond.cleanup: ; CHECK: for.cond.cleanup:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; CHECK-ASM-LABEL: gather: ; CHECK-ASM-LABEL: gather:
; CHECK-ASM: # %bb.0: # %entry ; CHECK-ASM: # %bb.0: # %entry
; CHECK-ASM-NEXT: li a2, 0 ; CHECK-ASM-NEXT: li a2, 0
; CHECK-ASM-NEXT: li a6, 32 ; CHECK-ASM-NEXT: li a3, 32
; CHECK-ASM-NEXT: li a4, 5 ; CHECK-ASM-NEXT: li a4, 5
; CHECK-ASM-NEXT: li a5, 1024 ; CHECK-ASM-NEXT: li a5, 1024
; CHECK-ASM-NEXT: .LBB0_1: # %vector.body ; CHECK-ASM-NEXT: .LBB0_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu ; CHECK-ASM-NEXT: vsetvli zero, a3, e8, m1, ta, mu
; CHECK-ASM-NEXT: vlse8.v v8, (a1), a4 ; CHECK-ASM-NEXT: vlse8.v v8, (a1), a4
; CHECK-ASM-NEXT: add a3, a0, a2 ; CHECK-ASM-NEXT: add a6, a0, a2
; CHECK-ASM-NEXT: vle8.v v9, (a3) ; CHECK-ASM-NEXT: vle8.v v9, (a6)
; CHECK-ASM-NEXT: vadd.vv v8, v9, v8 ; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
; CHECK-ASM-NEXT: vse8.v v8, (a3) ; CHECK-ASM-NEXT: vse8.v v8, (a6)
; CHECK-ASM-NEXT: addi a2, a2, 32 ; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a1, a1, 160 ; CHECK-ASM-NEXT: addi a1, a1, 160
; CHECK-ASM-NEXT: bne a2, a5, .LBB0_1 ; CHECK-ASM-NEXT: bne a2, a5, .LBB0_1
; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-ASM-NEXT: ret ; CHECK-ASM-NEXT: ret
entry: entry:
br label %vector.body br label %vector.body
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; ;
; CHECK-ASM-LABEL: gather_masked: ; CHECK-ASM-LABEL: gather_masked:
; CHECK-ASM: # %bb.0: # %entry ; CHECK-ASM: # %bb.0: # %entry
; CHECK-ASM-NEXT: li a2, 0 ; CHECK-ASM-NEXT: li a2, 0
; CHECK-ASM-NEXT: lui a3, 983765 ; CHECK-ASM-NEXT: lui a3, 983765
; CHECK-ASM-NEXT: addiw a3, a3, 873 ; CHECK-ASM-NEXT: addiw a3, a3, 873
; CHECK-ASM-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-ASM-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-ASM-NEXT: vmv.s.x v0, a3 ; CHECK-ASM-NEXT: vmv.s.x v0, a3
; CHECK-ASM-NEXT: li a6, 32 ; CHECK-ASM-NEXT: li a3, 32
; CHECK-ASM-NEXT: li a4, 5 ; CHECK-ASM-NEXT: li a4, 5
; CHECK-ASM-NEXT: li a5, 1024 ; CHECK-ASM-NEXT: li a5, 1024
; CHECK-ASM-NEXT: .LBB1_1: # %vector.body ; CHECK-ASM-NEXT: .LBB1_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu ; CHECK-ASM-NEXT: vsetvli zero, a3, e8, m1, ta, mu
; CHECK-ASM-NEXT: vmv1r.v v9, v8 ; CHECK-ASM-NEXT: vmv1r.v v9, v8
; CHECK-ASM-NEXT: vlse8.v v9, (a1), a4, v0.t ; CHECK-ASM-NEXT: vlse8.v v9, (a1), a4, v0.t
; CHECK-ASM-NEXT: add a3, a0, a2 ; CHECK-ASM-NEXT: add a6, a0, a2
; CHECK-ASM-NEXT: vle8.v v10, (a3) ; CHECK-ASM-NEXT: vle8.v v10, (a6)
; CHECK-ASM-NEXT: vadd.vv v9, v10, v9 ; CHECK-ASM-NEXT: vadd.vv v9, v10, v9
; CHECK-ASM-NEXT: vse8.v v9, (a3) ; CHECK-ASM-NEXT: vse8.v v9, (a6)
; CHECK-ASM-NEXT: addi a2, a2, 32 ; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a1, a1, 160 ; CHECK-ASM-NEXT: addi a1, a1, 160
; CHECK-ASM-NEXT: bne a2, a5, .LBB1_1 ; CHECK-ASM-NEXT: bne a2, a5, .LBB1_1
; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-ASM-NEXT: ret ; CHECK-ASM-NEXT: ret
entry: entry:
br label %vector.body br label %vector.body
Show All 39 Lines
; CHECK-NEXT: br i1 [[TMP5]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]] ; CHECK-NEXT: br i1 [[TMP5]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]]
; CHECK: for.cond.cleanup: ; CHECK: for.cond.cleanup:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; CHECK-ASM-LABEL: gather_negative_stride: ; CHECK-ASM-LABEL: gather_negative_stride:
; CHECK-ASM: # %bb.0: # %entry ; CHECK-ASM: # %bb.0: # %entry
; CHECK-ASM-NEXT: li a2, 0 ; CHECK-ASM-NEXT: li a2, 0
; CHECK-ASM-NEXT: addi a1, a1, 155 ; CHECK-ASM-NEXT: addi a1, a1, 155
; CHECK-ASM-NEXT: li a6, 32 ; CHECK-ASM-NEXT: li a3, 32
; CHECK-ASM-NEXT: li a4, -5 ; CHECK-ASM-NEXT: li a4, -5
; CHECK-ASM-NEXT: li a5, 1024 ; CHECK-ASM-NEXT: li a5, 1024
; CHECK-ASM-NEXT: .LBB2_1: # %vector.body ; CHECK-ASM-NEXT: .LBB2_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu ; CHECK-ASM-NEXT: vsetvli zero, a3, e8, m1, ta, mu
; CHECK-ASM-NEXT: vlse8.v v8, (a1), a4 ; CHECK-ASM-NEXT: vlse8.v v8, (a1), a4
; CHECK-ASM-NEXT: add a3, a0, a2 ; CHECK-ASM-NEXT: add a6, a0, a2
; CHECK-ASM-NEXT: vle8.v v9, (a3) ; CHECK-ASM-NEXT: vle8.v v9, (a6)
; CHECK-ASM-NEXT: vadd.vv v8, v9, v8 ; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
; CHECK-ASM-NEXT: vse8.v v8, (a3) ; CHECK-ASM-NEXT: vse8.v v8, (a6)
; CHECK-ASM-NEXT: addi a2, a2, 32 ; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a1, a1, 160 ; CHECK-ASM-NEXT: addi a1, a1, 160
; CHECK-ASM-NEXT: bne a2, a5, .LBB2_1 ; CHECK-ASM-NEXT: bne a2, a5, .LBB2_1
; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-ASM-NEXT: ret ; CHECK-ASM-NEXT: ret
entry: entry:
br label %vector.body br label %vector.body
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; CHECK-NEXT: br i1 [[TMP5]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]] ; CHECK-NEXT: br i1 [[TMP5]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]]
; CHECK: for.cond.cleanup: ; CHECK: for.cond.cleanup:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; CHECK-ASM-LABEL: scatter: ; CHECK-ASM-LABEL: scatter:
; CHECK-ASM: # %bb.0: # %entry ; CHECK-ASM: # %bb.0: # %entry
; CHECK-ASM-NEXT: li a2, 0 ; CHECK-ASM-NEXT: li a2, 0
; CHECK-ASM-NEXT: li a6, 32 ; CHECK-ASM-NEXT: li a3, 32
; CHECK-ASM-NEXT: li a4, 5 ; CHECK-ASM-NEXT: li a4, 5
; CHECK-ASM-NEXT: li a5, 1024 ; CHECK-ASM-NEXT: li a5, 1024
; CHECK-ASM-NEXT: .LBB4_1: # %vector.body ; CHECK-ASM-NEXT: .LBB4_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: add a3, a1, a2 ; CHECK-ASM-NEXT: add a6, a1, a2
; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu ; CHECK-ASM-NEXT: vsetvli zero, a3, e8, m1, ta, mu
; CHECK-ASM-NEXT: vle8.v v8, (a3) ; CHECK-ASM-NEXT: vle8.v v8, (a6)
; CHECK-ASM-NEXT: vlse8.v v9, (a0), a4 ; CHECK-ASM-NEXT: vlse8.v v9, (a0), a4
; CHECK-ASM-NEXT: vadd.vv v8, v9, v8 ; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
; CHECK-ASM-NEXT: vsse8.v v8, (a0), a4 ; CHECK-ASM-NEXT: vsse8.v v8, (a0), a4
; CHECK-ASM-NEXT: addi a2, a2, 32 ; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a0, a0, 160 ; CHECK-ASM-NEXT: addi a0, a0, 160
; CHECK-ASM-NEXT: bne a2, a5, .LBB4_1 ; CHECK-ASM-NEXT: bne a2, a5, .LBB4_1
; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup
; CHECK-ASM-NEXT: ret ; CHECK-ASM-NEXT: ret
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; CHECK-NEXT: br i1 [[TMP5]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]] ; CHECK-NEXT: br i1 [[TMP5]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]]
; CHECK: for.cond.cleanup: ; CHECK: for.cond.cleanup:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
; CHECK-ASM-LABEL: scatter_masked: ; CHECK-ASM-LABEL: scatter_masked:
; CHECK-ASM: # %bb.0: # %entry ; CHECK-ASM: # %bb.0: # %entry
; CHECK-ASM-NEXT: li a2, 0 ; CHECK-ASM-NEXT: li a2, 0
; CHECK-ASM-NEXT: li a6, 32 ; CHECK-ASM-NEXT: li a3, 32
; CHECK-ASM-NEXT: lui a4, 983765 ; CHECK-ASM-NEXT: lui a4, 983765
; CHECK-ASM-NEXT: addiw a4, a4, 873 ; CHECK-ASM-NEXT: addiw a4, a4, 873
; CHECK-ASM-NEXT: vsetivli zero, 1, e32, mf2, ta, mu ; CHECK-ASM-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-ASM-NEXT: vmv.s.x v0, a4 ; CHECK-ASM-NEXT: vmv.s.x v0, a4
; CHECK-ASM-NEXT: li a4, 5 ; CHECK-ASM-NEXT: li a4, 5
; CHECK-ASM-NEXT: li a5, 1024 ; CHECK-ASM-NEXT: li a5, 1024
; CHECK-ASM-NEXT: .LBB5_1: # %vector.body ; CHECK-ASM-NEXT: .LBB5_1: # %vector.body
; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: add a3, a1, a2 ; CHECK-ASM-NEXT: add a6, a1, a2
; CHECK-ASM-NEXT: vsetvli zero, a6, e8, m1, ta, mu ; CHECK-ASM-NEXT: vsetvli zero, a3, e8, m1, ta, mu
; CHECK-ASM-NEXT: vle8.v v9, (a3) ; CHECK-ASM-NEXT: vle8.v v9, (a6)
; CHECK-ASM-NEXT: vmv1r.v v10, v8 ; CHECK-ASM-NEXT: vmv1r.v v10, v8
; CHECK-ASM-NEXT: vlse8.v v10, (a0), a4, v0.t ; CHECK-ASM-NEXT: vlse8.v v10, (a0), a4, v0.t
; CHECK-ASM-NEXT: vadd.vv v9, v10, v9 ; CHECK-ASM-NEXT: vadd.vv v9, v10, v9
; CHECK-ASM-NEXT: vsse8.v v9, (a0), a4, v0.t ; CHECK-ASM-NEXT: vsse8.v v9, (a0), a4, v0.t
; CHECK-ASM-NEXT: addi a2, a2, 32 ; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a0, a0, 160 ; CHECK-ASM-NEXT: addi a0, a0, 160
; CHECK-ASM-NEXT: bne a2, a5, .LBB5_1 ; CHECK-ASM-NEXT: bne a2, a5, .LBB5_1
; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-ASM-NEXT: # %bb.2: # %for.cond.cleanup
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; CHECK-ASM-NEXT: li a3, 1023 ; CHECK-ASM-NEXT: li a3, 1023
; CHECK-ASM-NEXT: subw a4, a3, a2 ; CHECK-ASM-NEXT: subw a4, a3, a2
; CHECK-ASM-NEXT: li a5, 31 ; CHECK-ASM-NEXT: li a5, 31
; CHECK-ASM-NEXT: mv a3, a2 ; CHECK-ASM-NEXT: mv a3, a2
; CHECK-ASM-NEXT: bltu a4, a5, .LBB12_5 ; CHECK-ASM-NEXT: bltu a4, a5, .LBB12_5
; CHECK-ASM-NEXT: # %bb.2: ; CHECK-ASM-NEXT: # %bb.2:
; CHECK-ASM-NEXT: slli a3, a4, 32 ; CHECK-ASM-NEXT: slli a3, a4, 32
; CHECK-ASM-NEXT: srli a3, a3, 32 ; CHECK-ASM-NEXT: srli a3, a3, 32
; CHECK-ASM-NEXT: addi a6, a3, 1 ; CHECK-ASM-NEXT: addi a4, a3, 1
; CHECK-ASM-NEXT: andi a7, a6, -32 ; CHECK-ASM-NEXT: andi a5, a4, -32
; CHECK-ASM-NEXT: add a3, a7, a2 ; CHECK-ASM-NEXT: add a3, a5, a2
; CHECK-ASM-NEXT: slli a4, a2, 2 ; CHECK-ASM-NEXT: slli a6, a2, 2
; CHECK-ASM-NEXT: add a4, a4, a2 ; CHECK-ASM-NEXT: add a6, a6, a2
; CHECK-ASM-NEXT: add a2, a0, a2 ; CHECK-ASM-NEXT: add a2, a0, a2
; CHECK-ASM-NEXT: add a4, a1, a4 ; CHECK-ASM-NEXT: add a6, a1, a6
; CHECK-ASM-NEXT: li t0, 32 ; CHECK-ASM-NEXT: li a7, 32
; CHECK-ASM-NEXT: li t1, 5 ; CHECK-ASM-NEXT: li t0, 5
; CHECK-ASM-NEXT: mv a5, a7 ; CHECK-ASM-NEXT: mv t1, a5
; CHECK-ASM-NEXT: .LBB12_3: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: .LBB12_3: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: vsetvli zero, t0, e8, m1, ta, mu ; CHECK-ASM-NEXT: vsetvli zero, a7, e8, m1, ta, mu
; CHECK-ASM-NEXT: vlse8.v v8, (a4), t1 ; CHECK-ASM-NEXT: vlse8.v v8, (a6), t0
; CHECK-ASM-NEXT: vle8.v v9, (a2) ; CHECK-ASM-NEXT: vle8.v v9, (a2)
; CHECK-ASM-NEXT: vadd.vv v8, v9, v8 ; CHECK-ASM-NEXT: vadd.vv v8, v9, v8
; CHECK-ASM-NEXT: vse8.v v8, (a2) ; CHECK-ASM-NEXT: vse8.v v8, (a2)
; CHECK-ASM-NEXT: addi a5, a5, -32 ; CHECK-ASM-NEXT: addi t1, t1, -32
; CHECK-ASM-NEXT: addi a2, a2, 32 ; CHECK-ASM-NEXT: addi a2, a2, 32
; CHECK-ASM-NEXT: addi a4, a4, 160 ; CHECK-ASM-NEXT: addi a6, a6, 160
; CHECK-ASM-NEXT: bnez a5, .LBB12_3 ; CHECK-ASM-NEXT: bnez t1, .LBB12_3
; CHECK-ASM-NEXT: # %bb.4: ; CHECK-ASM-NEXT: # %bb.4:
; CHECK-ASM-NEXT: beq a6, a7, .LBB12_7 ; CHECK-ASM-NEXT: beq a4, a5, .LBB12_7
; CHECK-ASM-NEXT: .LBB12_5: ; CHECK-ASM-NEXT: .LBB12_5:
; CHECK-ASM-NEXT: slli a2, a3, 2 ; CHECK-ASM-NEXT: slli a2, a3, 2
; CHECK-ASM-NEXT: add a2, a2, a3 ; CHECK-ASM-NEXT: add a2, a2, a3
; CHECK-ASM-NEXT: add a1, a1, a2 ; CHECK-ASM-NEXT: add a1, a1, a2
; CHECK-ASM-NEXT: li a6, 1024 ; CHECK-ASM-NEXT: li a2, 1024
; CHECK-ASM-NEXT: .LBB12_6: # =>This Inner Loop Header: Depth=1 ; CHECK-ASM-NEXT: .LBB12_6: # =>This Inner Loop Header: Depth=1
; CHECK-ASM-NEXT: lb a4, 0(a1) ; CHECK-ASM-NEXT: lb a4, 0(a1)
; CHECK-ASM-NEXT: add a5, a0, a3 ; CHECK-ASM-NEXT: add a5, a0, a3
; CHECK-ASM-NEXT: lb a2, 0(a5) ; CHECK-ASM-NEXT: lb a6, 0(a5)
; CHECK-ASM-NEXT: addw a2, a2, a4 ; CHECK-ASM-NEXT: addw a4, a6, a4
; CHECK-ASM-NEXT: sb a2, 0(a5) ; CHECK-ASM-NEXT: sb a4, 0(a5)
; CHECK-ASM-NEXT: addiw a2, a3, 1 ; CHECK-ASM-NEXT: addiw a4, a3, 1
; CHECK-ASM-NEXT: addi a3, a3, 1 ; CHECK-ASM-NEXT: addi a3, a3, 1
; CHECK-ASM-NEXT: addi a1, a1, 5 ; CHECK-ASM-NEXT: addi a1, a1, 5
; CHECK-ASM-NEXT: bne a2, a6, .LBB12_6 ; CHECK-ASM-NEXT: bne a4, a2, .LBB12_6
; CHECK-ASM-NEXT: .LBB12_7: ; CHECK-ASM-NEXT: .LBB12_7:
; CHECK-ASM-NEXT: ret ; CHECK-ASM-NEXT: ret
%4 = icmp eq i32 %2, 1024 %4 = icmp eq i32 %2, 1024
br i1 %4, label %36, label %5 br i1 %4, label %36, label %5
5: ; preds = %3 5: ; preds = %3
%6 = sext i32 %2 to i64 %6 = sext i32 %2 to i64
%7 = sub i32 1023, %2 %7 = sub i32 1023, %2
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll

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; LMULMAX1-RV32-NEXT: vle32.v v9, (a0) ; LMULMAX1-RV32-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8
; LMULMAX1-RV32-NEXT: lui a2, 16 ; LMULMAX1-RV32-NEXT: lui a2, 16
; LMULMAX1-RV32-NEXT: addi a2, a2, -256 ; LMULMAX1-RV32-NEXT: addi a2, a2, -256
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV32-NEXT: vsll.vi v11, v8, 8 ; LMULMAX1-RV32-NEXT: vsll.vi v11, v8, 8
; LMULMAX1-RV32-NEXT: lui a6, 4080 ; LMULMAX1-RV32-NEXT: lui a3, 4080
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a6 ; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a3
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24 ; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV32-NEXT: lui a4, 61681 ; LMULMAX1-RV32-NEXT: lui a4, 61681
; LMULMAX1-RV32-NEXT: addi a4, a4, -241 ; LMULMAX1-RV32-NEXT: addi a4, a4, -241
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4 ; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4
; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 2
; LMULMAX1-RV32-NEXT: lui a5, 209715 ; LMULMAX1-RV32-NEXT: lui a5, 209715
; LMULMAX1-RV32-NEXT: addi a5, a5, 819 ; LMULMAX1-RV32-NEXT: addi a5, a5, 819
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2 ; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 2
; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV32-NEXT: lui a3, 349525 ; LMULMAX1-RV32-NEXT: lui a6, 349525
; LMULMAX1-RV32-NEXT: addi a3, a3, 1365 ; LMULMAX1-RV32-NEXT: addi a6, a6, 1365
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a6
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a3 ; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a6
; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8 ; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8
; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV32-NEXT: vsll.vi v11, v9, 8 ; LMULMAX1-RV32-NEXT: vsll.vi v11, v9, 8
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a6 ; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a3
; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 24 ; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 24
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v11 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4 ; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4
; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 4 ; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 4
; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 2 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 2
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a5 ; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 2 ; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 2
; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a6
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a3 ; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a6
; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v9 ; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v9
; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV32-NEXT: vse32.v v9, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1-RV32-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV32-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: bitreverse_v8i32: ; LMULMAX1-RV64-LABEL: bitreverse_v8i32:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle32.v v9, (a0) ; LMULMAX1-RV64-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX1-RV64-NEXT: lui a2, 16 ; LMULMAX1-RV64-NEXT: lui a2, 16
; LMULMAX1-RV64-NEXT: addiw a2, a2, -256 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -256
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8
; LMULMAX1-RV64-NEXT: lui a6, 4080 ; LMULMAX1-RV64-NEXT: lui a3, 4080
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a3
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 24 ; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 24
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: lui a4, 61681 ; LMULMAX1-RV64-NEXT: lui a4, 61681
; LMULMAX1-RV64-NEXT: addiw a4, a4, -241 ; LMULMAX1-RV64-NEXT: addiw a4, a4, -241
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4 ; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2
; LMULMAX1-RV64-NEXT: lui a5, 209715 ; LMULMAX1-RV64-NEXT: lui a5, 209715
; LMULMAX1-RV64-NEXT: addiw a5, a5, 819 ; LMULMAX1-RV64-NEXT: addiw a5, a5, 819
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: lui a3, 349525 ; LMULMAX1-RV64-NEXT: lui a6, 349525
; LMULMAX1-RV64-NEXT: addiw a3, a3, 1365 ; LMULMAX1-RV64-NEXT: addiw a6, a6, 1365
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a6
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8 ; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a3
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 24 ; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 24
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4 ; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2 ; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a6
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9 ; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vse32.v v9, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1-RV64-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV64-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <8 x i32>, <8 x i32>* %x %a = load <8 x i32>, <8 x i32>* %x
%b = load <8 x i32>, <8 x i32>* %y %b = load <8 x i32>, <8 x i32>* %y
%c = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %a) %c = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %a)
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; LMULMAX1-RV32-NEXT: vsrl.vx v9, v12, a2 ; LMULMAX1-RV32-NEXT: vsrl.vx v9, v12, a2
; LMULMAX1-RV32-NEXT: li a3, 40 ; LMULMAX1-RV32-NEXT: li a3, 40
; LMULMAX1-RV32-NEXT: vsrl.vx v10, v12, a3 ; LMULMAX1-RV32-NEXT: vsrl.vx v10, v12, a3
; LMULMAX1-RV32-NEXT: lui a4, 16 ; LMULMAX1-RV32-NEXT: lui a4, 16
; LMULMAX1-RV32-NEXT: addi a4, a4, -256 ; LMULMAX1-RV32-NEXT: addi a4, a4, -256
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v9 ; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v12, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v9, v12, 24
; LMULMAX1-RV32-NEXT: lui a6, 4080 ; LMULMAX1-RV32-NEXT: lui a5, 4080
; LMULMAX1-RV32-NEXT: vand.vx v11, v9, a6 ; LMULMAX1-RV32-NEXT: vand.vx v11, v9, a5
; LMULMAX1-RV32-NEXT: li a5, 5 ; LMULMAX1-RV32-NEXT: li a6, 5
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a5 ; LMULMAX1-RV32-NEXT: vmv.s.x v0, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.i v9, 0 ; LMULMAX1-RV32-NEXT: vmv.v.i v9, 0
; LMULMAX1-RV32-NEXT: lui a5, 1044480 ; LMULMAX1-RV32-NEXT: lui a6, 1044480
; LMULMAX1-RV32-NEXT: vmerge.vxm v9, v9, a5, v0 ; LMULMAX1-RV32-NEXT: vmerge.vxm v9, v9, a6, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 8
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v9 ; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v9
; LMULMAX1-RV32-NEXT: vor.vv v11, v13, v11 ; LMULMAX1-RV32-NEXT: vor.vv v11, v13, v11
; LMULMAX1-RV32-NEXT: vor.vv v13, v11, v10 ; LMULMAX1-RV32-NEXT: vor.vv v13, v11, v10
; LMULMAX1-RV32-NEXT: li a5, 255 ; LMULMAX1-RV32-NEXT: li a6, 255
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v10, a5 ; LMULMAX1-RV32-NEXT: vmv.v.x v10, a6
; LMULMAX1-RV32-NEXT: vmerge.vim v10, v10, 0, v0 ; LMULMAX1-RV32-NEXT: vmerge.vim v10, v10, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vsll.vi v11, v12, 8 ; LMULMAX1-RV32-NEXT: vsll.vi v11, v12, 8
; LMULMAX1-RV32-NEXT: vand.vv v14, v11, v10 ; LMULMAX1-RV32-NEXT: vand.vv v14, v11, v10
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v11, a4 ; LMULMAX1-RV32-NEXT: vmv.v.x v11, a4
; LMULMAX1-RV32-NEXT: vmerge.vim v11, v11, 0, v0 ; LMULMAX1-RV32-NEXT: vmerge.vim v11, v11, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vsll.vi v15, v12, 24 ; LMULMAX1-RV32-NEXT: vsll.vi v15, v12, 24
; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v11 ; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v11
; LMULMAX1-RV32-NEXT: vor.vv v14, v15, v14 ; LMULMAX1-RV32-NEXT: vor.vv v14, v15, v14
; LMULMAX1-RV32-NEXT: vsll.vx v15, v12, a3 ; LMULMAX1-RV32-NEXT: vsll.vx v15, v12, a3
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v16, a6 ; LMULMAX1-RV32-NEXT: vmv.v.x v16, a5
; LMULMAX1-RV32-NEXT: vmerge.vim v16, v16, 0, v0 ; LMULMAX1-RV32-NEXT: vmerge.vim v16, v16, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v16 ; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v16
; LMULMAX1-RV32-NEXT: vsll.vx v12, v12, a2 ; LMULMAX1-RV32-NEXT: vsll.vx v12, v12, a2
; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v15 ; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v15
; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v14 ; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v14
; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13 ; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 4 ; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 4
; LMULMAX1-RV32-NEXT: lui a5, 61681 ; LMULMAX1-RV32-NEXT: lui a6, 61681
; LMULMAX1-RV32-NEXT: addi a5, a5, -241 ; LMULMAX1-RV32-NEXT: addi a6, a6, -241
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v14, a5 ; LMULMAX1-RV32-NEXT: vmv.v.x v14, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v14 ; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v14
; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v14 ; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v14
; LMULMAX1-RV32-NEXT: vsll.vi v12, v12, 4 ; LMULMAX1-RV32-NEXT: vsll.vi v12, v12, 4
; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12 ; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 2 ; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 2
; LMULMAX1-RV32-NEXT: lui a5, 209715 ; LMULMAX1-RV32-NEXT: lui a6, 209715
; LMULMAX1-RV32-NEXT: addi a5, a5, 819 ; LMULMAX1-RV32-NEXT: addi a6, a6, 819
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v15, a5 ; LMULMAX1-RV32-NEXT: vmv.v.x v15, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v15 ; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v15
; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v15 ; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v15
; LMULMAX1-RV32-NEXT: vsll.vi v12, v12, 2 ; LMULMAX1-RV32-NEXT: vsll.vi v12, v12, 2
; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12 ; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 1 ; LMULMAX1-RV32-NEXT: vsrl.vi v13, v12, 1
; LMULMAX1-RV32-NEXT: lui a5, 349525 ; LMULMAX1-RV32-NEXT: lui a6, 349525
; LMULMAX1-RV32-NEXT: addi a5, a5, 1365 ; LMULMAX1-RV32-NEXT: addi a6, a6, 1365
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v17, a5 ; LMULMAX1-RV32-NEXT: vmv.v.x v17, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v17 ; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v17
; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v17 ; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v17
; LMULMAX1-RV32-NEXT: vadd.vv v12, v12, v12 ; LMULMAX1-RV32-NEXT: vadd.vv v12, v12, v12
; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12 ; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12
; LMULMAX1-RV32-NEXT: vsrl.vx v13, v8, a2 ; LMULMAX1-RV32-NEXT: vsrl.vx v13, v8, a2
; LMULMAX1-RV32-NEXT: vsrl.vx v18, v8, a3 ; LMULMAX1-RV32-NEXT: vsrl.vx v18, v8, a3
; LMULMAX1-RV32-NEXT: vand.vx v18, v18, a4 ; LMULMAX1-RV32-NEXT: vand.vx v18, v18, a4
; LMULMAX1-RV32-NEXT: vor.vv v13, v18, v13 ; LMULMAX1-RV32-NEXT: vor.vv v13, v18, v13
; LMULMAX1-RV32-NEXT: vsrl.vi v18, v8, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v18, v8, 24
; LMULMAX1-RV32-NEXT: vand.vx v18, v18, a6 ; LMULMAX1-RV32-NEXT: vand.vx v18, v18, a5
; LMULMAX1-RV32-NEXT: vsrl.vi v19, v8, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v19, v8, 8
; LMULMAX1-RV32-NEXT: vand.vv v9, v19, v9 ; LMULMAX1-RV32-NEXT: vand.vv v9, v19, v9
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v18 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v18
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v13 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v13
; LMULMAX1-RV32-NEXT: vsll.vi v13, v8, 8 ; LMULMAX1-RV32-NEXT: vsll.vi v13, v8, 8
; LMULMAX1-RV32-NEXT: vand.vv v10, v13, v10 ; LMULMAX1-RV32-NEXT: vand.vv v10, v13, v10
; LMULMAX1-RV32-NEXT: vsll.vi v13, v8, 24 ; LMULMAX1-RV32-NEXT: vsll.vi v13, v8, 24
; LMULMAX1-RV32-NEXT: vand.vv v11, v13, v11 ; LMULMAX1-RV32-NEXT: vand.vv v11, v13, v11
Show All 21 Lines
; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV32-NEXT: vse64.v v12, (a1) ; LMULMAX1-RV32-NEXT: vse64.v v12, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: bitreverse_v4i64: ; LMULMAX1-RV64-LABEL: bitreverse_v4i64:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a7, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v9, (a7) ; LMULMAX1-RV64-NEXT: vle64.v v9, (a1)
; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: li t0, 56 ; LMULMAX1-RV64-NEXT: li a2, 56
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, t0 ; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, a2
; LMULMAX1-RV64-NEXT: li t1, 40 ; LMULMAX1-RV64-NEXT: li a3, 40
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v9, t1 ; LMULMAX1-RV64-NEXT: vsrl.vx v11, v9, a3
; LMULMAX1-RV64-NEXT: lui a4, 16 ; LMULMAX1-RV64-NEXT: lui a4, 16
; LMULMAX1-RV64-NEXT: addiw t2, a4, -256 ; LMULMAX1-RV64-NEXT: addiw a4, a4, -256
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t2 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV64-NEXT: lui a6, 4080 ; LMULMAX1-RV64-NEXT: lui a5, 4080
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV64-NEXT: vsrl.vi v12, v9, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v12, v9, 8
; LMULMAX1-RV64-NEXT: li a5, 255 ; LMULMAX1-RV64-NEXT: li a6, 255
; LMULMAX1-RV64-NEXT: slli t3, a5, 24 ; LMULMAX1-RV64-NEXT: slli a7, a6, 24
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t3 ; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a7
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8
; LMULMAX1-RV64-NEXT: slli t4, a5, 32 ; LMULMAX1-RV64-NEXT: slli t0, a6, 32
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t4 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t0
; LMULMAX1-RV64-NEXT: vsll.vi v12, v9, 24 ; LMULMAX1-RV64-NEXT: vsll.vi v12, v9, 24
; LMULMAX1-RV64-NEXT: slli a3, a5, 40 ; LMULMAX1-RV64-NEXT: slli t1, a6, 40
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a3 ; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t1
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vsll.vx v12, v9, t0 ; LMULMAX1-RV64-NEXT: vsll.vx v12, v9, a2
; LMULMAX1-RV64-NEXT: vsll.vx v9, v9, t1 ; LMULMAX1-RV64-NEXT: vsll.vx v9, v9, a3
; LMULMAX1-RV64-NEXT: slli a5, a5, 48 ; LMULMAX1-RV64-NEXT: slli a6, a6, 48
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vor.vv v9, v12, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v12, v9
; LMULMAX1-RV64-NEXT: lui a4, %hi(.LCPI5_0) ; LMULMAX1-RV64-NEXT: lui t2, %hi(.LCPI5_0)
; LMULMAX1-RV64-NEXT: ld a4, %lo(.LCPI5_0)(a4) ; LMULMAX1-RV64-NEXT: ld t2, %lo(.LCPI5_0)(t2)
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t2
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, t2
; LMULMAX1-RV64-NEXT: lui a1, %hi(.LCPI5_1) ; LMULMAX1-RV64-NEXT: lui t3, %hi(.LCPI5_1)
; LMULMAX1-RV64-NEXT: ld a1, %lo(.LCPI5_1)(a1) ; LMULMAX1-RV64-NEXT: ld t3, %lo(.LCPI5_1)(t3)
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4 ; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a1 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t3
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a1 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, t3
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI5_2) ; LMULMAX1-RV64-NEXT: lui t4, %hi(.LCPI5_2)
; LMULMAX1-RV64-NEXT: ld a2, %lo(.LCPI5_2)(a2) ; LMULMAX1-RV64-NEXT: ld t4, %lo(.LCPI5_2)(t4)
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2 ; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 2
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t4
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a2 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, t4
; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9 ; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v9
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, t0 ; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a2
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v8, t1 ; LMULMAX1-RV64-NEXT: vsrl.vx v11, v8, a3
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t2 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV64-NEXT: vsrl.vi v12, v8, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v12, v8, 8
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t3 ; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a7
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t4 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t0
; LMULMAX1-RV64-NEXT: vsll.vi v12, v8, 24 ; LMULMAX1-RV64-NEXT: vsll.vi v12, v8, 24
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a3 ; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t1
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vsll.vx v12, v8, t0 ; LMULMAX1-RV64-NEXT: vsll.vx v12, v8, a2
; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, t1 ; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, a3
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: vor.vv v8, v12, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v12, v8
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t2
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, t2
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4 ; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a1 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t3
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a1 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, t3
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, t4
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a2 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, t4
; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8 ; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v9, (a7) ; LMULMAX1-RV64-NEXT: vse64.v v9, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x %a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y %b = load <4 x i64>, <4 x i64>* %y
%c = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %a) %c = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %a)
store <4 x i64> %c, <4 x i64>* %x store <4 x i64> %c, <4 x i64>* %x
ret void ret void
} }
declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

Show First 20 Lines • Show All 589 Lines • ▼ Show 20 Lines
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: bswap_v4i64: ; LMULMAX1-RV32-LABEL: bswap_v4i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle64.v v9, (a1) ; LMULMAX1-RV32-NEXT: vle64.v v9, (a1)
; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: li a6, 56 ; LMULMAX1-RV32-NEXT: li a2, 56
; LMULMAX1-RV32-NEXT: vsrl.vx v10, v9, a6 ; LMULMAX1-RV32-NEXT: vsrl.vx v10, v9, a2
; LMULMAX1-RV32-NEXT: li a3, 40 ; LMULMAX1-RV32-NEXT: li a3, 40
; LMULMAX1-RV32-NEXT: vsrl.vx v11, v9, a3 ; LMULMAX1-RV32-NEXT: vsrl.vx v11, v9, a3
; LMULMAX1-RV32-NEXT: lui a4, 16 ; LMULMAX1-RV32-NEXT: lui a4, 16
; LMULMAX1-RV32-NEXT: addi a4, a4, -256 ; LMULMAX1-RV32-NEXT: addi a4, a4, -256
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a4 ; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV32-NEXT: lui a5, 4080 ; LMULMAX1-RV32-NEXT: lui a5, 4080
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a5 ; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV32-NEXT: li a2, 5 ; LMULMAX1-RV32-NEXT: li a6, 5
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-RV32-NEXT: vmv.s.x v0, a2 ; LMULMAX1-RV32-NEXT: vmv.s.x v0, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.i v12, 0 ; LMULMAX1-RV32-NEXT: vmv.v.i v12, 0
; LMULMAX1-RV32-NEXT: lui a2, 1044480 ; LMULMAX1-RV32-NEXT: lui a6, 1044480
; LMULMAX1-RV32-NEXT: vmerge.vxm v12, v12, a2, v0 ; LMULMAX1-RV32-NEXT: vmerge.vxm v12, v12, a6, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v9, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v13, v9, 8
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v12 ; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v12
; LMULMAX1-RV32-NEXT: vor.vv v11, v13, v11 ; LMULMAX1-RV32-NEXT: vor.vv v11, v13, v11
; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV32-NEXT: li a2, 255 ; LMULMAX1-RV32-NEXT: li a6, 255
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v11, a2 ; LMULMAX1-RV32-NEXT: vmv.v.x v11, a6
; LMULMAX1-RV32-NEXT: vmerge.vim v11, v11, 0, v0 ; LMULMAX1-RV32-NEXT: vmerge.vim v11, v11, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vsll.vi v13, v9, 8 ; LMULMAX1-RV32-NEXT: vsll.vi v13, v9, 8
; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v11 ; LMULMAX1-RV32-NEXT: vand.vv v13, v13, v11
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v14, a4 ; LMULMAX1-RV32-NEXT: vmv.v.x v14, a4
; LMULMAX1-RV32-NEXT: vmerge.vim v14, v14, 0, v0 ; LMULMAX1-RV32-NEXT: vmerge.vim v14, v14, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vsll.vi v15, v9, 24 ; LMULMAX1-RV32-NEXT: vsll.vi v15, v9, 24
; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v14 ; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v14
; LMULMAX1-RV32-NEXT: vor.vv v13, v15, v13 ; LMULMAX1-RV32-NEXT: vor.vv v13, v15, v13
; LMULMAX1-RV32-NEXT: vsll.vx v15, v9, a3 ; LMULMAX1-RV32-NEXT: vsll.vx v15, v9, a3
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmv.v.x v16, a5 ; LMULMAX1-RV32-NEXT: vmv.v.x v16, a5
; LMULMAX1-RV32-NEXT: vmerge.vim v16, v16, 0, v0 ; LMULMAX1-RV32-NEXT: vmerge.vim v16, v16, 0, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v16 ; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v16
; LMULMAX1-RV32-NEXT: vsll.vx v9, v9, a6 ; LMULMAX1-RV32-NEXT: vsll.vx v9, v9, a2
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v15 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v15
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v13 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v13
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vsrl.vx v10, v8, a6 ; LMULMAX1-RV32-NEXT: vsrl.vx v10, v8, a2
; LMULMAX1-RV32-NEXT: vsrl.vx v13, v8, a3 ; LMULMAX1-RV32-NEXT: vsrl.vx v13, v8, a3
; LMULMAX1-RV32-NEXT: vand.vx v13, v13, a4 ; LMULMAX1-RV32-NEXT: vand.vx v13, v13, a4
; LMULMAX1-RV32-NEXT: vor.vv v10, v13, v10 ; LMULMAX1-RV32-NEXT: vor.vv v10, v13, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v8, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v13, v8, 24
; LMULMAX1-RV32-NEXT: vand.vx v13, v13, a5 ; LMULMAX1-RV32-NEXT: vand.vx v13, v13, a5
; LMULMAX1-RV32-NEXT: vsrl.vi v15, v8, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v15, v8, 8
; LMULMAX1-RV32-NEXT: vand.vv v12, v15, v12 ; LMULMAX1-RV32-NEXT: vand.vv v12, v15, v12
; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13 ; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13
; LMULMAX1-RV32-NEXT: vor.vv v10, v12, v10 ; LMULMAX1-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX1-RV32-NEXT: vsll.vi v12, v8, 8 ; LMULMAX1-RV32-NEXT: vsll.vi v12, v8, 8
; LMULMAX1-RV32-NEXT: vand.vv v11, v12, v11 ; LMULMAX1-RV32-NEXT: vand.vv v11, v12, v11
; LMULMAX1-RV32-NEXT: vsll.vi v12, v8, 24 ; LMULMAX1-RV32-NEXT: vsll.vi v12, v8, 24
; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v14 ; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v14
; LMULMAX1-RV32-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV32-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV32-NEXT: vsll.vx v12, v8, a3 ; LMULMAX1-RV32-NEXT: vsll.vx v12, v8, a3
; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v16 ; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v16
; LMULMAX1-RV32-NEXT: vsll.vx v8, v8, a6 ; LMULMAX1-RV32-NEXT: vsll.vx v8, v8, a2
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v12 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v12
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV32-NEXT: vse64.v v9, (a1) ; LMULMAX1-RV32-NEXT: vse64.v v9, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: bswap_v4i64: ; LMULMAX1-RV64-LABEL: bswap_v4i64:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi t1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v8, (t1) ; LMULMAX1-RV64-NEXT: vle64.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle64.v v9, (a0) ; LMULMAX1-RV64-NEXT: vle64.v v9, (a0)
; LMULMAX1-RV64-NEXT: li a7, 56 ; LMULMAX1-RV64-NEXT: li a2, 56
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a7 ; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a2
; LMULMAX1-RV64-NEXT: li t0, 40 ; LMULMAX1-RV64-NEXT: li a3, 40
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v8, t0 ; LMULMAX1-RV64-NEXT: vsrl.vx v11, v8, a3
; LMULMAX1-RV64-NEXT: lui a4, 16 ; LMULMAX1-RV64-NEXT: lui a4, 16
; LMULMAX1-RV64-NEXT: addiw a4, a4, -256 ; LMULMAX1-RV64-NEXT: addiw a4, a4, -256
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV64-NEXT: lui a6, 4080 ; LMULMAX1-RV64-NEXT: lui a5, 4080
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV64-NEXT: vsrl.vi v12, v8, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v12, v8, 8
; LMULMAX1-RV64-NEXT: li a5, 255 ; LMULMAX1-RV64-NEXT: li a6, 255
; LMULMAX1-RV64-NEXT: slli a2, a5, 24 ; LMULMAX1-RV64-NEXT: slli a7, a6, 24
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a2 ; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a7
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 8
; LMULMAX1-RV64-NEXT: slli a3, a5, 32 ; LMULMAX1-RV64-NEXT: slli t0, a6, 32
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a3 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t0
; LMULMAX1-RV64-NEXT: vsll.vi v12, v8, 24 ; LMULMAX1-RV64-NEXT: vsll.vi v12, v8, 24
; LMULMAX1-RV64-NEXT: slli a1, a5, 40 ; LMULMAX1-RV64-NEXT: slli t1, a6, 40
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a1 ; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t1
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vsll.vx v12, v8, a7 ; LMULMAX1-RV64-NEXT: vsll.vx v12, v8, a2
; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, t0 ; LMULMAX1-RV64-NEXT: vsll.vx v8, v8, a3
; LMULMAX1-RV64-NEXT: slli a5, a5, 48 ; LMULMAX1-RV64-NEXT: slli a6, a6, 48
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: vor.vv v8, v12, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v12, v8
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, a7 ; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, a2
; LMULMAX1-RV64-NEXT: vsrl.vx v11, v9, t0 ; LMULMAX1-RV64-NEXT: vsrl.vx v11, v9, a3
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a6 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a5
; LMULMAX1-RV64-NEXT: vsrl.vi v12, v9, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v12, v9, 8
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a2 ; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a7
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV64-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 8
; LMULMAX1-RV64-NEXT: vand.vx v11, v11, a3 ; LMULMAX1-RV64-NEXT: vand.vx v11, v11, t0
; LMULMAX1-RV64-NEXT: vsll.vi v12, v9, 24 ; LMULMAX1-RV64-NEXT: vsll.vi v12, v9, 24
; LMULMAX1-RV64-NEXT: vand.vx v12, v12, a1 ; LMULMAX1-RV64-NEXT: vand.vx v12, v12, t1
; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11 ; LMULMAX1-RV64-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV64-NEXT: vsll.vx v12, v9, a7 ; LMULMAX1-RV64-NEXT: vsll.vx v12, v9, a2
; LMULMAX1-RV64-NEXT: vsll.vx v9, v9, t0 ; LMULMAX1-RV64-NEXT: vsll.vx v9, v9, a3
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vor.vv v9, v12, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v12, v9
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vse64.v v9, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v8, (t1) ; LMULMAX1-RV64-NEXT: vse64.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x %a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y %b = load <4 x i64>, <4 x i64>* %y
%c = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a) %c = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
store <4 x i64> %c, <4 x i64>* %x store <4 x i64> %c, <4 x i64>* %x
ret void ret void
} }
declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll

Show First 20 Lines • Show All 1,740 Lines • ▼ Show 20 Lines
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 2
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 16 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 16
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: li a6, 32 ; LMULMAX1-RV64-NEXT: li a2, 32
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a6 ; LMULMAX1-RV64-NEXT: vsrl.vx v10, v8, a2
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vxor.vi v8, v8, -1 ; LMULMAX1-RV64-NEXT: vxor.vi v8, v8, -1
; LMULMAX1-RV64-NEXT: lui a3, %hi(.LCPI7_0) ; LMULMAX1-RV64-NEXT: lui a3, %hi(.LCPI7_0)
; LMULMAX1-RV64-NEXT: ld a3, %lo(.LCPI7_0)(a3) ; LMULMAX1-RV64-NEXT: ld a3, %lo(.LCPI7_0)(a3)
; LMULMAX1-RV64-NEXT: lui a4, %hi(.LCPI7_1) ; LMULMAX1-RV64-NEXT: lui a4, %hi(.LCPI7_1)
; LMULMAX1-RV64-NEXT: ld a4, %lo(.LCPI7_1)(a4) ; LMULMAX1-RV64-NEXT: ld a4, %lo(.LCPI7_1)(a4)
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vand.vx v10, v8, a4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v8, a4
; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: lui a5, %hi(.LCPI7_2) ; LMULMAX1-RV64-NEXT: lui a5, %hi(.LCPI7_2)
; LMULMAX1-RV64-NEXT: ld a5, %lo(.LCPI7_2)(a5) ; LMULMAX1-RV64-NEXT: ld a5, %lo(.LCPI7_2)(a5)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI7_3) ; LMULMAX1-RV64-NEXT: lui a6, %hi(.LCPI7_3)
; LMULMAX1-RV64-NEXT: ld a2, %lo(.LCPI7_3)(a2) ; LMULMAX1-RV64-NEXT: ld a6, %lo(.LCPI7_3)(a6)
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a2 ; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: li a7, 56 ; LMULMAX1-RV64-NEXT: li a7, 56
; LMULMAX1-RV64-NEXT: vsrl.vx v8, v8, a7 ; LMULMAX1-RV64-NEXT: vsrl.vx v8, v8, a7
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 16 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 16
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, a6 ; LMULMAX1-RV64-NEXT: vsrl.vx v10, v9, a2
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vxor.vi v9, v9, -1 ; LMULMAX1-RV64-NEXT: vxor.vi v9, v9, -1
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vand.vx v10, v9, a4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v9, a4
; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 2
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a2 ; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vsrl.vx v9, v9, a7 ; LMULMAX1-RV64-NEXT: vsrl.vx v9, v9, a7
; LMULMAX1-RV64-NEXT: vse64.v v9, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v8, (a1) ; LMULMAX1-RV64-NEXT: vse64.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
; ;
; LMULMAX8-RV32-LABEL: ctlz_v4i64: ; LMULMAX8-RV32-LABEL: ctlz_v4i64:
; LMULMAX8-RV32: # %bb.0: ; LMULMAX8-RV32: # %bb.0:
; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll

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; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: cttz_v16i16: ; LMULMAX1-RV32-LABEL: cttz_v16i16:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle16.v v8, (a1) ; LMULMAX1-RV32-NEXT: vle16.v v8, (a1)
; LMULMAX1-RV32-NEXT: vle16.v v9, (a0) ; LMULMAX1-RV32-NEXT: vle16.v v9, (a0)
; LMULMAX1-RV32-NEXT: li a6, 1 ; LMULMAX1-RV32-NEXT: li a2, 1
; LMULMAX1-RV32-NEXT: vsub.vx v10, v8, a6 ; LMULMAX1-RV32-NEXT: vsub.vx v10, v8, a2
; LMULMAX1-RV32-NEXT: vxor.vi v8, v8, -1 ; LMULMAX1-RV32-NEXT: vxor.vi v8, v8, -1
; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV32-NEXT: lui a3, 5 ; LMULMAX1-RV32-NEXT: lui a3, 5
; LMULMAX1-RV32-NEXT: addi a3, a3, 1365 ; LMULMAX1-RV32-NEXT: addi a3, a3, 1365
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: lui a4, 3 ; LMULMAX1-RV32-NEXT: lui a4, 3
; LMULMAX1-RV32-NEXT: addi a4, a4, 819 ; LMULMAX1-RV32-NEXT: addi a4, a4, 819
; LMULMAX1-RV32-NEXT: vand.vx v10, v8, a4 ; LMULMAX1-RV32-NEXT: vand.vx v10, v8, a4
; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2 ; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV32-NEXT: vadd.vv v8, v10, v8 ; LMULMAX1-RV32-NEXT: vadd.vv v8, v10, v8
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: lui a5, 1 ; LMULMAX1-RV32-NEXT: lui a5, 1
; LMULMAX1-RV32-NEXT: addi a5, a5, -241 ; LMULMAX1-RV32-NEXT: addi a5, a5, -241
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV32-NEXT: li a2, 257 ; LMULMAX1-RV32-NEXT: li a6, 257
; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a2 ; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a6
; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 8
; LMULMAX1-RV32-NEXT: vsub.vx v10, v9, a6 ; LMULMAX1-RV32-NEXT: vsub.vx v10, v9, a2
; LMULMAX1-RV32-NEXT: vxor.vi v9, v9, -1 ; LMULMAX1-RV32-NEXT: vxor.vi v9, v9, -1
; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10 ; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10 ; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vand.vx v10, v9, a4 ; LMULMAX1-RV32-NEXT: vand.vx v10, v9, a4
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 2 ; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 2
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4 ; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4
; LMULMAX1-RV32-NEXT: vadd.vv v9, v10, v9 ; LMULMAX1-RV32-NEXT: vadd.vv v9, v10, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10 ; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a5 ; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV32-NEXT: vmul.vx v9, v9, a2 ; LMULMAX1-RV32-NEXT: vmul.vx v9, v9, a6
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 8
; LMULMAX1-RV32-NEXT: vse16.v v9, (a0) ; LMULMAX1-RV32-NEXT: vse16.v v9, (a0)
; LMULMAX1-RV32-NEXT: vse16.v v8, (a1) ; LMULMAX1-RV32-NEXT: vse16.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: cttz_v16i16: ; LMULMAX1-RV64-LABEL: cttz_v16i16:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-RV64-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle16.v v8, (a1) ; LMULMAX1-RV64-NEXT: vle16.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle16.v v9, (a0) ; LMULMAX1-RV64-NEXT: vle16.v v9, (a0)
; LMULMAX1-RV64-NEXT: li a6, 1 ; LMULMAX1-RV64-NEXT: li a2, 1
; LMULMAX1-RV64-NEXT: vsub.vx v10, v8, a6 ; LMULMAX1-RV64-NEXT: vsub.vx v10, v8, a2
; LMULMAX1-RV64-NEXT: vxor.vi v8, v8, -1 ; LMULMAX1-RV64-NEXT: vxor.vi v8, v8, -1
; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: lui a3, 5 ; LMULMAX1-RV64-NEXT: lui a3, 5
; LMULMAX1-RV64-NEXT: addiw a3, a3, 1365 ; LMULMAX1-RV64-NEXT: addiw a3, a3, 1365
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: lui a4, 3 ; LMULMAX1-RV64-NEXT: lui a4, 3
; LMULMAX1-RV64-NEXT: addiw a4, a4, 819 ; LMULMAX1-RV64-NEXT: addiw a4, a4, 819
; LMULMAX1-RV64-NEXT: vand.vx v10, v8, a4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v8, a4
; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: lui a5, 1 ; LMULMAX1-RV64-NEXT: lui a5, 1
; LMULMAX1-RV64-NEXT: addiw a5, a5, -241 ; LMULMAX1-RV64-NEXT: addiw a5, a5, -241
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV64-NEXT: li a2, 257 ; LMULMAX1-RV64-NEXT: li a6, 257
; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a2 ; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 8
; LMULMAX1-RV64-NEXT: vsub.vx v10, v9, a6 ; LMULMAX1-RV64-NEXT: vsub.vx v10, v9, a2
; LMULMAX1-RV64-NEXT: vxor.vi v9, v9, -1 ; LMULMAX1-RV64-NEXT: vxor.vi v9, v9, -1
; LMULMAX1-RV64-NEXT: vand.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vand.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vand.vx v10, v9, a4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v9, a4
; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 2
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a2 ; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 8
; LMULMAX1-RV64-NEXT: vse16.v v9, (a0) ; LMULMAX1-RV64-NEXT: vse16.v v9, (a0)
; LMULMAX1-RV64-NEXT: vse16.v v8, (a1) ; LMULMAX1-RV64-NEXT: vse16.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
; ;
; LMULMAX8-RV32-LABEL: cttz_v16i16: ; LMULMAX8-RV32-LABEL: cttz_v16i16:
; LMULMAX8-RV32: # %bb.0: ; LMULMAX8-RV32: # %bb.0:
; LMULMAX8-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; LMULMAX8-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, mu
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; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: cttz_v8i32: ; LMULMAX1-RV32-LABEL: cttz_v8i32:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV32-NEXT: vle32.v v9, (a0) ; LMULMAX1-RV32-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV32-NEXT: li a6, 1 ; LMULMAX1-RV32-NEXT: li a2, 1
; LMULMAX1-RV32-NEXT: vsub.vx v10, v8, a6 ; LMULMAX1-RV32-NEXT: vsub.vx v10, v8, a2
; LMULMAX1-RV32-NEXT: vxor.vi v8, v8, -1 ; LMULMAX1-RV32-NEXT: vxor.vi v8, v8, -1
; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV32-NEXT: lui a3, 349525 ; LMULMAX1-RV32-NEXT: lui a3, 349525
; LMULMAX1-RV32-NEXT: addi a3, a3, 1365 ; LMULMAX1-RV32-NEXT: addi a3, a3, 1365
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: lui a4, 209715 ; LMULMAX1-RV32-NEXT: lui a4, 209715
; LMULMAX1-RV32-NEXT: addi a4, a4, 819 ; LMULMAX1-RV32-NEXT: addi a4, a4, 819
; LMULMAX1-RV32-NEXT: vand.vx v10, v8, a4 ; LMULMAX1-RV32-NEXT: vand.vx v10, v8, a4
; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2 ; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 2
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV32-NEXT: vadd.vv v8, v10, v8 ; LMULMAX1-RV32-NEXT: vadd.vv v8, v10, v8
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: lui a5, 61681 ; LMULMAX1-RV32-NEXT: lui a5, 61681
; LMULMAX1-RV32-NEXT: addi a5, a5, -241 ; LMULMAX1-RV32-NEXT: addi a5, a5, -241
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV32-NEXT: lui a2, 4112 ; LMULMAX1-RV32-NEXT: lui a6, 4112
; LMULMAX1-RV32-NEXT: addi a2, a2, 257 ; LMULMAX1-RV32-NEXT: addi a6, a6, 257
; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a2 ; LMULMAX1-RV32-NEXT: vmul.vx v8, v8, a6
; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v8, v8, 24
; LMULMAX1-RV32-NEXT: vsub.vx v10, v9, a6 ; LMULMAX1-RV32-NEXT: vsub.vx v10, v9, a2
; LMULMAX1-RV32-NEXT: vxor.vi v9, v9, -1 ; LMULMAX1-RV32-NEXT: vxor.vi v9, v9, -1
; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10 ; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10 ; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vand.vx v10, v9, a4 ; LMULMAX1-RV32-NEXT: vand.vx v10, v9, a4
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 2 ; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 2
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4 ; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a4
; LMULMAX1-RV32-NEXT: vadd.vv v9, v10, v9 ; LMULMAX1-RV32-NEXT: vadd.vv v9, v10, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10 ; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a5 ; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV32-NEXT: vmul.vx v9, v9, a2 ; LMULMAX1-RV32-NEXT: vmul.vx v9, v9, a6
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v9, v9, 24
; LMULMAX1-RV32-NEXT: vse32.v v9, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1-RV32-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV32-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: cttz_v8i32: ; LMULMAX1-RV64-LABEL: cttz_v8i32:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle32.v v9, (a0) ; LMULMAX1-RV64-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV64-NEXT: li a6, 1 ; LMULMAX1-RV64-NEXT: li a2, 1
; LMULMAX1-RV64-NEXT: vsub.vx v10, v8, a6 ; LMULMAX1-RV64-NEXT: vsub.vx v10, v8, a2
; LMULMAX1-RV64-NEXT: vxor.vi v8, v8, -1 ; LMULMAX1-RV64-NEXT: vxor.vi v8, v8, -1
; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: lui a3, 349525 ; LMULMAX1-RV64-NEXT: lui a3, 349525
; LMULMAX1-RV64-NEXT: addiw a3, a3, 1365 ; LMULMAX1-RV64-NEXT: addiw a3, a3, 1365
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: lui a4, 209715 ; LMULMAX1-RV64-NEXT: lui a4, 209715
; LMULMAX1-RV64-NEXT: addiw a4, a4, 819 ; LMULMAX1-RV64-NEXT: addiw a4, a4, 819
; LMULMAX1-RV64-NEXT: vand.vx v10, v8, a4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v8, a4
; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: lui a5, 61681 ; LMULMAX1-RV64-NEXT: lui a5, 61681
; LMULMAX1-RV64-NEXT: addiw a5, a5, -241 ; LMULMAX1-RV64-NEXT: addiw a5, a5, -241
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV64-NEXT: lui a2, 4112 ; LMULMAX1-RV64-NEXT: lui a6, 4112
; LMULMAX1-RV64-NEXT: addiw a2, a2, 257 ; LMULMAX1-RV64-NEXT: addiw a6, a6, 257
; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a2 ; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 24
; LMULMAX1-RV64-NEXT: vsub.vx v10, v9, a6 ; LMULMAX1-RV64-NEXT: vsub.vx v10, v9, a2
; LMULMAX1-RV64-NEXT: vxor.vi v9, v9, -1 ; LMULMAX1-RV64-NEXT: vxor.vi v9, v9, -1
; LMULMAX1-RV64-NEXT: vand.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vand.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vand.vx v10, v9, a4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v9, a4
; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 2
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a2 ; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 24
; LMULMAX1-RV64-NEXT: vse32.v v9, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1-RV64-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV64-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
; ;
; LMULMAX8-RV32-LABEL: cttz_v8i32: ; LMULMAX8-RV32-LABEL: cttz_v8i32:
; LMULMAX8-RV32: # %bb.0: ; LMULMAX8-RV32: # %bb.0:
; LMULMAX8-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu ; LMULMAX8-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, mu
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; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: cttz_v4i64: ; LMULMAX1-RV64-LABEL: cttz_v4i64:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v8, (a1) ; LMULMAX1-RV64-NEXT: vle64.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle64.v v9, (a0) ; LMULMAX1-RV64-NEXT: vle64.v v9, (a0)
; LMULMAX1-RV64-NEXT: li a6, 1 ; LMULMAX1-RV64-NEXT: li a2, 1
; LMULMAX1-RV64-NEXT: vsub.vx v10, v8, a6 ; LMULMAX1-RV64-NEXT: vsub.vx v10, v8, a2
; LMULMAX1-RV64-NEXT: vxor.vi v8, v8, -1 ; LMULMAX1-RV64-NEXT: vxor.vi v8, v8, -1
; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vand.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: lui a3, %hi(.LCPI7_0) ; LMULMAX1-RV64-NEXT: lui a3, %hi(.LCPI7_0)
; LMULMAX1-RV64-NEXT: ld a3, %lo(.LCPI7_0)(a3) ; LMULMAX1-RV64-NEXT: ld a3, %lo(.LCPI7_0)(a3)
; LMULMAX1-RV64-NEXT: lui a4, %hi(.LCPI7_1) ; LMULMAX1-RV64-NEXT: lui a4, %hi(.LCPI7_1)
; LMULMAX1-RV64-NEXT: ld a4, %lo(.LCPI7_1)(a4) ; LMULMAX1-RV64-NEXT: ld a4, %lo(.LCPI7_1)(a4)
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vand.vx v10, v8, a4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v8, a4
; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a4
; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: lui a5, %hi(.LCPI7_2) ; LMULMAX1-RV64-NEXT: lui a5, %hi(.LCPI7_2)
; LMULMAX1-RV64-NEXT: ld a5, %lo(.LCPI7_2)(a5) ; LMULMAX1-RV64-NEXT: ld a5, %lo(.LCPI7_2)(a5)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI7_3) ; LMULMAX1-RV64-NEXT: lui a6, %hi(.LCPI7_3)
; LMULMAX1-RV64-NEXT: ld a2, %lo(.LCPI7_3)(a2) ; LMULMAX1-RV64-NEXT: ld a6, %lo(.LCPI7_3)(a6)
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a2 ; LMULMAX1-RV64-NEXT: vmul.vx v8, v8, a6
; LMULMAX1-RV64-NEXT: li a7, 56 ; LMULMAX1-RV64-NEXT: li a7, 56
; LMULMAX1-RV64-NEXT: vsrl.vx v8, v8, a7 ; LMULMAX1-RV64-NEXT: vsrl.vx v8, v8, a7
; LMULMAX1-RV64-NEXT: vsub.vx v10, v9, a6 ; LMULMAX1-RV64-NEXT: vsub.vx v10, v9, a2
; LMULMAX1-RV64-NEXT: vxor.vi v9, v9, -1 ; LMULMAX1-RV64-NEXT: vxor.vi v9, v9, -1
; LMULMAX1-RV64-NEXT: vand.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vand.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 1
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vand.vx v10, v9, a4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v9, a4
; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v9, v9, 2
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a4
; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a2 ; LMULMAX1-RV64-NEXT: vmul.vx v9, v9, a6
; LMULMAX1-RV64-NEXT: vsrl.vx v9, v9, a7 ; LMULMAX1-RV64-NEXT: vsrl.vx v9, v9, a7
; LMULMAX1-RV64-NEXT: vse64.v v9, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v8, (a1) ; LMULMAX1-RV64-NEXT: vse64.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
; ;
; LMULMAX8-RV32-LABEL: cttz_v4i64: ; LMULMAX8-RV32-LABEL: cttz_v4i64:
; LMULMAX8-RV32: # %bb.0: ; LMULMAX8-RV32: # %bb.0:
; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, mu
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll

Show All 23 Lines; CHECK-NEXT: ret
ret void ret void
} }
; i64 vectors should be scalarized ; i64 vectors should be scalarized
define void @add_v2i64(<2 x i64>* %x, <2 x i64>* %y) { define void @add_v2i64(<2 x i64>* %x, <2 x i64>* %y) {
; RV32-LABEL: add_v2i64: ; RV32-LABEL: add_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: lw a2, 8(a0) ; RV32-NEXT: lw a2, 8(a0)
; RV32-NEXT: lw a6, 12(a0) ; RV32-NEXT: lw a3, 12(a0)
; RV32-NEXT: lw a4, 0(a0) ; RV32-NEXT: lw a4, 0(a0)
; RV32-NEXT: lw a7, 4(a0) ; RV32-NEXT: lw a5, 4(a0)
; RV32-NEXT: lw a3, 4(a1) ; RV32-NEXT: lw a6, 4(a1)
; RV32-NEXT: lw a5, 0(a1) ; RV32-NEXT: lw a7, 0(a1)
; RV32-NEXT: lw t0, 8(a1) ; RV32-NEXT: lw t0, 8(a1)
; RV32-NEXT: lw a1, 12(a1) ; RV32-NEXT: lw a1, 12(a1)
; RV32-NEXT: add a3, a7, a3 ; RV32-NEXT: add a5, a5, a6
; RV32-NEXT: add a5, a4, a5 ; RV32-NEXT: add a6, a4, a7
; RV32-NEXT: sltu a4, a5, a4 ; RV32-NEXT: sltu a4, a6, a4
; RV32-NEXT: add a3, a3, a4 ; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: add a1, a6, a1 ; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add a4, a2, t0 ; RV32-NEXT: add a3, a2, t0
; RV32-NEXT: sltu a2, a4, a2 ; RV32-NEXT: sltu a2, a3, a2
; RV32-NEXT: add a1, a1, a2 ; RV32-NEXT: add a1, a1, a2
; RV32-NEXT: sw a4, 8(a0) ; RV32-NEXT: sw a3, 8(a0)
; RV32-NEXT: sw a5, 0(a0) ; RV32-NEXT: sw a6, 0(a0)
; RV32-NEXT: sw a1, 12(a0) ; RV32-NEXT: sw a1, 12(a0)
; RV32-NEXT: sw a3, 4(a0) ; RV32-NEXT: sw a4, 4(a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: add_v2i64: ; RV64-LABEL: add_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: ld a2, 8(a0) ; RV64-NEXT: ld a2, 8(a0)
; RV64-NEXT: ld a3, 0(a0) ; RV64-NEXT: ld a3, 0(a0)
; RV64-NEXT: ld a4, 0(a1) ; RV64-NEXT: ld a4, 0(a1)
; RV64-NEXT: ld a1, 8(a1) ; RV64-NEXT: ld a1, 8(a1)
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; LMULMAX8-NEXT: li a2, 64 ; LMULMAX8-NEXT: li a2, 64
; LMULMAX8-NEXT: vsetvli zero, a2, e16, m8, ta, mu ; LMULMAX8-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; LMULMAX8-NEXT: vlse16.v v8, (a1), zero ; LMULMAX8-NEXT: vlse16.v v8, (a1), zero
; LMULMAX8-NEXT: vse16.v v8, (a0) ; LMULMAX8-NEXT: vse16.v v8, (a0)
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: gather_const_v64f16: ; LMULMAX1-LABEL: gather_const_v64f16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a6, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a7, a0, 48 ; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: addi a3, a0, 32 ; LMULMAX1-NEXT: addi a3, a0, 32
; LMULMAX1-NEXT: addi a4, a0, 80 ; LMULMAX1-NEXT: addi a4, a0, 80
; LMULMAX1-NEXT: addi a5, a0, 94 ; LMULMAX1-NEXT: addi a5, a0, 94
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; LMULMAX1-NEXT: vlse16.v v8, (a5), zero ; LMULMAX1-NEXT: vlse16.v v8, (a5), zero
; LMULMAX1-NEXT: addi a5, a0, 64 ; LMULMAX1-NEXT: addi a5, a0, 64
; LMULMAX1-NEXT: addi a1, a0, 112 ; LMULMAX1-NEXT: addi a6, a0, 112
; LMULMAX1-NEXT: addi a2, a0, 96 ; LMULMAX1-NEXT: addi a7, a0, 96
; LMULMAX1-NEXT: vse16.v v8, (a2) ; LMULMAX1-NEXT: vse16.v v8, (a7)
; LMULMAX1-NEXT: vse16.v v8, (a1) ; LMULMAX1-NEXT: vse16.v v8, (a6)
; LMULMAX1-NEXT: vse16.v v8, (a5) ; LMULMAX1-NEXT: vse16.v v8, (a5)
; LMULMAX1-NEXT: vse16.v v8, (a4) ; LMULMAX1-NEXT: vse16.v v8, (a4)
; LMULMAX1-NEXT: vse16.v v8, (a3) ; LMULMAX1-NEXT: vse16.v v8, (a3)
; LMULMAX1-NEXT: vse16.v v8, (a7) ; LMULMAX1-NEXT: vse16.v v8, (a2)
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: vse16.v v8, (a6) ; LMULMAX1-NEXT: vse16.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <64 x half>, <64 x half>* %x %a = load <64 x half>, <64 x half>* %x
%b = extractelement <64 x half> %a, i32 47 %b = extractelement <64 x half> %a, i32 47
%c = insertelement <64 x half> undef, half %b, i32 0 %c = insertelement <64 x half> undef, half %b, i32 0
%d = shufflevector <64 x half> %c, <64 x half> undef, <64 x i32> zeroinitializer %d = shufflevector <64 x half> %c, <64 x half> undef, <64 x i32> zeroinitializer
store <64 x half> %d, <64 x half>* %x store <64 x half> %d, <64 x half>* %x
ret void ret void
} }
define void @gather_const_v32f32(<32 x float>* %x) { define void @gather_const_v32f32(<32 x float>* %x) {
; LMULMAX8-LABEL: gather_const_v32f32: ; LMULMAX8-LABEL: gather_const_v32f32:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: addi a1, a0, 68 ; LMULMAX8-NEXT: addi a1, a0, 68
; LMULMAX8-NEXT: li a2, 32 ; LMULMAX8-NEXT: li a2, 32
; LMULMAX8-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; LMULMAX8-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; LMULMAX8-NEXT: vlse32.v v8, (a1), zero ; LMULMAX8-NEXT: vlse32.v v8, (a1), zero
; LMULMAX8-NEXT: vse32.v v8, (a0) ; LMULMAX8-NEXT: vse32.v v8, (a0)
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: gather_const_v32f32: ; LMULMAX1-LABEL: gather_const_v32f32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a6, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a7, a0, 48 ; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: addi a3, a0, 32 ; LMULMAX1-NEXT: addi a3, a0, 32
; LMULMAX1-NEXT: addi a4, a0, 80 ; LMULMAX1-NEXT: addi a4, a0, 80
; LMULMAX1-NEXT: addi a5, a0, 68 ; LMULMAX1-NEXT: addi a5, a0, 68
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; LMULMAX1-NEXT: vlse32.v v8, (a5), zero ; LMULMAX1-NEXT: vlse32.v v8, (a5), zero
; LMULMAX1-NEXT: addi a5, a0, 64 ; LMULMAX1-NEXT: addi a5, a0, 64
; LMULMAX1-NEXT: addi a1, a0, 112 ; LMULMAX1-NEXT: addi a6, a0, 112
; LMULMAX1-NEXT: addi a2, a0, 96 ; LMULMAX1-NEXT: addi a7, a0, 96
; LMULMAX1-NEXT: vse32.v v8, (a2) ; LMULMAX1-NEXT: vse32.v v8, (a7)
; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: vse32.v v8, (a6)
; LMULMAX1-NEXT: vse32.v v8, (a5) ; LMULMAX1-NEXT: vse32.v v8, (a5)
; LMULMAX1-NEXT: vse32.v v8, (a4) ; LMULMAX1-NEXT: vse32.v v8, (a4)
; LMULMAX1-NEXT: vse32.v v8, (a3) ; LMULMAX1-NEXT: vse32.v v8, (a3)
; LMULMAX1-NEXT: vse32.v v8, (a7) ; LMULMAX1-NEXT: vse32.v v8, (a2)
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: vse32.v v8, (a6) ; LMULMAX1-NEXT: vse32.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <32 x float>, <32 x float>* %x %a = load <32 x float>, <32 x float>* %x
%b = extractelement <32 x float> %a, i32 17 %b = extractelement <32 x float> %a, i32 17
%c = insertelement <32 x float> undef, float %b, i32 0 %c = insertelement <32 x float> undef, float %b, i32 0
%d = shufflevector <32 x float> %c, <32 x float> undef, <32 x i32> zeroinitializer %d = shufflevector <32 x float> %c, <32 x float> undef, <32 x i32> zeroinitializer
store <32 x float> %d, <32 x float>* %x store <32 x float> %d, <32 x float>* %x
ret void ret void
} }
define void @gather_const_v16f64(<16 x double>* %x) { define void @gather_const_v16f64(<16 x double>* %x) {
; LMULMAX8-LABEL: gather_const_v16f64: ; LMULMAX8-LABEL: gather_const_v16f64:
; LMULMAX8: # %bb.0: ; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: addi a1, a0, 80 ; LMULMAX8-NEXT: addi a1, a0, 80
; LMULMAX8-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; LMULMAX8-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; LMULMAX8-NEXT: vlse64.v v8, (a1), zero ; LMULMAX8-NEXT: vlse64.v v8, (a1), zero
; LMULMAX8-NEXT: vse64.v v8, (a0) ; LMULMAX8-NEXT: vse64.v v8, (a0)
; LMULMAX8-NEXT: ret ; LMULMAX8-NEXT: ret
; ;
; LMULMAX1-LABEL: gather_const_v16f64: ; LMULMAX1-LABEL: gather_const_v16f64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a6, a0, 16 ; LMULMAX1-NEXT: addi a1, a0, 16
; LMULMAX1-NEXT: addi a7, a0, 48 ; LMULMAX1-NEXT: addi a2, a0, 48
; LMULMAX1-NEXT: addi a3, a0, 32 ; LMULMAX1-NEXT: addi a3, a0, 32
; LMULMAX1-NEXT: addi a4, a0, 80 ; LMULMAX1-NEXT: addi a4, a0, 80
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; LMULMAX1-NEXT: vlse64.v v8, (a4), zero ; LMULMAX1-NEXT: vlse64.v v8, (a4), zero
; LMULMAX1-NEXT: addi a5, a0, 64 ; LMULMAX1-NEXT: addi a5, a0, 64
; LMULMAX1-NEXT: addi a1, a0, 112 ; LMULMAX1-NEXT: addi a6, a0, 112
; LMULMAX1-NEXT: addi a2, a0, 96 ; LMULMAX1-NEXT: addi a7, a0, 96
; LMULMAX1-NEXT: vse64.v v8, (a2) ; LMULMAX1-NEXT: vse64.v v8, (a7)
; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: vse64.v v8, (a6)
; LMULMAX1-NEXT: vse64.v v8, (a5) ; LMULMAX1-NEXT: vse64.v v8, (a5)
; LMULMAX1-NEXT: vse64.v v8, (a4) ; LMULMAX1-NEXT: vse64.v v8, (a4)
; LMULMAX1-NEXT: vse64.v v8, (a3) ; LMULMAX1-NEXT: vse64.v v8, (a3)
; LMULMAX1-NEXT: vse64.v v8, (a7) ; LMULMAX1-NEXT: vse64.v v8, (a2)
; LMULMAX1-NEXT: vse64.v v8, (a0) ; LMULMAX1-NEXT: vse64.v v8, (a0)
; LMULMAX1-NEXT: vse64.v v8, (a6) ; LMULMAX1-NEXT: vse64.v v8, (a1)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = load <16 x double>, <16 x double>* %x %a = load <16 x double>, <16 x double>* %x
%b = extractelement <16 x double> %a, i32 10 %b = extractelement <16 x double> %a, i32 10
%c = insertelement <16 x double> undef, double %b, i32 0 %c = insertelement <16 x double> undef, double %b, i32 0
%d = shufflevector <16 x double> %c, <16 x double> undef, <16 x i32> zeroinitializer %d = shufflevector <16 x double> %c, <16 x double> undef, <16 x i32> zeroinitializer
store <16 x double> %d, <16 x double>* %x store <16 x double> %d, <16 x double>* %x
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll

Show First 20 Lines • Show All 542 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmsne.vi v8, v9, 0 ; RV32-NEXT: vmsne.vi v8, v9, 0
; RV32-NEXT: addi a2, sp, 15 ; RV32-NEXT: addi a2, sp, 15
; RV32-NEXT: vsm.v v8, (a2) ; RV32-NEXT: vsm.v v8, (a2)
; RV32-NEXT: lbu a2, 15(sp) ; RV32-NEXT: lbu a2, 15(sp)
; RV32-NEXT: andi a3, a2, 1 ; RV32-NEXT: andi a3, a2, 1
; RV32-NEXT: beqz a3, .LBB8_2 ; RV32-NEXT: beqz a3, .LBB8_2
; RV32-NEXT: # %bb.1: # %cond.load ; RV32-NEXT: # %bb.1: # %cond.load
; RV32-NEXT: lbu a6, 1(a0) ; RV32-NEXT: lbu a3, 1(a0)
; RV32-NEXT: lbu a7, 0(a0) ; RV32-NEXT: lbu a4, 0(a0)
; RV32-NEXT: lbu a5, 3(a0) ; RV32-NEXT: lbu a5, 3(a0)
; RV32-NEXT: lbu a3, 2(a0) ; RV32-NEXT: lbu a6, 2(a0)
; RV32-NEXT: slli a4, a6, 8 ; RV32-NEXT: slli a3, a3, 8
; RV32-NEXT: or a4, a4, a7
; RV32-NEXT: slli a5, a5, 8
; RV32-NEXT: or a3, a5, a3
; RV32-NEXT: slli a3, a3, 16
; RV32-NEXT: or a3, a3, a4 ; RV32-NEXT: or a3, a3, a4
; RV32-NEXT: slli a4, a5, 8
; RV32-NEXT: or a4, a4, a6
; RV32-NEXT: slli a4, a4, 16
; RV32-NEXT: or a3, a4, a3
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vmv.v.x v8, a3 ; RV32-NEXT: vmv.v.x v8, a3
; RV32-NEXT: andi a2, a2, 2 ; RV32-NEXT: andi a2, a2, 2
; RV32-NEXT: bnez a2, .LBB8_3 ; RV32-NEXT: bnez a2, .LBB8_3
; RV32-NEXT: j .LBB8_4 ; RV32-NEXT: j .LBB8_4
; RV32-NEXT: .LBB8_2: ; RV32-NEXT: .LBB8_2:
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV32-NEXT: vmv.v.i v8, 0 ; RV32-NEXT: vmv.v.i v8, 0
Show All 34 Lines
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmsne.vi v8, v9, 0 ; RV64-NEXT: vmsne.vi v8, v9, 0
; RV64-NEXT: addi a2, sp, 15 ; RV64-NEXT: addi a2, sp, 15
; RV64-NEXT: vsm.v v8, (a2) ; RV64-NEXT: vsm.v v8, (a2)
; RV64-NEXT: lbu a2, 15(sp) ; RV64-NEXT: lbu a2, 15(sp)
; RV64-NEXT: andi a3, a2, 1 ; RV64-NEXT: andi a3, a2, 1
; RV64-NEXT: beqz a3, .LBB8_2 ; RV64-NEXT: beqz a3, .LBB8_2
; RV64-NEXT: # %bb.1: # %cond.load ; RV64-NEXT: # %bb.1: # %cond.load
; RV64-NEXT: lbu a6, 1(a0) ; RV64-NEXT: lbu a3, 1(a0)
; RV64-NEXT: lbu a7, 0(a0) ; RV64-NEXT: lbu a4, 0(a0)
; RV64-NEXT: lb a5, 3(a0) ; RV64-NEXT: lb a5, 3(a0)
; RV64-NEXT: lbu a3, 2(a0) ; RV64-NEXT: lbu a6, 2(a0)
; RV64-NEXT: slli a4, a6, 8 ; RV64-NEXT: slli a3, a3, 8
; RV64-NEXT: or a4, a4, a7
; RV64-NEXT: slli a5, a5, 8
; RV64-NEXT: or a3, a5, a3
; RV64-NEXT: slli a3, a3, 16
; RV64-NEXT: or a3, a3, a4 ; RV64-NEXT: or a3, a3, a4
; RV64-NEXT: slli a4, a5, 8
; RV64-NEXT: or a4, a4, a6
; RV64-NEXT: slli a4, a4, 16
; RV64-NEXT: or a3, a4, a3
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vmv.v.x v8, a3 ; RV64-NEXT: vmv.v.x v8, a3
; RV64-NEXT: andi a2, a2, 2 ; RV64-NEXT: andi a2, a2, 2
; RV64-NEXT: bnez a2, .LBB8_3 ; RV64-NEXT: bnez a2, .LBB8_3
; RV64-NEXT: j .LBB8_4 ; RV64-NEXT: j .LBB8_4
; RV64-NEXT: .LBB8_2: ; RV64-NEXT: .LBB8_2:
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; RV64-NEXT: vmv.v.i v8, 0 ; RV64-NEXT: vmv.v.i v8, 0
▲ Show 20 Lines • Show All 119 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll

Show First 20 Lines • Show All 415 Lines • ▼ Show 20 Lines
; CHECK-NEXT: addi a4, a2, -32 ; CHECK-NEXT: addi a4, a2, -32
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: li a3, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: bltu a2, a4, .LBB32_2 ; CHECK-NEXT: bltu a2, a4, .LBB32_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a5, a4 ; CHECK-NEXT: mv a5, a4
; CHECK-NEXT: .LBB32_2: ; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: li a6, 16 ; CHECK-NEXT: li a4, 16
; CHECK-NEXT: bltu a5, a6, .LBB32_4 ; CHECK-NEXT: bltu a5, a4, .LBB32_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: li a5, 16 ; CHECK-NEXT: li a5, 16
; CHECK-NEXT: .LBB32_4: ; CHECK-NEXT: .LBB32_4:
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v0, v8, 4 ; CHECK-NEXT: vslidedown.vi v0, v8, 4
; CHECK-NEXT: addi a4, a1, 256 ; CHECK-NEXT: addi a6, a1, 256
; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v16, (a4), v0.t ; CHECK-NEXT: vle64.v v16, (a6), v0.t
; CHECK-NEXT: li a4, 32 ; CHECK-NEXT: li a5, 32
; CHECK-NEXT: bltu a2, a4, .LBB32_6 ; CHECK-NEXT: bltu a2, a5, .LBB32_6
; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: li a2, 32 ; CHECK-NEXT: li a2, 32
; CHECK-NEXT: .LBB32_6: ; CHECK-NEXT: .LBB32_6:
; CHECK-NEXT: addi a5, a2, -16 ; CHECK-NEXT: addi a5, a2, -16
; CHECK-NEXT: bltu a2, a5, .LBB32_8 ; CHECK-NEXT: bltu a2, a5, .LBB32_8
; CHECK-NEXT: # %bb.7: ; CHECK-NEXT: # %bb.7:
; CHECK-NEXT: mv a3, a5 ; CHECK-NEXT: mv a3, a5
; CHECK-NEXT: .LBB32_8: ; CHECK-NEXT: .LBB32_8:
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vi v0, v8, 2 ; CHECK-NEXT: vslidedown.vi v0, v8, 2
; CHECK-NEXT: addi a4, a1, 128 ; CHECK-NEXT: addi a5, a1, 128
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v24, (a4), v0.t ; CHECK-NEXT: vle64.v v24, (a5), v0.t
; CHECK-NEXT: bltu a2, a6, .LBB32_10 ; CHECK-NEXT: bltu a2, a4, .LBB32_10
; CHECK-NEXT: # %bb.9: ; CHECK-NEXT: # %bb.9:
; CHECK-NEXT: li a2, 16 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: .LBB32_10: ; CHECK-NEXT: .LBB32_10:
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vle64.v v8, (a1), v0.t ; CHECK-NEXT: vle64.v v8, (a1), v0.t
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vse64.v v8, (a0) ; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: addi a1, a0, 128 ; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vse64.v v24, (a1) ; CHECK-NEXT: vse64.v v24, (a1)
; CHECK-NEXT: vfmv.f.s ft0, v16 ; CHECK-NEXT: vfmv.f.s ft0, v16
; CHECK-NEXT: fsd ft0, 256(a0) ; CHECK-NEXT: fsd ft0, 256(a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%load = call <33 x double> @llvm.vp.load.v33f64.p0v33f64(<33 x double>* %ptr, <33 x i1> %m, i32 %evl) %load = call <33 x double> @llvm.vp.load.v33f64.p0v33f64(<33 x double>* %ptr, <33 x i1> %m, i32 %evl)
ret <33 x double> %load ret <33 x double> %load
} }

llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll

Show All 21 Lines
; CHECK-NEXT: lw t0, 44(s1) ; CHECK-NEXT: lw t0, 44(s1)
; CHECK-NEXT: lw a2, 40(s1) ; CHECK-NEXT: lw a2, 40(s1)
; CHECK-NEXT: lw a3, 36(s1) ; CHECK-NEXT: lw a3, 36(s1)
; CHECK-NEXT: lw a4, 32(s1) ; CHECK-NEXT: lw a4, 32(s1)
; CHECK-NEXT: lw a5, 28(s1) ; CHECK-NEXT: lw a5, 28(s1)
; CHECK-NEXT: lw a6, 24(s1) ; CHECK-NEXT: lw a6, 24(s1)
; CHECK-NEXT: lw a7, 20(s1) ; CHECK-NEXT: lw a7, 20(s1)
; CHECK-NEXT: lw t1, 16(s1) ; CHECK-NEXT: lw t1, 16(s1)
; CHECK-NEXT: lw t2, 12(s1) ; CHECK-NEXT: lw a1, 12(s1)
; CHECK-NEXT: lw a1, 8(s1) ; CHECK-NEXT: lw t2, 8(s1)
; CHECK-NEXT: sw a0, 52(s1) ; CHECK-NEXT: sw a0, 52(s1)
; CHECK-NEXT: sw a0, 48(s1) ; CHECK-NEXT: sw a0, 48(s1)
; CHECK-NEXT: addi sp, sp, -32 ; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: sd a1, 16(sp) ; CHECK-NEXT: sd t2, 16(sp)
; CHECK-NEXT: sd t2, 8(sp) ; CHECK-NEXT: sd a1, 8(sp)
; CHECK-NEXT: addi a1, s1, 48 ; CHECK-NEXT: addi a1, s1, 48
; CHECK-NEXT: sd t1, 0(sp) ; CHECK-NEXT: sd t1, 0(sp)
; CHECK-NEXT: mv a0, t0 ; CHECK-NEXT: mv a0, t0
; CHECK-NEXT: call gfunc@plt ; CHECK-NEXT: call gfunc@plt
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: addi sp, s0, -80 ; CHECK-NEXT: addi sp, s0, -80
; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
Show All 39 Lines

llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 Lines
for.cond.cleanup: ; preds = %vector.body for.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
define void @sink_splat_mul_scalable(i32* nocapture %a, i32 signext %x) { define void @sink_splat_mul_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-LABEL: sink_splat_mul_scalable: ; CHECK-LABEL: sink_splat_mul_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: srli a7, a2, 1 ; CHECK-NEXT: srli a2, a6, 1
; CHECK-NEXT: li a3, 1024 ; CHECK-NEXT: li a3, 1024
; CHECK-NEXT: bgeu a3, a7, .LBB7_2 ; CHECK-NEXT: bgeu a3, a2, .LBB7_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li t0, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: j .LBB7_5 ; CHECK-NEXT: j .LBB7_5
; CHECK-NEXT: .LBB7_2: # %vector.ph ; CHECK-NEXT: .LBB7_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a3, a7 ; CHECK-NEXT: remu a4, a3, a2
; CHECK-NEXT: sub t0, a3, a6 ; CHECK-NEXT: sub a3, a3, a4
; CHECK-NEXT: slli a4, a2, 1 ; CHECK-NEXT: slli a6, a6, 1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a7, a0
; CHECK-NEXT: .LBB7_3: # %vector.body ; CHECK-NEXT: .LBB7_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vl2re32.v v8, (a7)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli t0, zero, e32, m2, ta, mu
; CHECK-NEXT: vmul.vx v8, v8, a1 ; CHECK-NEXT: vmul.vx v8, v8, a1
; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: vs2r.v v8, (a7)
; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: add a7, a7, a6
; CHECK-NEXT: bne a5, t0, .LBB7_3 ; CHECK-NEXT: bne a5, a3, .LBB7_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB7_7 ; CHECK-NEXT: beqz a4, .LBB7_7
; CHECK-NEXT: .LBB7_5: # %for.body.preheader ; CHECK-NEXT: .LBB7_5: # %for.body.preheader
; CHECK-NEXT: addi a2, t0, -1024 ; CHECK-NEXT: addi a2, a3, -1024
; CHECK-NEXT: slli a3, t0, 2 ; CHECK-NEXT: slli a3, a3, 2
; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB7_6: # %for.body ; CHECK-NEXT: .LBB7_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a3, 0(a0) ; CHECK-NEXT: lw a3, 0(a0)
; CHECK-NEXT: mv a4, a2 ; CHECK-NEXT: mv a4, a2
; CHECK-NEXT: mulw a2, a3, a1 ; CHECK-NEXT: mulw a2, a3, a1
; CHECK-NEXT: sw a2, 0(a0) ; CHECK-NEXT: sw a2, 0(a0)
; CHECK-NEXT: addi a2, a4, 1 ; CHECK-NEXT: addi a2, a4, 1
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_add_scalable(i32* nocapture %a, i32 signext %x) { define void @sink_splat_add_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-LABEL: sink_splat_add_scalable: ; CHECK-LABEL: sink_splat_add_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: srli a7, a2, 1 ; CHECK-NEXT: srli a2, a6, 1
; CHECK-NEXT: li a3, 1024 ; CHECK-NEXT: li a3, 1024
; CHECK-NEXT: bgeu a3, a7, .LBB8_2 ; CHECK-NEXT: bgeu a3, a2, .LBB8_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li t0, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: j .LBB8_5 ; CHECK-NEXT: j .LBB8_5
; CHECK-NEXT: .LBB8_2: # %vector.ph ; CHECK-NEXT: .LBB8_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a3, a7 ; CHECK-NEXT: remu a4, a3, a2
; CHECK-NEXT: sub t0, a3, a6 ; CHECK-NEXT: sub a3, a3, a4
; CHECK-NEXT: slli a4, a2, 1 ; CHECK-NEXT: slli a6, a6, 1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a7, a0
; CHECK-NEXT: .LBB8_3: # %vector.body ; CHECK-NEXT: .LBB8_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vl2re32.v v8, (a7)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli t0, zero, e32, m2, ta, mu
; CHECK-NEXT: vadd.vx v8, v8, a1 ; CHECK-NEXT: vadd.vx v8, v8, a1
; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: vs2r.v v8, (a7)
; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: add a7, a7, a6
; CHECK-NEXT: bne a5, t0, .LBB8_3 ; CHECK-NEXT: bne a5, a3, .LBB8_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB8_7 ; CHECK-NEXT: beqz a4, .LBB8_7
; CHECK-NEXT: .LBB8_5: # %for.body.preheader ; CHECK-NEXT: .LBB8_5: # %for.body.preheader
; CHECK-NEXT: addi a2, t0, -1024 ; CHECK-NEXT: addi a2, a3, -1024
; CHECK-NEXT: slli a3, t0, 2 ; CHECK-NEXT: slli a3, a3, 2
; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB8_6: # %for.body ; CHECK-NEXT: .LBB8_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a3, 0(a0) ; CHECK-NEXT: lw a3, 0(a0)
; CHECK-NEXT: mv a4, a2 ; CHECK-NEXT: mv a4, a2
; CHECK-NEXT: addw a2, a3, a1 ; CHECK-NEXT: addw a2, a3, a1
; CHECK-NEXT: sw a2, 0(a0) ; CHECK-NEXT: sw a2, 0(a0)
; CHECK-NEXT: addi a2, a4, 1 ; CHECK-NEXT: addi a2, a4, 1
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_sub_scalable(i32* nocapture %a, i32 signext %x) { define void @sink_splat_sub_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-LABEL: sink_splat_sub_scalable: ; CHECK-LABEL: sink_splat_sub_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: srli a7, a2, 1 ; CHECK-NEXT: srli a2, a6, 1
; CHECK-NEXT: li a3, 1024 ; CHECK-NEXT: li a3, 1024
; CHECK-NEXT: bgeu a3, a7, .LBB9_2 ; CHECK-NEXT: bgeu a3, a2, .LBB9_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li t0, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: j .LBB9_5 ; CHECK-NEXT: j .LBB9_5
; CHECK-NEXT: .LBB9_2: # %vector.ph ; CHECK-NEXT: .LBB9_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a3, a7 ; CHECK-NEXT: remu a4, a3, a2
; CHECK-NEXT: sub t0, a3, a6 ; CHECK-NEXT: sub a3, a3, a4
; CHECK-NEXT: slli a4, a2, 1 ; CHECK-NEXT: slli a6, a6, 1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a7, a0
; CHECK-NEXT: .LBB9_3: # %vector.body ; CHECK-NEXT: .LBB9_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vl2re32.v v8, (a7)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli t0, zero, e32, m2, ta, mu
; CHECK-NEXT: vsub.vx v8, v8, a1 ; CHECK-NEXT: vsub.vx v8, v8, a1
; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: vs2r.v v8, (a7)
; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: add a7, a7, a6
; CHECK-NEXT: bne a5, t0, .LBB9_3 ; CHECK-NEXT: bne a5, a3, .LBB9_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB9_7 ; CHECK-NEXT: beqz a4, .LBB9_7
; CHECK-NEXT: .LBB9_5: # %for.body.preheader ; CHECK-NEXT: .LBB9_5: # %for.body.preheader
; CHECK-NEXT: addi a2, t0, -1024 ; CHECK-NEXT: addi a2, a3, -1024
; CHECK-NEXT: slli a3, t0, 2 ; CHECK-NEXT: slli a3, a3, 2
; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB9_6: # %for.body ; CHECK-NEXT: .LBB9_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a3, 0(a0) ; CHECK-NEXT: lw a3, 0(a0)
; CHECK-NEXT: mv a4, a2 ; CHECK-NEXT: mv a4, a2
; CHECK-NEXT: addw a2, a3, a1 ; CHECK-NEXT: addw a2, a3, a1
; CHECK-NEXT: sw a2, 0(a0) ; CHECK-NEXT: sw a2, 0(a0)
; CHECK-NEXT: addi a2, a4, 1 ; CHECK-NEXT: addi a2, a4, 1
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_rsub_scalable(i32* nocapture %a, i32 signext %x) { define void @sink_splat_rsub_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-LABEL: sink_splat_rsub_scalable: ; CHECK-LABEL: sink_splat_rsub_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: srli a7, a2, 1 ; CHECK-NEXT: srli a2, a6, 1
; CHECK-NEXT: li a3, 1024 ; CHECK-NEXT: li a3, 1024
; CHECK-NEXT: bgeu a3, a7, .LBB10_2 ; CHECK-NEXT: bgeu a3, a2, .LBB10_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li t0, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: j .LBB10_5 ; CHECK-NEXT: j .LBB10_5
; CHECK-NEXT: .LBB10_2: # %vector.ph ; CHECK-NEXT: .LBB10_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a3, a7 ; CHECK-NEXT: remu a4, a3, a2
; CHECK-NEXT: sub t0, a3, a6 ; CHECK-NEXT: sub a3, a3, a4
; CHECK-NEXT: slli a4, a2, 1 ; CHECK-NEXT: slli a6, a6, 1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a7, a0
; CHECK-NEXT: .LBB10_3: # %vector.body ; CHECK-NEXT: .LBB10_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vl2re32.v v8, (a7)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli t0, zero, e32, m2, ta, mu
; CHECK-NEXT: vrsub.vx v8, v8, a1 ; CHECK-NEXT: vrsub.vx v8, v8, a1
; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: vs2r.v v8, (a7)
; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: add a7, a7, a6
; CHECK-NEXT: bne a5, t0, .LBB10_3 ; CHECK-NEXT: bne a5, a3, .LBB10_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB10_7 ; CHECK-NEXT: beqz a4, .LBB10_7
; CHECK-NEXT: .LBB10_5: # %for.body.preheader ; CHECK-NEXT: .LBB10_5: # %for.body.preheader
; CHECK-NEXT: addi a2, t0, -1024 ; CHECK-NEXT: addi a2, a3, -1024
; CHECK-NEXT: slli a3, t0, 2 ; CHECK-NEXT: slli a3, a3, 2
; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB10_6: # %for.body ; CHECK-NEXT: .LBB10_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a3, 0(a0) ; CHECK-NEXT: lw a3, 0(a0)
; CHECK-NEXT: mv a4, a2 ; CHECK-NEXT: mv a4, a2
; CHECK-NEXT: subw a2, a1, a3 ; CHECK-NEXT: subw a2, a1, a3
; CHECK-NEXT: sw a2, 0(a0) ; CHECK-NEXT: sw a2, 0(a0)
; CHECK-NEXT: addi a2, a4, 1 ; CHECK-NEXT: addi a2, a4, 1
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_and_scalable(i32* nocapture %a, i32 signext %x) { define void @sink_splat_and_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-LABEL: sink_splat_and_scalable: ; CHECK-LABEL: sink_splat_and_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: srli a7, a2, 1 ; CHECK-NEXT: srli a2, a6, 1
; CHECK-NEXT: li a3, 1024 ; CHECK-NEXT: li a3, 1024
; CHECK-NEXT: bgeu a3, a7, .LBB11_2 ; CHECK-NEXT: bgeu a3, a2, .LBB11_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li t0, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: j .LBB11_5 ; CHECK-NEXT: j .LBB11_5
; CHECK-NEXT: .LBB11_2: # %vector.ph ; CHECK-NEXT: .LBB11_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a3, a7 ; CHECK-NEXT: remu a4, a3, a2
; CHECK-NEXT: sub t0, a3, a6 ; CHECK-NEXT: sub a3, a3, a4
; CHECK-NEXT: slli a4, a2, 1 ; CHECK-NEXT: slli a6, a6, 1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a7, a0
; CHECK-NEXT: .LBB11_3: # %vector.body ; CHECK-NEXT: .LBB11_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vl2re32.v v8, (a7)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli t0, zero, e32, m2, ta, mu
; CHECK-NEXT: vand.vx v8, v8, a1 ; CHECK-NEXT: vand.vx v8, v8, a1
; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: vs2r.v v8, (a7)
; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: add a7, a7, a6
; CHECK-NEXT: bne a5, t0, .LBB11_3 ; CHECK-NEXT: bne a5, a3, .LBB11_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB11_7 ; CHECK-NEXT: beqz a4, .LBB11_7
; CHECK-NEXT: .LBB11_5: # %for.body.preheader ; CHECK-NEXT: .LBB11_5: # %for.body.preheader
; CHECK-NEXT: addi a2, t0, -1024 ; CHECK-NEXT: addi a2, a3, -1024
; CHECK-NEXT: slli a3, t0, 2 ; CHECK-NEXT: slli a3, a3, 2
; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB11_6: # %for.body ; CHECK-NEXT: .LBB11_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a3, 0(a0) ; CHECK-NEXT: lw a3, 0(a0)
; CHECK-NEXT: mv a4, a2 ; CHECK-NEXT: mv a4, a2
; CHECK-NEXT: and a2, a3, a1 ; CHECK-NEXT: and a2, a3, a1
; CHECK-NEXT: sw a2, 0(a0) ; CHECK-NEXT: sw a2, 0(a0)
; CHECK-NEXT: addi a2, a4, 1 ; CHECK-NEXT: addi a2, a4, 1
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_or_scalable(i32* nocapture %a, i32 signext %x) { define void @sink_splat_or_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-LABEL: sink_splat_or_scalable: ; CHECK-LABEL: sink_splat_or_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: srli a7, a2, 1 ; CHECK-NEXT: srli a2, a6, 1
; CHECK-NEXT: li a3, 1024 ; CHECK-NEXT: li a3, 1024
; CHECK-NEXT: bgeu a3, a7, .LBB12_2 ; CHECK-NEXT: bgeu a3, a2, .LBB12_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li t0, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: j .LBB12_5 ; CHECK-NEXT: j .LBB12_5
; CHECK-NEXT: .LBB12_2: # %vector.ph ; CHECK-NEXT: .LBB12_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a3, a7 ; CHECK-NEXT: remu a4, a3, a2
; CHECK-NEXT: sub t0, a3, a6 ; CHECK-NEXT: sub a3, a3, a4
; CHECK-NEXT: slli a4, a2, 1 ; CHECK-NEXT: slli a6, a6, 1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a7, a0
; CHECK-NEXT: .LBB12_3: # %vector.body ; CHECK-NEXT: .LBB12_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vl2re32.v v8, (a7)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli t0, zero, e32, m2, ta, mu
; CHECK-NEXT: vor.vx v8, v8, a1 ; CHECK-NEXT: vor.vx v8, v8, a1
; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: vs2r.v v8, (a7)
; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: add a7, a7, a6
; CHECK-NEXT: bne a5, t0, .LBB12_3 ; CHECK-NEXT: bne a5, a3, .LBB12_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB12_7 ; CHECK-NEXT: beqz a4, .LBB12_7
; CHECK-NEXT: .LBB12_5: # %for.body.preheader ; CHECK-NEXT: .LBB12_5: # %for.body.preheader
; CHECK-NEXT: addi a2, t0, -1024 ; CHECK-NEXT: addi a2, a3, -1024
; CHECK-NEXT: slli a3, t0, 2 ; CHECK-NEXT: slli a3, a3, 2
; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB12_6: # %for.body ; CHECK-NEXT: .LBB12_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a3, 0(a0) ; CHECK-NEXT: lw a3, 0(a0)
; CHECK-NEXT: mv a4, a2 ; CHECK-NEXT: mv a4, a2
; CHECK-NEXT: or a2, a3, a1 ; CHECK-NEXT: or a2, a3, a1
; CHECK-NEXT: sw a2, 0(a0) ; CHECK-NEXT: sw a2, 0(a0)
; CHECK-NEXT: addi a2, a4, 1 ; CHECK-NEXT: addi a2, a4, 1
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_xor_scalable(i32* nocapture %a, i32 signext %x) { define void @sink_splat_xor_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-LABEL: sink_splat_xor_scalable: ; CHECK-LABEL: sink_splat_xor_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: srli a7, a2, 1 ; CHECK-NEXT: srli a2, a6, 1
; CHECK-NEXT: li a3, 1024 ; CHECK-NEXT: li a3, 1024
; CHECK-NEXT: bgeu a3, a7, .LBB13_2 ; CHECK-NEXT: bgeu a3, a2, .LBB13_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li t0, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: j .LBB13_5 ; CHECK-NEXT: j .LBB13_5
; CHECK-NEXT: .LBB13_2: # %vector.ph ; CHECK-NEXT: .LBB13_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a3, a7 ; CHECK-NEXT: remu a4, a3, a2
; CHECK-NEXT: sub t0, a3, a6 ; CHECK-NEXT: sub a3, a3, a4
; CHECK-NEXT: slli a4, a2, 1 ; CHECK-NEXT: slli a6, a6, 1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a7, a0
; CHECK-NEXT: .LBB13_3: # %vector.body ; CHECK-NEXT: .LBB13_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vl2re32.v v8, (a7)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli t0, zero, e32, m2, ta, mu
; CHECK-NEXT: vxor.vx v8, v8, a1 ; CHECK-NEXT: vxor.vx v8, v8, a1
; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: vs2r.v v8, (a7)
; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: add a7, a7, a6
; CHECK-NEXT: bne a5, t0, .LBB13_3 ; CHECK-NEXT: bne a5, a3, .LBB13_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB13_7 ; CHECK-NEXT: beqz a4, .LBB13_7
; CHECK-NEXT: .LBB13_5: # %for.body.preheader ; CHECK-NEXT: .LBB13_5: # %for.body.preheader
; CHECK-NEXT: addi a2, t0, -1024 ; CHECK-NEXT: addi a2, a3, -1024
; CHECK-NEXT: slli a3, t0, 2 ; CHECK-NEXT: slli a3, a3, 2
; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB13_6: # %for.body ; CHECK-NEXT: .LBB13_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a3, 0(a0) ; CHECK-NEXT: lw a3, 0(a0)
; CHECK-NEXT: mv a4, a2 ; CHECK-NEXT: mv a4, a2
; CHECK-NEXT: xor a2, a3, a1 ; CHECK-NEXT: xor a2, a3, a1
; CHECK-NEXT: sw a2, 0(a0) ; CHECK-NEXT: sw a2, 0(a0)
; CHECK-NEXT: addi a2, a4, 1 ; CHECK-NEXT: addi a2, a4, 1
▲ Show 20 Lines • Show All 158 Lines • ▼ Show 20 Lines
for.cond.cleanup: ; preds = %vector.body for.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
define void @sink_splat_shl_scalable(i32* nocapture %a, i32 signext %x) { define void @sink_splat_shl_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-LABEL: sink_splat_shl_scalable: ; CHECK-LABEL: sink_splat_shl_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: srli a7, a2, 1 ; CHECK-NEXT: srli a2, a6, 1
; CHECK-NEXT: li a3, 1024 ; CHECK-NEXT: li a3, 1024
; CHECK-NEXT: bgeu a3, a7, .LBB17_2 ; CHECK-NEXT: bgeu a3, a2, .LBB17_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li t0, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: j .LBB17_5 ; CHECK-NEXT: j .LBB17_5
; CHECK-NEXT: .LBB17_2: # %vector.ph ; CHECK-NEXT: .LBB17_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a3, a7 ; CHECK-NEXT: remu a4, a3, a2
; CHECK-NEXT: sub t0, a3, a6 ; CHECK-NEXT: sub a3, a3, a4
; CHECK-NEXT: slli a4, a2, 1 ; CHECK-NEXT: slli a6, a6, 1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a7, a0
; CHECK-NEXT: .LBB17_3: # %vector.body ; CHECK-NEXT: .LBB17_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vl2re32.v v8, (a7)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli t0, zero, e32, m2, ta, mu
; CHECK-NEXT: vsll.vx v8, v8, a1 ; CHECK-NEXT: vsll.vx v8, v8, a1
; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: vs2r.v v8, (a7)
; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: add a7, a7, a6
; CHECK-NEXT: bne a5, t0, .LBB17_3 ; CHECK-NEXT: bne a5, a3, .LBB17_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB17_7 ; CHECK-NEXT: beqz a4, .LBB17_7
; CHECK-NEXT: .LBB17_5: # %for.body.preheader ; CHECK-NEXT: .LBB17_5: # %for.body.preheader
; CHECK-NEXT: addi a2, t0, -1024 ; CHECK-NEXT: addi a2, a3, -1024
; CHECK-NEXT: slli a3, t0, 2 ; CHECK-NEXT: slli a3, a3, 2
; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB17_6: # %for.body ; CHECK-NEXT: .LBB17_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a3, 0(a0) ; CHECK-NEXT: lw a3, 0(a0)
; CHECK-NEXT: mv a4, a2 ; CHECK-NEXT: mv a4, a2
; CHECK-NEXT: sllw a2, a3, a1 ; CHECK-NEXT: sllw a2, a3, a1
; CHECK-NEXT: sw a2, 0(a0) ; CHECK-NEXT: sw a2, 0(a0)
; CHECK-NEXT: addi a2, a4, 1 ; CHECK-NEXT: addi a2, a4, 1
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_lshr_scalable(i32* nocapture %a, i32 signext %x) { define void @sink_splat_lshr_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-LABEL: sink_splat_lshr_scalable: ; CHECK-LABEL: sink_splat_lshr_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: srli a7, a2, 1 ; CHECK-NEXT: srli a2, a6, 1
; CHECK-NEXT: li a3, 1024 ; CHECK-NEXT: li a3, 1024
; CHECK-NEXT: bgeu a3, a7, .LBB18_2 ; CHECK-NEXT: bgeu a3, a2, .LBB18_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li t0, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: j .LBB18_5 ; CHECK-NEXT: j .LBB18_5
; CHECK-NEXT: .LBB18_2: # %vector.ph ; CHECK-NEXT: .LBB18_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a3, a7 ; CHECK-NEXT: remu a4, a3, a2
; CHECK-NEXT: sub t0, a3, a6 ; CHECK-NEXT: sub a3, a3, a4
; CHECK-NEXT: slli a4, a2, 1 ; CHECK-NEXT: slli a6, a6, 1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a7, a0
; CHECK-NEXT: .LBB18_3: # %vector.body ; CHECK-NEXT: .LBB18_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vl2re32.v v8, (a7)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli t0, zero, e32, m2, ta, mu
; CHECK-NEXT: vsrl.vx v8, v8, a1 ; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: vs2r.v v8, (a7)
; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: add a7, a7, a6
; CHECK-NEXT: bne a5, t0, .LBB18_3 ; CHECK-NEXT: bne a5, a3, .LBB18_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB18_7 ; CHECK-NEXT: beqz a4, .LBB18_7
; CHECK-NEXT: .LBB18_5: # %for.body.preheader ; CHECK-NEXT: .LBB18_5: # %for.body.preheader
; CHECK-NEXT: addi a2, t0, -1024 ; CHECK-NEXT: addi a2, a3, -1024
; CHECK-NEXT: slli a3, t0, 2 ; CHECK-NEXT: slli a3, a3, 2
; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB18_6: # %for.body ; CHECK-NEXT: .LBB18_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a3, 0(a0) ; CHECK-NEXT: lw a3, 0(a0)
; CHECK-NEXT: mv a4, a2 ; CHECK-NEXT: mv a4, a2
; CHECK-NEXT: srlw a2, a3, a1 ; CHECK-NEXT: srlw a2, a3, a1
; CHECK-NEXT: sw a2, 0(a0) ; CHECK-NEXT: sw a2, 0(a0)
; CHECK-NEXT: addi a2, a4, 1 ; CHECK-NEXT: addi a2, a4, 1
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_ashr_scalable(i32* nocapture %a) { define void @sink_splat_ashr_scalable(i32* nocapture %a) {
; CHECK-LABEL: sink_splat_ashr_scalable: ; CHECK-LABEL: sink_splat_ashr_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: srli a7, a3, 1 ; CHECK-NEXT: srli a1, a5, 1
; CHECK-NEXT: li a2, 1024 ; CHECK-NEXT: li a2, 1024
; CHECK-NEXT: bgeu a2, a7, .LBB19_2 ; CHECK-NEXT: bgeu a2, a1, .LBB19_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 0 ; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB19_5 ; CHECK-NEXT: j .LBB19_5
; CHECK-NEXT: .LBB19_2: # %vector.ph ; CHECK-NEXT: .LBB19_2: # %vector.ph
; CHECK-NEXT: li a4, 0 ; CHECK-NEXT: li a4, 0
; CHECK-NEXT: remu a6, a2, a7 ; CHECK-NEXT: remu a3, a2, a1
; CHECK-NEXT: sub a2, a2, a6 ; CHECK-NEXT: sub a2, a2, a3
; CHECK-NEXT: slli a5, a3, 1 ; CHECK-NEXT: slli a5, a5, 1
; CHECK-NEXT: mv a3, a0 ; CHECK-NEXT: mv a6, a0
; CHECK-NEXT: .LBB19_3: # %vector.body ; CHECK-NEXT: .LBB19_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl2re32.v v8, (a3) ; CHECK-NEXT: vl2re32.v v8, (a6)
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a7, zero, e32, m2, ta, mu
; CHECK-NEXT: vsra.vi v8, v8, 2 ; CHECK-NEXT: vsra.vi v8, v8, 2
; CHECK-NEXT: vs2r.v v8, (a3) ; CHECK-NEXT: vs2r.v v8, (a6)
; CHECK-NEXT: add a4, a4, a7 ; CHECK-NEXT: add a4, a4, a1
; CHECK-NEXT: add a3, a3, a5 ; CHECK-NEXT: add a6, a6, a5
; CHECK-NEXT: bne a4, a2, .LBB19_3 ; CHECK-NEXT: bne a4, a2, .LBB19_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB19_7 ; CHECK-NEXT: beqz a3, .LBB19_7
; CHECK-NEXT: .LBB19_5: # %for.body.preheader ; CHECK-NEXT: .LBB19_5: # %for.body.preheader
; CHECK-NEXT: addi a1, a2, -1024 ; CHECK-NEXT: addi a1, a2, -1024
; CHECK-NEXT: slli a2, a2, 2 ; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a0, a0, a2 ; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: .LBB19_6: # %for.body ; CHECK-NEXT: .LBB19_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a2, 0(a0) ; CHECK-NEXT: lw a2, 0(a0)
; CHECK-NEXT: mv a3, a1 ; CHECK-NEXT: mv a3, a1
▲ Show 20 Lines • Show All 275 Lines • ▼ Show 20 Lines
for.cond.cleanup: ; preds = %vector.body for.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
define void @sink_splat_fmul_scalable(float* nocapture %a, float %x) { define void @sink_splat_fmul_scalable(float* nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_fmul_scalable: ; CHECK-LABEL: sink_splat_fmul_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a7, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: srli a3, a7, 2 ; CHECK-NEXT: srli a3, a2, 2
; CHECK-NEXT: li a4, 1024 ; CHECK-NEXT: li a6, 1024
; CHECK-NEXT: fmv.w.x ft0, a1 ; CHECK-NEXT: fmv.w.x ft0, a1
; CHECK-NEXT: bgeu a4, a3, .LBB26_2 ; CHECK-NEXT: bgeu a6, a3, .LBB26_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB26_5 ; CHECK-NEXT: j .LBB26_5
; CHECK-NEXT: .LBB26_2: # %vector.ph ; CHECK-NEXT: .LBB26_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a4, a3 ; CHECK-NEXT: remu a4, a6, a3
; CHECK-NEXT: sub a1, a4, a6 ; CHECK-NEXT: sub a1, a6, a4
; CHECK-NEXT: mv a4, a0 ; CHECK-NEXT: mv a6, a0
; CHECK-NEXT: .LBB26_3: # %vector.body ; CHECK-NEXT: .LBB26_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl1re32.v v8, (a4) ; CHECK-NEXT: vl1re32.v v8, (a6)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmul.vf v8, v8, ft0 ; CHECK-NEXT: vfmul.vf v8, v8, ft0
; CHECK-NEXT: vs1r.v v8, (a4) ; CHECK-NEXT: vs1r.v v8, (a6)
; CHECK-NEXT: add a5, a5, a3 ; CHECK-NEXT: add a5, a5, a3
; CHECK-NEXT: add a4, a4, a7 ; CHECK-NEXT: add a6, a6, a2
; CHECK-NEXT: bne a5, a1, .LBB26_3 ; CHECK-NEXT: bne a5, a1, .LBB26_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB26_7 ; CHECK-NEXT: beqz a4, .LBB26_7
; CHECK-NEXT: .LBB26_5: # %for.body.preheader ; CHECK-NEXT: .LBB26_5: # %for.body.preheader
; CHECK-NEXT: addi a2, a1, -1024 ; CHECK-NEXT: addi a2, a1, -1024
; CHECK-NEXT: slli a1, a1, 2 ; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: .LBB26_6: # %for.body ; CHECK-NEXT: .LBB26_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft1, 0(a0) ; CHECK-NEXT: flw ft1, 0(a0)
; CHECK-NEXT: mv a1, a2 ; CHECK-NEXT: mv a1, a2
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_fdiv_scalable(float* nocapture %a, float %x) { define void @sink_splat_fdiv_scalable(float* nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_fdiv_scalable: ; CHECK-LABEL: sink_splat_fdiv_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a7, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: srli a3, a7, 2 ; CHECK-NEXT: srli a3, a2, 2
; CHECK-NEXT: li a4, 1024 ; CHECK-NEXT: li a6, 1024
; CHECK-NEXT: fmv.w.x ft0, a1 ; CHECK-NEXT: fmv.w.x ft0, a1
; CHECK-NEXT: bgeu a4, a3, .LBB27_2 ; CHECK-NEXT: bgeu a6, a3, .LBB27_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB27_5 ; CHECK-NEXT: j .LBB27_5
; CHECK-NEXT: .LBB27_2: # %vector.ph ; CHECK-NEXT: .LBB27_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a4, a3 ; CHECK-NEXT: remu a4, a6, a3
; CHECK-NEXT: sub a1, a4, a6 ; CHECK-NEXT: sub a1, a6, a4
; CHECK-NEXT: mv a4, a0 ; CHECK-NEXT: mv a6, a0
; CHECK-NEXT: .LBB27_3: # %vector.body ; CHECK-NEXT: .LBB27_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl1re32.v v8, (a4) ; CHECK-NEXT: vl1re32.v v8, (a6)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, mu
; CHECK-NEXT: vfdiv.vf v8, v8, ft0 ; CHECK-NEXT: vfdiv.vf v8, v8, ft0
; CHECK-NEXT: vs1r.v v8, (a4) ; CHECK-NEXT: vs1r.v v8, (a6)
; CHECK-NEXT: add a5, a5, a3 ; CHECK-NEXT: add a5, a5, a3
; CHECK-NEXT: add a4, a4, a7 ; CHECK-NEXT: add a6, a6, a2
; CHECK-NEXT: bne a5, a1, .LBB27_3 ; CHECK-NEXT: bne a5, a1, .LBB27_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB27_7 ; CHECK-NEXT: beqz a4, .LBB27_7
; CHECK-NEXT: .LBB27_5: # %for.body.preheader ; CHECK-NEXT: .LBB27_5: # %for.body.preheader
; CHECK-NEXT: addi a2, a1, -1024 ; CHECK-NEXT: addi a2, a1, -1024
; CHECK-NEXT: slli a1, a1, 2 ; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: .LBB27_6: # %for.body ; CHECK-NEXT: .LBB27_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft1, 0(a0) ; CHECK-NEXT: flw ft1, 0(a0)
; CHECK-NEXT: mv a1, a2 ; CHECK-NEXT: mv a1, a2
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_frdiv_scalable(float* nocapture %a, float %x) { define void @sink_splat_frdiv_scalable(float* nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_frdiv_scalable: ; CHECK-LABEL: sink_splat_frdiv_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a7, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: srli a3, a7, 2 ; CHECK-NEXT: srli a3, a2, 2
; CHECK-NEXT: li a4, 1024 ; CHECK-NEXT: li a6, 1024
; CHECK-NEXT: fmv.w.x ft0, a1 ; CHECK-NEXT: fmv.w.x ft0, a1
; CHECK-NEXT: bgeu a4, a3, .LBB28_2 ; CHECK-NEXT: bgeu a6, a3, .LBB28_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB28_5 ; CHECK-NEXT: j .LBB28_5
; CHECK-NEXT: .LBB28_2: # %vector.ph ; CHECK-NEXT: .LBB28_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a4, a3 ; CHECK-NEXT: remu a4, a6, a3
; CHECK-NEXT: sub a1, a4, a6 ; CHECK-NEXT: sub a1, a6, a4
; CHECK-NEXT: mv a4, a0 ; CHECK-NEXT: mv a6, a0
; CHECK-NEXT: .LBB28_3: # %vector.body ; CHECK-NEXT: .LBB28_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl1re32.v v8, (a4) ; CHECK-NEXT: vl1re32.v v8, (a6)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, mu
; CHECK-NEXT: vfrdiv.vf v8, v8, ft0 ; CHECK-NEXT: vfrdiv.vf v8, v8, ft0
; CHECK-NEXT: vs1r.v v8, (a4) ; CHECK-NEXT: vs1r.v v8, (a6)
; CHECK-NEXT: add a5, a5, a3 ; CHECK-NEXT: add a5, a5, a3
; CHECK-NEXT: add a4, a4, a7 ; CHECK-NEXT: add a6, a6, a2
; CHECK-NEXT: bne a5, a1, .LBB28_3 ; CHECK-NEXT: bne a5, a1, .LBB28_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB28_7 ; CHECK-NEXT: beqz a4, .LBB28_7
; CHECK-NEXT: .LBB28_5: # %for.body.preheader ; CHECK-NEXT: .LBB28_5: # %for.body.preheader
; CHECK-NEXT: addi a2, a1, -1024 ; CHECK-NEXT: addi a2, a1, -1024
; CHECK-NEXT: slli a1, a1, 2 ; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: .LBB28_6: # %for.body ; CHECK-NEXT: .LBB28_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft1, 0(a0) ; CHECK-NEXT: flw ft1, 0(a0)
; CHECK-NEXT: mv a1, a2 ; CHECK-NEXT: mv a1, a2
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_fadd_scalable(float* nocapture %a, float %x) { define void @sink_splat_fadd_scalable(float* nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_fadd_scalable: ; CHECK-LABEL: sink_splat_fadd_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a7, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: srli a3, a7, 2 ; CHECK-NEXT: srli a3, a2, 2
; CHECK-NEXT: li a4, 1024 ; CHECK-NEXT: li a6, 1024
; CHECK-NEXT: fmv.w.x ft0, a1 ; CHECK-NEXT: fmv.w.x ft0, a1
; CHECK-NEXT: bgeu a4, a3, .LBB29_2 ; CHECK-NEXT: bgeu a6, a3, .LBB29_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB29_5 ; CHECK-NEXT: j .LBB29_5
; CHECK-NEXT: .LBB29_2: # %vector.ph ; CHECK-NEXT: .LBB29_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a4, a3 ; CHECK-NEXT: remu a4, a6, a3
; CHECK-NEXT: sub a1, a4, a6 ; CHECK-NEXT: sub a1, a6, a4
; CHECK-NEXT: mv a4, a0 ; CHECK-NEXT: mv a6, a0
; CHECK-NEXT: .LBB29_3: # %vector.body ; CHECK-NEXT: .LBB29_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl1re32.v v8, (a4) ; CHECK-NEXT: vl1re32.v v8, (a6)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, mu
; CHECK-NEXT: vfadd.vf v8, v8, ft0 ; CHECK-NEXT: vfadd.vf v8, v8, ft0
; CHECK-NEXT: vs1r.v v8, (a4) ; CHECK-NEXT: vs1r.v v8, (a6)
; CHECK-NEXT: add a5, a5, a3 ; CHECK-NEXT: add a5, a5, a3
; CHECK-NEXT: add a4, a4, a7 ; CHECK-NEXT: add a6, a6, a2
; CHECK-NEXT: bne a5, a1, .LBB29_3 ; CHECK-NEXT: bne a5, a1, .LBB29_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB29_7 ; CHECK-NEXT: beqz a4, .LBB29_7
; CHECK-NEXT: .LBB29_5: # %for.body.preheader ; CHECK-NEXT: .LBB29_5: # %for.body.preheader
; CHECK-NEXT: addi a2, a1, -1024 ; CHECK-NEXT: addi a2, a1, -1024
; CHECK-NEXT: slli a1, a1, 2 ; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: .LBB29_6: # %for.body ; CHECK-NEXT: .LBB29_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft1, 0(a0) ; CHECK-NEXT: flw ft1, 0(a0)
; CHECK-NEXT: mv a1, a2 ; CHECK-NEXT: mv a1, a2
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_fsub_scalable(float* nocapture %a, float %x) { define void @sink_splat_fsub_scalable(float* nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_fsub_scalable: ; CHECK-LABEL: sink_splat_fsub_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a7, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: srli a3, a7, 2 ; CHECK-NEXT: srli a3, a2, 2
; CHECK-NEXT: li a4, 1024 ; CHECK-NEXT: li a6, 1024
; CHECK-NEXT: fmv.w.x ft0, a1 ; CHECK-NEXT: fmv.w.x ft0, a1
; CHECK-NEXT: bgeu a4, a3, .LBB30_2 ; CHECK-NEXT: bgeu a6, a3, .LBB30_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB30_5 ; CHECK-NEXT: j .LBB30_5
; CHECK-NEXT: .LBB30_2: # %vector.ph ; CHECK-NEXT: .LBB30_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a4, a3 ; CHECK-NEXT: remu a4, a6, a3
; CHECK-NEXT: sub a1, a4, a6 ; CHECK-NEXT: sub a1, a6, a4
; CHECK-NEXT: mv a4, a0 ; CHECK-NEXT: mv a6, a0
; CHECK-NEXT: .LBB30_3: # %vector.body ; CHECK-NEXT: .LBB30_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl1re32.v v8, (a4) ; CHECK-NEXT: vl1re32.v v8, (a6)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, mu
; CHECK-NEXT: vfsub.vf v8, v8, ft0 ; CHECK-NEXT: vfsub.vf v8, v8, ft0
; CHECK-NEXT: vs1r.v v8, (a4) ; CHECK-NEXT: vs1r.v v8, (a6)
; CHECK-NEXT: add a5, a5, a3 ; CHECK-NEXT: add a5, a5, a3
; CHECK-NEXT: add a4, a4, a7 ; CHECK-NEXT: add a6, a6, a2
; CHECK-NEXT: bne a5, a1, .LBB30_3 ; CHECK-NEXT: bne a5, a1, .LBB30_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB30_7 ; CHECK-NEXT: beqz a4, .LBB30_7
; CHECK-NEXT: .LBB30_5: # %for.body.preheader ; CHECK-NEXT: .LBB30_5: # %for.body.preheader
; CHECK-NEXT: addi a2, a1, -1024 ; CHECK-NEXT: addi a2, a1, -1024
; CHECK-NEXT: slli a1, a1, 2 ; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: .LBB30_6: # %for.body ; CHECK-NEXT: .LBB30_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft1, 0(a0) ; CHECK-NEXT: flw ft1, 0(a0)
; CHECK-NEXT: mv a1, a2 ; CHECK-NEXT: mv a1, a2
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_frsub_scalable(float* nocapture %a, float %x) { define void @sink_splat_frsub_scalable(float* nocapture %a, float %x) {
; CHECK-LABEL: sink_splat_frsub_scalable: ; CHECK-LABEL: sink_splat_frsub_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a7, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: srli a3, a7, 2 ; CHECK-NEXT: srli a3, a2, 2
; CHECK-NEXT: li a4, 1024 ; CHECK-NEXT: li a6, 1024
; CHECK-NEXT: fmv.w.x ft0, a1 ; CHECK-NEXT: fmv.w.x ft0, a1
; CHECK-NEXT: bgeu a4, a3, .LBB31_2 ; CHECK-NEXT: bgeu a6, a3, .LBB31_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: j .LBB31_5 ; CHECK-NEXT: j .LBB31_5
; CHECK-NEXT: .LBB31_2: # %vector.ph ; CHECK-NEXT: .LBB31_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a4, a3 ; CHECK-NEXT: remu a4, a6, a3
; CHECK-NEXT: sub a1, a4, a6 ; CHECK-NEXT: sub a1, a6, a4
; CHECK-NEXT: mv a4, a0 ; CHECK-NEXT: mv a6, a0
; CHECK-NEXT: .LBB31_3: # %vector.body ; CHECK-NEXT: .LBB31_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl1re32.v v8, (a4) ; CHECK-NEXT: vl1re32.v v8, (a6)
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a7, zero, e32, m1, ta, mu
; CHECK-NEXT: vfrsub.vf v8, v8, ft0 ; CHECK-NEXT: vfrsub.vf v8, v8, ft0
; CHECK-NEXT: vs1r.v v8, (a4) ; CHECK-NEXT: vs1r.v v8, (a6)
; CHECK-NEXT: add a5, a5, a3 ; CHECK-NEXT: add a5, a5, a3
; CHECK-NEXT: add a4, a4, a7 ; CHECK-NEXT: add a6, a6, a2
; CHECK-NEXT: bne a5, a1, .LBB31_3 ; CHECK-NEXT: bne a5, a1, .LBB31_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB31_7 ; CHECK-NEXT: beqz a4, .LBB31_7
; CHECK-NEXT: .LBB31_5: # %for.body.preheader ; CHECK-NEXT: .LBB31_5: # %for.body.preheader
; CHECK-NEXT: addi a2, a1, -1024 ; CHECK-NEXT: addi a2, a1, -1024
; CHECK-NEXT: slli a1, a1, 2 ; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: .LBB31_6: # %for.body ; CHECK-NEXT: .LBB31_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft1, 0(a0) ; CHECK-NEXT: flw ft1, 0(a0)
; CHECK-NEXT: mv a1, a2 ; CHECK-NEXT: mv a1, a2
▲ Show 20 Lines • Show All 137 Lines • ▼ Show 20 Lines
for.cond.cleanup: ; preds = %vector.body for.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
define void @sink_splat_fma_scalable(float* noalias nocapture %a, float* noalias nocapture readonly %b, float %x) { define void @sink_splat_fma_scalable(float* noalias nocapture %a, float* noalias nocapture readonly %b, float %x) {
; CHECK-LABEL: sink_splat_fma_scalable: ; CHECK-LABEL: sink_splat_fma_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a7, vlenb ; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: srli t1, a7, 2 ; CHECK-NEXT: srli a4, a3, 2
; CHECK-NEXT: li t0, 1024 ; CHECK-NEXT: li t0, 1024
; CHECK-NEXT: fmv.w.x ft0, a2 ; CHECK-NEXT: fmv.w.x ft0, a2
; CHECK-NEXT: bgeu t0, t1, .LBB34_2 ; CHECK-NEXT: bgeu t0, a4, .LBB34_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li t0, 0 ; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB34_5 ; CHECK-NEXT: j .LBB34_5
; CHECK-NEXT: .LBB34_2: # %vector.ph ; CHECK-NEXT: .LBB34_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a6, 0
; CHECK-NEXT: li a3, 0 ; CHECK-NEXT: li a7, 0
; CHECK-NEXT: remu a6, t0, t1 ; CHECK-NEXT: remu a5, t0, a4
; CHECK-NEXT: sub t0, t0, a6 ; CHECK-NEXT: sub a2, t0, a5
; CHECK-NEXT: .LBB34_3: # %vector.body ; CHECK-NEXT: .LBB34_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add a2, a0, a5 ; CHECK-NEXT: add t0, a0, a6
; CHECK-NEXT: vl1re32.v v8, (a2) ; CHECK-NEXT: vl1re32.v v8, (t0)
; CHECK-NEXT: add a4, a1, a5 ; CHECK-NEXT: add t1, a1, a6
; CHECK-NEXT: vl1re32.v v9, (a4) ; CHECK-NEXT: vl1re32.v v9, (t1)
; CHECK-NEXT: vsetvli a4, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli t1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmacc.vf v9, ft0, v8 ; CHECK-NEXT: vfmacc.vf v9, ft0, v8
; CHECK-NEXT: vs1r.v v9, (a2) ; CHECK-NEXT: vs1r.v v9, (t0)
; CHECK-NEXT: add a3, a3, t1 ; CHECK-NEXT: add a7, a7, a4
; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a6, a6, a3
; CHECK-NEXT: bne a3, t0, .LBB34_3 ; CHECK-NEXT: bne a7, a2, .LBB34_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB34_7 ; CHECK-NEXT: beqz a5, .LBB34_7
; CHECK-NEXT: .LBB34_5: # %for.body.preheader ; CHECK-NEXT: .LBB34_5: # %for.body.preheader
; CHECK-NEXT: addi a3, t0, -1024 ; CHECK-NEXT: addi a3, a2, -1024
; CHECK-NEXT: slli a2, t0, 2 ; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a1, a1, a2 ; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a0, a0, a2 ; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: .LBB34_6: # %for.body ; CHECK-NEXT: .LBB34_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft1, 0(a0) ; CHECK-NEXT: flw ft1, 0(a0)
; CHECK-NEXT: flw ft2, 0(a1) ; CHECK-NEXT: flw ft2, 0(a1)
; CHECK-NEXT: mv a2, a3 ; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: fmadd.s ft1, ft1, ft0, ft2 ; CHECK-NEXT: fmadd.s ft1, ft1, ft0, ft2
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_fma_commute_scalable(float* noalias nocapture %a, float* noalias nocapture readonly %b, float %x) { define void @sink_splat_fma_commute_scalable(float* noalias nocapture %a, float* noalias nocapture readonly %b, float %x) {
; CHECK-LABEL: sink_splat_fma_commute_scalable: ; CHECK-LABEL: sink_splat_fma_commute_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a7, vlenb ; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: srli t1, a7, 2 ; CHECK-NEXT: srli a4, a3, 2
; CHECK-NEXT: li t0, 1024 ; CHECK-NEXT: li t0, 1024
; CHECK-NEXT: fmv.w.x ft0, a2 ; CHECK-NEXT: fmv.w.x ft0, a2
; CHECK-NEXT: bgeu t0, t1, .LBB35_2 ; CHECK-NEXT: bgeu t0, a4, .LBB35_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li t0, 0 ; CHECK-NEXT: li a2, 0
; CHECK-NEXT: j .LBB35_5 ; CHECK-NEXT: j .LBB35_5
; CHECK-NEXT: .LBB35_2: # %vector.ph ; CHECK-NEXT: .LBB35_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a6, 0
; CHECK-NEXT: li a3, 0 ; CHECK-NEXT: li a7, 0
; CHECK-NEXT: remu a6, t0, t1 ; CHECK-NEXT: remu a5, t0, a4
; CHECK-NEXT: sub t0, t0, a6 ; CHECK-NEXT: sub a2, t0, a5
; CHECK-NEXT: .LBB35_3: # %vector.body ; CHECK-NEXT: .LBB35_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: add a2, a0, a5 ; CHECK-NEXT: add t0, a0, a6
; CHECK-NEXT: vl1re32.v v8, (a2) ; CHECK-NEXT: vl1re32.v v8, (t0)
; CHECK-NEXT: add a4, a1, a5 ; CHECK-NEXT: add t1, a1, a6
; CHECK-NEXT: vl1re32.v v9, (a4) ; CHECK-NEXT: vl1re32.v v9, (t1)
; CHECK-NEXT: vsetvli a4, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli t1, zero, e32, m1, ta, mu
; CHECK-NEXT: vfmacc.vf v9, ft0, v8 ; CHECK-NEXT: vfmacc.vf v9, ft0, v8
; CHECK-NEXT: vs1r.v v9, (a2) ; CHECK-NEXT: vs1r.v v9, (t0)
; CHECK-NEXT: add a3, a3, t1 ; CHECK-NEXT: add a7, a7, a4
; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a6, a6, a3
; CHECK-NEXT: bne a3, t0, .LBB35_3 ; CHECK-NEXT: bne a7, a2, .LBB35_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB35_7 ; CHECK-NEXT: beqz a5, .LBB35_7
; CHECK-NEXT: .LBB35_5: # %for.body.preheader ; CHECK-NEXT: .LBB35_5: # %for.body.preheader
; CHECK-NEXT: addi a3, t0, -1024 ; CHECK-NEXT: addi a3, a2, -1024
; CHECK-NEXT: slli a2, t0, 2 ; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: add a1, a1, a2 ; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: add a0, a0, a2 ; CHECK-NEXT: add a0, a0, a2
; CHECK-NEXT: .LBB35_6: # %for.body ; CHECK-NEXT: .LBB35_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: flw ft1, 0(a0) ; CHECK-NEXT: flw ft1, 0(a0)
; CHECK-NEXT: flw ft2, 0(a1) ; CHECK-NEXT: flw ft2, 0(a1)
; CHECK-NEXT: mv a2, a3 ; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: fmadd.s ft1, ft0, ft1, ft2 ; CHECK-NEXT: fmadd.s ft1, ft0, ft1, ft2
▲ Show 20 Lines • Show All 284 Lines • ▼ Show 20 Lines
for.cond.cleanup: ; preds = %vector.body for.cond.cleanup: ; preds = %vector.body
ret void ret void
} }
define void @sink_splat_udiv_scalable(i32* nocapture %a, i32 signext %x) { define void @sink_splat_udiv_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-LABEL: sink_splat_udiv_scalable: ; CHECK-LABEL: sink_splat_udiv_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: srli a7, a2, 1 ; CHECK-NEXT: srli a2, a6, 1
; CHECK-NEXT: li a3, 1024 ; CHECK-NEXT: li a3, 1024
; CHECK-NEXT: bgeu a3, a7, .LBB42_2 ; CHECK-NEXT: bgeu a3, a2, .LBB42_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li t0, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: j .LBB42_5 ; CHECK-NEXT: j .LBB42_5
; CHECK-NEXT: .LBB42_2: # %vector.ph ; CHECK-NEXT: .LBB42_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a3, a7 ; CHECK-NEXT: remu a4, a3, a2
; CHECK-NEXT: sub t0, a3, a6 ; CHECK-NEXT: sub a3, a3, a4
; CHECK-NEXT: slli a4, a2, 1 ; CHECK-NEXT: slli a6, a6, 1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a7, a0
; CHECK-NEXT: .LBB42_3: # %vector.body ; CHECK-NEXT: .LBB42_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vl2re32.v v8, (a7)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli t0, zero, e32, m2, ta, mu
; CHECK-NEXT: vdivu.vx v8, v8, a1 ; CHECK-NEXT: vdivu.vx v8, v8, a1
; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: vs2r.v v8, (a7)
; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: add a7, a7, a6
; CHECK-NEXT: bne a5, t0, .LBB42_3 ; CHECK-NEXT: bne a5, a3, .LBB42_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB42_7 ; CHECK-NEXT: beqz a4, .LBB42_7
; CHECK-NEXT: .LBB42_5: # %for.body.preheader ; CHECK-NEXT: .LBB42_5: # %for.body.preheader
; CHECK-NEXT: addi a2, t0, -1024 ; CHECK-NEXT: addi a2, a3, -1024
; CHECK-NEXT: slli a3, t0, 2 ; CHECK-NEXT: slli a3, a3, 2
; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB42_6: # %for.body ; CHECK-NEXT: .LBB42_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a3, 0(a0) ; CHECK-NEXT: lw a3, 0(a0)
; CHECK-NEXT: mv a4, a2 ; CHECK-NEXT: mv a4, a2
; CHECK-NEXT: divuw a2, a3, a1 ; CHECK-NEXT: divuw a2, a3, a1
; CHECK-NEXT: sw a2, 0(a0) ; CHECK-NEXT: sw a2, 0(a0)
; CHECK-NEXT: addi a2, a4, 1 ; CHECK-NEXT: addi a2, a4, 1
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_sdiv_scalable(i32* nocapture %a, i32 signext %x) { define void @sink_splat_sdiv_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-LABEL: sink_splat_sdiv_scalable: ; CHECK-LABEL: sink_splat_sdiv_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: srli a7, a2, 1 ; CHECK-NEXT: srli a2, a6, 1
; CHECK-NEXT: li a3, 1024 ; CHECK-NEXT: li a3, 1024
; CHECK-NEXT: bgeu a3, a7, .LBB43_2 ; CHECK-NEXT: bgeu a3, a2, .LBB43_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li t0, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: j .LBB43_5 ; CHECK-NEXT: j .LBB43_5
; CHECK-NEXT: .LBB43_2: # %vector.ph ; CHECK-NEXT: .LBB43_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a3, a7 ; CHECK-NEXT: remu a4, a3, a2
; CHECK-NEXT: sub t0, a3, a6 ; CHECK-NEXT: sub a3, a3, a4
; CHECK-NEXT: slli a4, a2, 1 ; CHECK-NEXT: slli a6, a6, 1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a7, a0
; CHECK-NEXT: .LBB43_3: # %vector.body ; CHECK-NEXT: .LBB43_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vl2re32.v v8, (a7)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli t0, zero, e32, m2, ta, mu
; CHECK-NEXT: vdiv.vx v8, v8, a1 ; CHECK-NEXT: vdiv.vx v8, v8, a1
; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: vs2r.v v8, (a7)
; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: add a7, a7, a6
; CHECK-NEXT: bne a5, t0, .LBB43_3 ; CHECK-NEXT: bne a5, a3, .LBB43_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB43_7 ; CHECK-NEXT: beqz a4, .LBB43_7
; CHECK-NEXT: .LBB43_5: # %for.body.preheader ; CHECK-NEXT: .LBB43_5: # %for.body.preheader
; CHECK-NEXT: addi a2, t0, -1024 ; CHECK-NEXT: addi a2, a3, -1024
; CHECK-NEXT: slli a3, t0, 2 ; CHECK-NEXT: slli a3, a3, 2
; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB43_6: # %for.body ; CHECK-NEXT: .LBB43_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a3, 0(a0) ; CHECK-NEXT: lw a3, 0(a0)
; CHECK-NEXT: mv a4, a2 ; CHECK-NEXT: mv a4, a2
; CHECK-NEXT: divw a2, a3, a1 ; CHECK-NEXT: divw a2, a3, a1
; CHECK-NEXT: sw a2, 0(a0) ; CHECK-NEXT: sw a2, 0(a0)
; CHECK-NEXT: addi a2, a4, 1 ; CHECK-NEXT: addi a2, a4, 1
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_urem_scalable(i32* nocapture %a, i32 signext %x) { define void @sink_splat_urem_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-LABEL: sink_splat_urem_scalable: ; CHECK-LABEL: sink_splat_urem_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: srli a7, a2, 1 ; CHECK-NEXT: srli a2, a6, 1
; CHECK-NEXT: li a3, 1024 ; CHECK-NEXT: li a3, 1024
; CHECK-NEXT: bgeu a3, a7, .LBB44_2 ; CHECK-NEXT: bgeu a3, a2, .LBB44_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li t0, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: j .LBB44_5 ; CHECK-NEXT: j .LBB44_5
; CHECK-NEXT: .LBB44_2: # %vector.ph ; CHECK-NEXT: .LBB44_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a3, a7 ; CHECK-NEXT: remu a4, a3, a2
; CHECK-NEXT: sub t0, a3, a6 ; CHECK-NEXT: sub a3, a3, a4
; CHECK-NEXT: slli a4, a2, 1 ; CHECK-NEXT: slli a6, a6, 1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a7, a0
; CHECK-NEXT: .LBB44_3: # %vector.body ; CHECK-NEXT: .LBB44_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vl2re32.v v8, (a7)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli t0, zero, e32, m2, ta, mu
; CHECK-NEXT: vremu.vx v8, v8, a1 ; CHECK-NEXT: vremu.vx v8, v8, a1
; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: vs2r.v v8, (a7)
; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: add a7, a7, a6
; CHECK-NEXT: bne a5, t0, .LBB44_3 ; CHECK-NEXT: bne a5, a3, .LBB44_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB44_7 ; CHECK-NEXT: beqz a4, .LBB44_7
; CHECK-NEXT: .LBB44_5: # %for.body.preheader ; CHECK-NEXT: .LBB44_5: # %for.body.preheader
; CHECK-NEXT: addi a2, t0, -1024 ; CHECK-NEXT: addi a2, a3, -1024
; CHECK-NEXT: slli a3, t0, 2 ; CHECK-NEXT: slli a3, a3, 2
; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB44_6: # %for.body ; CHECK-NEXT: .LBB44_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a3, 0(a0) ; CHECK-NEXT: lw a3, 0(a0)
; CHECK-NEXT: mv a4, a2 ; CHECK-NEXT: mv a4, a2
; CHECK-NEXT: remuw a2, a3, a1 ; CHECK-NEXT: remuw a2, a3, a1
; CHECK-NEXT: sw a2, 0(a0) ; CHECK-NEXT: sw a2, 0(a0)
; CHECK-NEXT: addi a2, a4, 1 ; CHECK-NEXT: addi a2, a4, 1
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader, %for.body
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
%cmp.not = icmp eq i64 %indvars.iv.next, 1024 %cmp.not = icmp eq i64 %indvars.iv.next, 1024
br i1 %cmp.not, label %for.cond.cleanup, label %for.body br i1 %cmp.not, label %for.cond.cleanup, label %for.body
} }
define void @sink_splat_srem_scalable(i32* nocapture %a, i32 signext %x) { define void @sink_splat_srem_scalable(i32* nocapture %a, i32 signext %x) {
; CHECK-LABEL: sink_splat_srem_scalable: ; CHECK-LABEL: sink_splat_srem_scalable:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: srli a7, a2, 1 ; CHECK-NEXT: srli a2, a6, 1
; CHECK-NEXT: li a3, 1024 ; CHECK-NEXT: li a3, 1024
; CHECK-NEXT: bgeu a3, a7, .LBB45_2 ; CHECK-NEXT: bgeu a3, a2, .LBB45_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li t0, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: j .LBB45_5 ; CHECK-NEXT: j .LBB45_5
; CHECK-NEXT: .LBB45_2: # %vector.ph ; CHECK-NEXT: .LBB45_2: # %vector.ph
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: remu a6, a3, a7 ; CHECK-NEXT: remu a4, a3, a2
; CHECK-NEXT: sub t0, a3, a6 ; CHECK-NEXT: sub a3, a3, a4
; CHECK-NEXT: slli a4, a2, 1 ; CHECK-NEXT: slli a6, a6, 1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a7, a0
; CHECK-NEXT: .LBB45_3: # %vector.body ; CHECK-NEXT: .LBB45_3: # %vector.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl2re32.v v8, (a2) ; CHECK-NEXT: vl2re32.v v8, (a7)
; CHECK-NEXT: vsetvli a3, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli t0, zero, e32, m2, ta, mu
; CHECK-NEXT: vrem.vx v8, v8, a1 ; CHECK-NEXT: vrem.vx v8, v8, a1
; CHECK-NEXT: vs2r.v v8, (a2) ; CHECK-NEXT: vs2r.v v8, (a7)
; CHECK-NEXT: add a5, a5, a7 ; CHECK-NEXT: add a5, a5, a2
; CHECK-NEXT: add a2, a2, a4 ; CHECK-NEXT: add a7, a7, a6
; CHECK-NEXT: bne a5, t0, .LBB45_3 ; CHECK-NEXT: bne a5, a3, .LBB45_3
; CHECK-NEXT: # %bb.4: # %middle.block ; CHECK-NEXT: # %bb.4: # %middle.block
; CHECK-NEXT: beqz a6, .LBB45_7 ; CHECK-NEXT: beqz a4, .LBB45_7
; CHECK-NEXT: .LBB45_5: # %for.body.preheader ; CHECK-NEXT: .LBB45_5: # %for.body.preheader
; CHECK-NEXT: addi a2, t0, -1024 ; CHECK-NEXT: addi a2, a3, -1024
; CHECK-NEXT: slli a3, t0, 2 ; CHECK-NEXT: slli a3, a3, 2
; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: .LBB45_6: # %for.body ; CHECK-NEXT: .LBB45_6: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lw a3, 0(a0) ; CHECK-NEXT: lw a3, 0(a0)
; CHECK-NEXT: mv a4, a2 ; CHECK-NEXT: mv a4, a2
; CHECK-NEXT: remw a2, a3, a1 ; CHECK-NEXT: remw a2, a3, a1
; CHECK-NEXT: sw a2, 0(a0) ; CHECK-NEXT: sw a2, 0(a0)
; CHECK-NEXT: addi a2, a4, 1 ; CHECK-NEXT: addi a2, a4, 1
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vpload.ll

Show First 20 Lines • Show All 489 Lines • ▼ Show 20 Lines
; vp.load legalization, manually split it. ; vp.load legalization, manually split it.
; Widen to nxv32f64 then split into 4 x nxv8f64, of which 1 is empty. ; Widen to nxv32f64 then split into 4 x nxv8f64, of which 1 is empty.
define <vscale x 16 x double> @vpload_nxv17f64(<vscale x 17 x double>* %ptr, <vscale x 1 x double>* %out, <vscale x 17 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x double> @vpload_nxv17f64(<vscale x 17 x double>* %ptr, <vscale x 1 x double>* %out, <vscale x 17 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpload_nxv17f64: ; CHECK-LABEL: vpload_nxv17f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a7, a3, 1 ; CHECK-NEXT: slli a5, a3, 1
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: mv t0, a2 ; CHECK-NEXT: mv a4, a2
; CHECK-NEXT: bltu a2, a7, .LBB38_2 ; CHECK-NEXT: bltu a2, a5, .LBB38_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv t0, a7 ; CHECK-NEXT: mv a4, a5
; CHECK-NEXT: .LBB38_2: ; CHECK-NEXT: .LBB38_2:
; CHECK-NEXT: sub a5, t0, a3 ; CHECK-NEXT: sub a7, a4, a3
; CHECK-NEXT: li a6, 0 ; CHECK-NEXT: li a6, 0
; CHECK-NEXT: bltu t0, a5, .LBB38_4 ; CHECK-NEXT: bltu a4, a7, .LBB38_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a6, a5 ; CHECK-NEXT: mv a6, a7
; CHECK-NEXT: .LBB38_4: ; CHECK-NEXT: .LBB38_4:
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a7, 0
; CHECK-NEXT: srli t1, a3, 3 ; CHECK-NEXT: srli t0, a3, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli t1, zero, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v0, v8, t1 ; CHECK-NEXT: vslidedown.vx v0, v8, t0
; CHECK-NEXT: slli a4, a3, 3 ; CHECK-NEXT: slli t0, a3, 3
; CHECK-NEXT: add a4, a0, a4 ; CHECK-NEXT: add t0, a0, t0
; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v16, (a4), v0.t ; CHECK-NEXT: vle64.v v16, (t0), v0.t
; CHECK-NEXT: srli a6, a3, 2 ; CHECK-NEXT: srli a6, a3, 2
; CHECK-NEXT: sub a4, a2, a7 ; CHECK-NEXT: sub t0, a2, a5
; CHECK-NEXT: slli a7, a3, 4 ; CHECK-NEXT: slli a5, a3, 4
; CHECK-NEXT: bltu a2, a4, .LBB38_6 ; CHECK-NEXT: bltu a2, t0, .LBB38_6
; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: mv a5, a4 ; CHECK-NEXT: mv a7, t0
; CHECK-NEXT: .LBB38_6: ; CHECK-NEXT: .LBB38_6:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v0, v8, a6 ; CHECK-NEXT: vslidedown.vx v0, v8, a6
; CHECK-NEXT: add a2, a0, a7 ; CHECK-NEXT: add a2, a0, a5
; CHECK-NEXT: bltu a5, a3, .LBB38_8 ; CHECK-NEXT: bltu a7, a3, .LBB38_8
; CHECK-NEXT: # %bb.7: ; CHECK-NEXT: # %bb.7:
; CHECK-NEXT: mv a5, a3 ; CHECK-NEXT: mv a7, a3
; CHECK-NEXT: .LBB38_8: ; CHECK-NEXT: .LBB38_8:
; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a7, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v24, (a2), v0.t ; CHECK-NEXT: vle64.v v24, (a2), v0.t
; CHECK-NEXT: bltu t0, a3, .LBB38_10 ; CHECK-NEXT: bltu a4, a3, .LBB38_10
; CHECK-NEXT: # %bb.9: ; CHECK-NEXT: # %bb.9:
; CHECK-NEXT: mv t0, a3 ; CHECK-NEXT: mv a4, a3
; CHECK-NEXT: .LBB38_10: ; CHECK-NEXT: .LBB38_10:
; CHECK-NEXT: vsetvli zero, t0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vle64.v v8, (a0), v0.t ; CHECK-NEXT: vle64.v v8, (a0), v0.t
; CHECK-NEXT: vs1r.v v24, (a1) ; CHECK-NEXT: vs1r.v v24, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%load = call <vscale x 17 x double> @llvm.vp.load.nxv17f64.p0nxv17f64(<vscale x 17 x double>* %ptr, <vscale x 17 x i1> %m, i32 %evl) %load = call <vscale x 17 x double> @llvm.vp.load.nxv17f64.p0nxv17f64(<vscale x 17 x double>* %ptr, <vscale x 17 x i1> %m, i32 %evl)
%lo = call <vscale x 16 x double> @llvm.experimental.vector.extract.nxv16f64(<vscale x 17 x double> %load, i64 0) %lo = call <vscale x 16 x double> @llvm.experimental.vector.extract.nxv16f64(<vscale x 17 x double> %load, i64 0)
%hi = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64(<vscale x 17 x double> %load, i64 16) %hi = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64(<vscale x 17 x double> %load, i64 16)
store <vscale x 1 x double> %hi, <vscale x 1 x double>* %out store <vscale x 1 x double> %hi, <vscale x 1 x double>* %out
ret <vscale x 16 x double> %lo ret <vscale x 16 x double> %lo
} }

llvm/test/CodeGen/RISCV/rvv/vpstore.ll

Show First 20 Lines • Show All 402 Lines • ▼ Show 20 Lines
; CHECK-LABEL: vpstore_nxv17f64: ; CHECK-LABEL: vpstore_nxv17f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a3, a3, 3 ; CHECK-NEXT: slli a3, a3, 3
; CHECK-NEXT: sub sp, sp, a3 ; CHECK-NEXT: sub sp, sp, a3
; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a6, a3, 1 ; CHECK-NEXT: slli a4, a3, 1
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: addi a4, sp, 16 ; CHECK-NEXT: addi a5, sp, 16
; CHECK-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; CHECK-NEXT: mv a5, a2 ; CHECK-NEXT: mv a5, a2
; CHECK-NEXT: bltu a2, a6, .LBB31_2 ; CHECK-NEXT: bltu a2, a4, .LBB31_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a5, a6 ; CHECK-NEXT: mv a5, a4
; CHECK-NEXT: .LBB31_2: ; CHECK-NEXT: .LBB31_2:
; CHECK-NEXT: mv a4, a5 ; CHECK-NEXT: mv a7, a5
; CHECK-NEXT: bltu a5, a3, .LBB31_4 ; CHECK-NEXT: bltu a5, a3, .LBB31_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a4, a3 ; CHECK-NEXT: mv a7, a3
; CHECK-NEXT: .LBB31_4: ; CHECK-NEXT: .LBB31_4:
; CHECK-NEXT: li a7, 0 ; CHECK-NEXT: li a6, 0
; CHECK-NEXT: vl8re64.v v16, (a0) ; CHECK-NEXT: vl8re64.v v16, (a0)
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a7, e64, m8, ta, mu
; CHECK-NEXT: sub a0, a5, a3 ; CHECK-NEXT: sub a0, a5, a3
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vse64.v v8, (a1), v0.t ; CHECK-NEXT: vse64.v v8, (a1), v0.t
; CHECK-NEXT: bltu a5, a0, .LBB31_6 ; CHECK-NEXT: bltu a5, a0, .LBB31_6
; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: mv a7, a0 ; CHECK-NEXT: mv a6, a0
; CHECK-NEXT: .LBB31_6: ; CHECK-NEXT: .LBB31_6:
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: srli a4, a3, 3 ; CHECK-NEXT: srli a5, a3, 3
; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, mu
; CHECK-NEXT: vslidedown.vx v0, v24, a4 ; CHECK-NEXT: vslidedown.vx v0, v24, a5
; CHECK-NEXT: slli a4, a3, 3 ; CHECK-NEXT: slli a5, a3, 3
; CHECK-NEXT: add a4, a1, a4 ; CHECK-NEXT: add a5, a1, a5
; CHECK-NEXT: vsetvli zero, a7, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, mu
; CHECK-NEXT: addi a5, sp, 16 ; CHECK-NEXT: addi a6, sp, 16
; CHECK-NEXT: vl8re8.v v8, (a5) # Unknown-size Folded Reload ; CHECK-NEXT: vl8re8.v v8, (a6) # Unknown-size Folded Reload
; CHECK-NEXT: vse64.v v8, (a4), v0.t ; CHECK-NEXT: vse64.v v8, (a5), v0.t
; CHECK-NEXT: srli a7, a3, 2 ; CHECK-NEXT: srli a5, a3, 2
; CHECK-NEXT: sub a4, a2, a6 ; CHECK-NEXT: sub a6, a2, a4
; CHECK-NEXT: slli a5, a3, 4 ; CHECK-NEXT: slli a4, a3, 4
; CHECK-NEXT: bltu a2, a4, .LBB31_8 ; CHECK-NEXT: bltu a2, a6, .LBB31_8
; CHECK-NEXT: # %bb.7: ; CHECK-NEXT: # %bb.7:
; CHECK-NEXT: mv a0, a4 ; CHECK-NEXT: mv a0, a6
; CHECK-NEXT: .LBB31_8: ; CHECK-NEXT: .LBB31_8:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vx v0, v24, a7 ; CHECK-NEXT: vslidedown.vx v0, v24, a5
; CHECK-NEXT: add a1, a1, a5 ; CHECK-NEXT: add a1, a1, a4
; CHECK-NEXT: bltu a0, a3, .LBB31_10 ; CHECK-NEXT: bltu a0, a3, .LBB31_10
; CHECK-NEXT: # %bb.9: ; CHECK-NEXT: # %bb.9:
; CHECK-NEXT: mv a0, a3 ; CHECK-NEXT: mv a0, a3
; CHECK-NEXT: .LBB31_10: ; CHECK-NEXT: .LBB31_10:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu
; CHECK-NEXT: vse64.v v16, (a1), v0.t ; CHECK-NEXT: vse64.v v16, (a1), v0.t
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.vp.store.nxv17f64.p0nxv17f64(<vscale x 17 x double> %val, <vscale x 17 x double>* %ptr, <vscale x 17 x i1> %m, i32 %evl) call void @llvm.vp.store.nxv17f64.p0nxv17f64(<vscale x 17 x double> %val, <vscale x 17 x double>* %ptr, <vscale x 17 x i1> %m, i32 %evl)
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll

Show First 20 Lines • Show All 1,179 Lines • ▼ Show 20 Lines
; RV32-NEXT: vmv1r.v v0, v24 ; RV32-NEXT: vmv1r.v v0, v24
; RV32-NEXT: vredmaxu.vs v8, v16, v8, v0.t ; RV32-NEXT: vredmaxu.vs v8, v16, v8, v0.t
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpreduce_umax_nxv32i32: ; RV64-LABEL: vpreduce_umax_nxv32i32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: csrr a3, vlenb ; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: srli a6, a3, 2 ; RV64-NEXT: srli a2, a3, 2
; RV64-NEXT: slli a4, a0, 32 ; RV64-NEXT: slli a4, a0, 32
; RV64-NEXT: slli a0, a3, 1 ; RV64-NEXT: slli a0, a3, 1
; RV64-NEXT: srli a3, a4, 32 ; RV64-NEXT: srli a3, a4, 32
; RV64-NEXT: mv a4, a1 ; RV64-NEXT: mv a4, a1
; RV64-NEXT: bltu a1, a0, .LBB67_2 ; RV64-NEXT: bltu a1, a0, .LBB67_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a4, a0 ; RV64-NEXT: mv a4, a0
; RV64-NEXT: .LBB67_2: ; RV64-NEXT: .LBB67_2:
; RV64-NEXT: li a5, 0 ; RV64-NEXT: li a5, 0
; RV64-NEXT: vsetvli a2, zero, e8, mf2, ta, mu ; RV64-NEXT: vsetvli a6, zero, e8, mf2, ta, mu
; RV64-NEXT: vslidedown.vx v24, v0, a6 ; RV64-NEXT: vslidedown.vx v24, v0, a2
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV64-NEXT: vmv.s.x v25, a3 ; RV64-NEXT: vmv.s.x v25, a3
; RV64-NEXT: vsetvli zero, a4, e32, m8, tu, mu ; RV64-NEXT: vsetvli zero, a4, e32, m8, tu, mu
; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t ; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
; RV64-NEXT: vmv.x.s a2, v25 ; RV64-NEXT: vmv.x.s a2, v25
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu ; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
; RV64-NEXT: sub a0, a1, a0 ; RV64-NEXT: sub a0, a1, a0
; RV64-NEXT: vmv.s.x v8, a2 ; RV64-NEXT: vmv.s.x v8, a2
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llvm/test/CodeGen/RISCV/sadd_sat.ll

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; RV32IZbbZbt-LABEL: func2: ; RV32IZbbZbt-LABEL: func2:
; RV32IZbbZbt: # %bb.0: ; RV32IZbbZbt: # %bb.0:
; RV32IZbbZbt-NEXT: add a4, a1, a3 ; RV32IZbbZbt-NEXT: add a4, a1, a3
; RV32IZbbZbt-NEXT: add a2, a0, a2 ; RV32IZbbZbt-NEXT: add a2, a0, a2
; RV32IZbbZbt-NEXT: sltu a0, a2, a0 ; RV32IZbbZbt-NEXT: sltu a0, a2, a0
; RV32IZbbZbt-NEXT: add a0, a4, a0 ; RV32IZbbZbt-NEXT: add a0, a4, a0
; RV32IZbbZbt-NEXT: srai a4, a0, 31 ; RV32IZbbZbt-NEXT: srai a4, a0, 31
; RV32IZbbZbt-NEXT: lui a5, 524288 ; RV32IZbbZbt-NEXT: lui a5, 524288
; RV32IZbbZbt-NEXT: xor a6, a4, a5 ; RV32IZbbZbt-NEXT: xor a5, a4, a5
; RV32IZbbZbt-NEXT: xor a5, a1, a0 ; RV32IZbbZbt-NEXT: xor a6, a1, a0
; RV32IZbbZbt-NEXT: xor a1, a1, a3 ; RV32IZbbZbt-NEXT: xor a1, a1, a3
; RV32IZbbZbt-NEXT: andn a1, a5, a1 ; RV32IZbbZbt-NEXT: andn a1, a6, a1
; RV32IZbbZbt-NEXT: slti a3, a1, 0 ; RV32IZbbZbt-NEXT: slti a3, a1, 0
; RV32IZbbZbt-NEXT: cmov a1, a3, a6, a0 ; RV32IZbbZbt-NEXT: cmov a1, a3, a5, a0
; RV32IZbbZbt-NEXT: cmov a0, a3, a4, a2 ; RV32IZbbZbt-NEXT: cmov a0, a3, a4, a2
; RV32IZbbZbt-NEXT: ret ; RV32IZbbZbt-NEXT: ret
; ;
; RV64IZbbZbt-LABEL: func2: ; RV64IZbbZbt-LABEL: func2:
; RV64IZbbZbt: # %bb.0: ; RV64IZbbZbt: # %bb.0:
; RV64IZbbZbt-NEXT: add a2, a0, a1 ; RV64IZbbZbt-NEXT: add a2, a0, a1
; RV64IZbbZbt-NEXT: slt a0, a2, a0 ; RV64IZbbZbt-NEXT: slt a0, a2, a0
; RV64IZbbZbt-NEXT: slti a1, a1, 0 ; RV64IZbbZbt-NEXT: slti a1, a1, 0
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llvm/test/CodeGen/RISCV/sadd_sat_plus.ll

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; RV32IZbbZbt-LABEL: func64: ; RV32IZbbZbt-LABEL: func64:
; RV32IZbbZbt: # %bb.0: ; RV32IZbbZbt: # %bb.0:
; RV32IZbbZbt-NEXT: add a2, a1, a5 ; RV32IZbbZbt-NEXT: add a2, a1, a5
; RV32IZbbZbt-NEXT: add a3, a0, a4 ; RV32IZbbZbt-NEXT: add a3, a0, a4
; RV32IZbbZbt-NEXT: sltu a0, a3, a0 ; RV32IZbbZbt-NEXT: sltu a0, a3, a0
; RV32IZbbZbt-NEXT: add a0, a2, a0 ; RV32IZbbZbt-NEXT: add a0, a2, a0
; RV32IZbbZbt-NEXT: srai a2, a0, 31 ; RV32IZbbZbt-NEXT: srai a2, a0, 31
; RV32IZbbZbt-NEXT: lui a4, 524288 ; RV32IZbbZbt-NEXT: lui a4, 524288
; RV32IZbbZbt-NEXT: xor a6, a2, a4 ; RV32IZbbZbt-NEXT: xor a4, a2, a4
; RV32IZbbZbt-NEXT: xor a4, a1, a0 ; RV32IZbbZbt-NEXT: xor a6, a1, a0
; RV32IZbbZbt-NEXT: xor a1, a1, a5 ; RV32IZbbZbt-NEXT: xor a1, a1, a5
; RV32IZbbZbt-NEXT: andn a1, a4, a1 ; RV32IZbbZbt-NEXT: andn a1, a6, a1
; RV32IZbbZbt-NEXT: slti a4, a1, 0 ; RV32IZbbZbt-NEXT: slti a5, a1, 0
; RV32IZbbZbt-NEXT: cmov a1, a4, a6, a0 ; RV32IZbbZbt-NEXT: cmov a1, a5, a4, a0
; RV32IZbbZbt-NEXT: cmov a0, a4, a2, a3 ; RV32IZbbZbt-NEXT: cmov a0, a5, a2, a3
; RV32IZbbZbt-NEXT: ret ; RV32IZbbZbt-NEXT: ret
; ;
; RV64IZbbZbt-LABEL: func64: ; RV64IZbbZbt-LABEL: func64:
; RV64IZbbZbt: # %bb.0: ; RV64IZbbZbt: # %bb.0:
; RV64IZbbZbt-NEXT: add a1, a0, a2 ; RV64IZbbZbt-NEXT: add a1, a0, a2
; RV64IZbbZbt-NEXT: slt a0, a1, a0 ; RV64IZbbZbt-NEXT: slt a0, a1, a0
; RV64IZbbZbt-NEXT: slti a2, a2, 0 ; RV64IZbbZbt-NEXT: slti a2, a2, 0
; RV64IZbbZbt-NEXT: xor a0, a2, a0 ; RV64IZbbZbt-NEXT: xor a0, a2, a0
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llvm/test/CodeGen/RISCV/select-optimize-multiple.ll

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; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: beqz a1, .LBB1_2 ; RV32I-NEXT: beqz a1, .LBB1_2
; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a2, a4 ; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: .LBB1_2: # %entry ; RV32I-NEXT: .LBB1_2: # %entry
; RV32I-NEXT: beqz a1, .LBB1_5 ; RV32I-NEXT: beqz a1, .LBB1_5
; RV32I-NEXT: # %bb.3: # %entry ; RV32I-NEXT: # %bb.3: # %entry
; RV32I-NEXT: addi a7, a4, 4 ; RV32I-NEXT: addi a5, a4, 4
; RV32I-NEXT: bnez a1, .LBB1_6 ; RV32I-NEXT: bnez a1, .LBB1_6
; RV32I-NEXT: .LBB1_4: ; RV32I-NEXT: .LBB1_4:
; RV32I-NEXT: addi a5, a3, 8 ; RV32I-NEXT: addi a6, a3, 8
; RV32I-NEXT: j .LBB1_7 ; RV32I-NEXT: j .LBB1_7
; RV32I-NEXT: .LBB1_5: ; RV32I-NEXT: .LBB1_5:
; RV32I-NEXT: addi a7, a3, 4 ; RV32I-NEXT: addi a5, a3, 4
; RV32I-NEXT: beqz a1, .LBB1_4 ; RV32I-NEXT: beqz a1, .LBB1_4
; RV32I-NEXT: .LBB1_6: # %entry ; RV32I-NEXT: .LBB1_6: # %entry
; RV32I-NEXT: addi a5, a4, 8 ; RV32I-NEXT: addi a6, a4, 8
; RV32I-NEXT: .LBB1_7: # %entry ; RV32I-NEXT: .LBB1_7: # %entry
; RV32I-NEXT: lw a6, 0(a2) ; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a7, 0(a7) ; RV32I-NEXT: lw a5, 0(a5)
; RV32I-NEXT: lw a2, 0(a5) ; RV32I-NEXT: lw a6, 0(a6)
; RV32I-NEXT: beqz a1, .LBB1_9 ; RV32I-NEXT: beqz a1, .LBB1_9
; RV32I-NEXT: # %bb.8: # %entry ; RV32I-NEXT: # %bb.8: # %entry
; RV32I-NEXT: addi a1, a4, 12 ; RV32I-NEXT: addi a1, a4, 12
; RV32I-NEXT: j .LBB1_10 ; RV32I-NEXT: j .LBB1_10
; RV32I-NEXT: .LBB1_9: ; RV32I-NEXT: .LBB1_9:
; RV32I-NEXT: addi a1, a3, 12 ; RV32I-NEXT: addi a1, a3, 12
; RV32I-NEXT: .LBB1_10: # %entry ; RV32I-NEXT: .LBB1_10: # %entry
; RV32I-NEXT: lw a1, 0(a1) ; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sw a1, 12(a0) ; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: sw a2, 8(a0) ; RV32I-NEXT: sw a6, 8(a0)
; RV32I-NEXT: sw a7, 4(a0) ; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: sw a6, 0(a0) ; RV32I-NEXT: sw a2, 0(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: cmovcc128: ; RV32IBT-LABEL: cmovcc128:
; RV32IBT: # %bb.0: # %entry ; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: addi a6, a3, 12 ; RV32IBT-NEXT: addi a5, a3, 12
; RV32IBT-NEXT: addi a7, a4, 12 ; RV32IBT-NEXT: addi a6, a4, 12
; RV32IBT-NEXT: addi t0, a3, 8 ; RV32IBT-NEXT: addi a7, a3, 8
; RV32IBT-NEXT: addi t1, a4, 8 ; RV32IBT-NEXT: addi t0, a4, 8
; RV32IBT-NEXT: addi t2, a3, 4 ; RV32IBT-NEXT: addi t1, a3, 4
; RV32IBT-NEXT: addi a5, a4, 4 ; RV32IBT-NEXT: addi t2, a4, 4
; RV32IBT-NEXT: xori a1, a1, 123 ; RV32IBT-NEXT: xori a1, a1, 123
; RV32IBT-NEXT: or a1, a1, a2 ; RV32IBT-NEXT: or a1, a1, a2
; RV32IBT-NEXT: cmov a2, a1, a4, a3 ; RV32IBT-NEXT: cmov a2, a1, a4, a3
; RV32IBT-NEXT: cmov a3, a1, a5, t2 ; RV32IBT-NEXT: cmov a3, a1, t2, t1
; RV32IBT-NEXT: cmov a4, a1, t1, t0 ; RV32IBT-NEXT: cmov a4, a1, t0, a7
; RV32IBT-NEXT: cmov a1, a1, a7, a6 ; RV32IBT-NEXT: cmov a1, a1, a6, a5
; RV32IBT-NEXT: lw a1, 0(a1) ; RV32IBT-NEXT: lw a1, 0(a1)
; RV32IBT-NEXT: lw a4, 0(a4) ; RV32IBT-NEXT: lw a4, 0(a4)
; RV32IBT-NEXT: lw a3, 0(a3) ; RV32IBT-NEXT: lw a3, 0(a3)
; RV32IBT-NEXT: lw a2, 0(a2) ; RV32IBT-NEXT: lw a2, 0(a2)
; RV32IBT-NEXT: sw a1, 12(a0) ; RV32IBT-NEXT: sw a1, 12(a0)
; RV32IBT-NEXT: sw a4, 8(a0) ; RV32IBT-NEXT: sw a4, 8(a0)
; RV32IBT-NEXT: sw a3, 4(a0) ; RV32IBT-NEXT: sw a3, 4(a0)
; RV32IBT-NEXT: sw a2, 0(a0) ; RV32IBT-NEXT: sw a2, 0(a0)
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
; RV32I-NEXT: andi a1, a1, 1 ; RV32I-NEXT: andi a1, a1, 1
; RV32I-NEXT: mv a4, a2 ; RV32I-NEXT: mv a4, a2
; RV32I-NEXT: bnez a1, .LBB3_2 ; RV32I-NEXT: bnez a1, .LBB3_2
; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a4, a3 ; RV32I-NEXT: mv a4, a3
; RV32I-NEXT: .LBB3_2: # %entry ; RV32I-NEXT: .LBB3_2: # %entry
; RV32I-NEXT: bnez a1, .LBB3_5 ; RV32I-NEXT: bnez a1, .LBB3_5
; RV32I-NEXT: # %bb.3: # %entry ; RV32I-NEXT: # %bb.3: # %entry
; RV32I-NEXT: addi a7, a3, 4 ; RV32I-NEXT: addi a5, a3, 4
; RV32I-NEXT: beqz a1, .LBB3_6 ; RV32I-NEXT: beqz a1, .LBB3_6
; RV32I-NEXT: .LBB3_4: ; RV32I-NEXT: .LBB3_4:
; RV32I-NEXT: addi a5, a2, 8 ; RV32I-NEXT: addi a6, a2, 8
; RV32I-NEXT: j .LBB3_7 ; RV32I-NEXT: j .LBB3_7
; RV32I-NEXT: .LBB3_5: ; RV32I-NEXT: .LBB3_5:
; RV32I-NEXT: addi a7, a2, 4 ; RV32I-NEXT: addi a5, a2, 4
; RV32I-NEXT: bnez a1, .LBB3_4 ; RV32I-NEXT: bnez a1, .LBB3_4
; RV32I-NEXT: .LBB3_6: # %entry ; RV32I-NEXT: .LBB3_6: # %entry
; RV32I-NEXT: addi a5, a3, 8 ; RV32I-NEXT: addi a6, a3, 8
; RV32I-NEXT: .LBB3_7: # %entry ; RV32I-NEXT: .LBB3_7: # %entry
; RV32I-NEXT: lw a6, 0(a4) ; RV32I-NEXT: lw a4, 0(a4)
; RV32I-NEXT: lw a7, 0(a7) ; RV32I-NEXT: lw a5, 0(a5)
; RV32I-NEXT: lw a4, 0(a5) ; RV32I-NEXT: lw a6, 0(a6)
; RV32I-NEXT: bnez a1, .LBB3_9 ; RV32I-NEXT: bnez a1, .LBB3_9
; RV32I-NEXT: # %bb.8: # %entry ; RV32I-NEXT: # %bb.8: # %entry
; RV32I-NEXT: addi a1, a3, 12 ; RV32I-NEXT: addi a1, a3, 12
; RV32I-NEXT: j .LBB3_10 ; RV32I-NEXT: j .LBB3_10
; RV32I-NEXT: .LBB3_9: ; RV32I-NEXT: .LBB3_9:
; RV32I-NEXT: addi a1, a2, 12 ; RV32I-NEXT: addi a1, a2, 12
; RV32I-NEXT: .LBB3_10: # %entry ; RV32I-NEXT: .LBB3_10: # %entry
; RV32I-NEXT: lw a1, 0(a1) ; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sw a1, 12(a0) ; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: sw a4, 8(a0) ; RV32I-NEXT: sw a6, 8(a0)
; RV32I-NEXT: sw a7, 4(a0) ; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: sw a6, 0(a0) ; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: cmov128: ; RV32IBT-LABEL: cmov128:
; RV32IBT: # %bb.0: # %entry ; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: addi a6, a3, 12 ; RV32IBT-NEXT: addi a4, a3, 12
; RV32IBT-NEXT: addi a7, a2, 12 ; RV32IBT-NEXT: addi a5, a2, 12
; RV32IBT-NEXT: addi t0, a3, 8 ; RV32IBT-NEXT: addi a6, a3, 8
; RV32IBT-NEXT: addi t1, a2, 8 ; RV32IBT-NEXT: addi a7, a2, 8
; RV32IBT-NEXT: addi a4, a3, 4 ; RV32IBT-NEXT: addi t0, a3, 4
; RV32IBT-NEXT: addi a5, a2, 4 ; RV32IBT-NEXT: addi t1, a2, 4
; RV32IBT-NEXT: andi a1, a1, 1 ; RV32IBT-NEXT: andi a1, a1, 1
; RV32IBT-NEXT: cmov a2, a1, a2, a3 ; RV32IBT-NEXT: cmov a2, a1, a2, a3
; RV32IBT-NEXT: cmov a3, a1, a5, a4 ; RV32IBT-NEXT: cmov a3, a1, t1, t0
; RV32IBT-NEXT: cmov a4, a1, t1, t0 ; RV32IBT-NEXT: cmov a6, a1, a7, a6
; RV32IBT-NEXT: cmov a1, a1, a7, a6 ; RV32IBT-NEXT: cmov a1, a1, a5, a4
; RV32IBT-NEXT: lw a1, 0(a1) ; RV32IBT-NEXT: lw a1, 0(a1)
; RV32IBT-NEXT: lw a4, 0(a4) ; RV32IBT-NEXT: lw a4, 0(a6)
; RV32IBT-NEXT: lw a3, 0(a3) ; RV32IBT-NEXT: lw a3, 0(a3)
; RV32IBT-NEXT: lw a2, 0(a2) ; RV32IBT-NEXT: lw a2, 0(a2)
; RV32IBT-NEXT: sw a1, 12(a0) ; RV32IBT-NEXT: sw a1, 12(a0)
; RV32IBT-NEXT: sw a4, 8(a0) ; RV32IBT-NEXT: sw a4, 8(a0)
; RV32IBT-NEXT: sw a3, 4(a0) ; RV32IBT-NEXT: sw a3, 4(a0)
; RV32IBT-NEXT: sw a2, 0(a0) ; RV32IBT-NEXT: sw a2, 0(a0)
; RV32IBT-NEXT: ret ; RV32IBT-NEXT: ret
; ;
▲ Show 20 Lines • Show All 225 Lines • ▼ Show 20 Linesentry:
ret i32 %ret ret i32 %ret
} }
; Check that selects with different conditions aren't incorrectly optimized. ; Check that selects with different conditions aren't incorrectly optimized.
define i32 @cmovdiffcc(i1 %a, i1 %b, i32 %c, i32 %d, i32 %e, i32 %f) nounwind { define i32 @cmovdiffcc(i1 %a, i1 %b, i32 %c, i32 %d, i32 %e, i32 %f) nounwind {
; RV32I-LABEL: cmovdiffcc: ; RV32I-LABEL: cmovdiffcc:
; RV32I: # %bb.0: # %entry ; RV32I: # %bb.0: # %entry
; RV32I-NEXT: andi a0, a0, 1 ; RV32I-NEXT: andi a6, a0, 1
; RV32I-NEXT: andi a1, a1, 1 ; RV32I-NEXT: andi a0, a1, 1
; RV32I-NEXT: beqz a0, .LBB7_3 ; RV32I-NEXT: beqz a6, .LBB7_3
; RV32I-NEXT: # %bb.1: # %entry ; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: beqz a1, .LBB7_4 ; RV32I-NEXT: beqz a0, .LBB7_4
; RV32I-NEXT: .LBB7_2: # %entry ; RV32I-NEXT: .LBB7_2: # %entry
; RV32I-NEXT: add a0, a2, a4 ; RV32I-NEXT: add a0, a2, a4
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB7_3: # %entry ; RV32I-NEXT: .LBB7_3: # %entry
; RV32I-NEXT: mv a2, a3 ; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: bnez a1, .LBB7_2 ; RV32I-NEXT: bnez a0, .LBB7_2
; RV32I-NEXT: .LBB7_4: # %entry ; RV32I-NEXT: .LBB7_4: # %entry
; RV32I-NEXT: mv a4, a5 ; RV32I-NEXT: mv a4, a5
; RV32I-NEXT: add a0, a2, a4 ; RV32I-NEXT: add a0, a2, a4
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IBT-LABEL: cmovdiffcc: ; RV32IBT-LABEL: cmovdiffcc:
; RV32IBT: # %bb.0: # %entry ; RV32IBT: # %bb.0: # %entry
; RV32IBT-NEXT: andi a1, a1, 1 ; RV32IBT-NEXT: andi a1, a1, 1
; RV32IBT-NEXT: andi a0, a0, 1 ; RV32IBT-NEXT: andi a0, a0, 1
; RV32IBT-NEXT: cmov a0, a0, a2, a3 ; RV32IBT-NEXT: cmov a0, a0, a2, a3
; RV32IBT-NEXT: cmov a1, a1, a4, a5 ; RV32IBT-NEXT: cmov a1, a1, a4, a5
; RV32IBT-NEXT: add a0, a0, a1 ; RV32IBT-NEXT: add a0, a0, a1
; RV32IBT-NEXT: ret ; RV32IBT-NEXT: ret
; ;
; RV64I-LABEL: cmovdiffcc: ; RV64I-LABEL: cmovdiffcc:
; RV64I: # %bb.0: # %entry ; RV64I: # %bb.0: # %entry
; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: andi a6, a0, 1
; RV64I-NEXT: andi a1, a1, 1 ; RV64I-NEXT: andi a0, a1, 1
; RV64I-NEXT: beqz a0, .LBB7_3 ; RV64I-NEXT: beqz a6, .LBB7_3
; RV64I-NEXT: # %bb.1: # %entry ; RV64I-NEXT: # %bb.1: # %entry
; RV64I-NEXT: beqz a1, .LBB7_4 ; RV64I-NEXT: beqz a0, .LBB7_4
; RV64I-NEXT: .LBB7_2: # %entry ; RV64I-NEXT: .LBB7_2: # %entry
; RV64I-NEXT: addw a0, a2, a4 ; RV64I-NEXT: addw a0, a2, a4
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; RV64I-NEXT: .LBB7_3: # %entry ; RV64I-NEXT: .LBB7_3: # %entry
; RV64I-NEXT: mv a2, a3 ; RV64I-NEXT: mv a2, a3
; RV64I-NEXT: bnez a1, .LBB7_2 ; RV64I-NEXT: bnez a0, .LBB7_2
; RV64I-NEXT: .LBB7_4: # %entry ; RV64I-NEXT: .LBB7_4: # %entry
; RV64I-NEXT: mv a4, a5 ; RV64I-NEXT: mv a4, a5
; RV64I-NEXT: addw a0, a2, a4 ; RV64I-NEXT: addw a0, a2, a4
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IBT-LABEL: cmovdiffcc: ; RV64IBT-LABEL: cmovdiffcc:
; RV64IBT: # %bb.0: # %entry ; RV64IBT: # %bb.0: # %entry
; RV64IBT-NEXT: andi a1, a1, 1 ; RV64IBT-NEXT: andi a1, a1, 1
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llvm/test/CodeGen/RISCV/sextw-removal.ll

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; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sraw a0, a0, a1 ; RV64I-NEXT: sraw a0, a0, a1
; RV64I-NEXT: lui a1, 349525 ; RV64I-NEXT: lui a1, 349525
; RV64I-NEXT: addiw s2, a1, 1365 ; RV64I-NEXT: addiw s0, a1, 1365
; RV64I-NEXT: lui a1, 209715 ; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw s1, a1, 819 ; RV64I-NEXT: addiw s1, a1, 819
; RV64I-NEXT: lui a1, 61681 ; RV64I-NEXT: lui a1, 61681
; RV64I-NEXT: addiw s3, a1, -241 ; RV64I-NEXT: addiw s2, a1, -241
; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw s0, a1, 257 ; RV64I-NEXT: addiw s3, a1, 257
; RV64I-NEXT: .LBB4_1: # %bb2 ; RV64I-NEXT: .LBB4_1: # %bb2
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: call bar@plt ; RV64I-NEXT: call bar@plt
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: and a0, a0, s2 ; RV64I-NEXT: and a0, a0, s0
; RV64I-NEXT: subw a0, a1, a0 ; RV64I-NEXT: subw a0, a1, a0
; RV64I-NEXT: and a2, a0, s1 ; RV64I-NEXT: and a2, a0, s1
; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, s1 ; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: add a0, a2, a0 ; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: srli a2, a0, 4 ; RV64I-NEXT: srli a2, a0, 4
; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: and a0, a0, s3 ; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: mulw a0, a0, s0 ; RV64I-NEXT: mulw a0, a0, s3
; RV64I-NEXT: srliw a0, a0, 24 ; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: bnez a1, .LBB4_1 ; RV64I-NEXT: bnez a1, .LBB4_1
; RV64I-NEXT: # %bb.2: # %bb7 ; RV64I-NEXT: # %bb.2: # %bb7
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
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llvm/test/CodeGen/RISCV/shadowcallstack.ll

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s3, 0(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s3, 0(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: .cfi_offset s0, -8 ; RV32-NEXT: .cfi_offset s0, -8
; RV32-NEXT: .cfi_offset s1, -12 ; RV32-NEXT: .cfi_offset s1, -12
; RV32-NEXT: .cfi_offset s3, -16 ; RV32-NEXT: .cfi_offset s3, -16
; RV32-NEXT: call bar@plt ; RV32-NEXT: call bar@plt
; RV32-NEXT: mv s3, a0 ; RV32-NEXT: mv s0, a0
; RV32-NEXT: call bar@plt ; RV32-NEXT: call bar@plt
; RV32-NEXT: mv s1, a0 ; RV32-NEXT: mv s1, a0
; RV32-NEXT: call bar@plt ; RV32-NEXT: call bar@plt
; RV32-NEXT: mv s0, a0 ; RV32-NEXT: mv s3, a0
; RV32-NEXT: call bar@plt ; RV32-NEXT: call bar@plt
; RV32-NEXT: add a1, s3, s1 ; RV32-NEXT: add a1, s0, s1
; RV32-NEXT: add a0, s0, a0 ; RV32-NEXT: add a0, s3, a0
; RV32-NEXT: add a0, a1, a0 ; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s3, 0(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s3, 0(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: lw ra, -4(s2) ; RV32-NEXT: lw ra, -4(s2)
; RV32-NEXT: addi s2, s2, -4 ; RV32-NEXT: addi s2, s2, -4
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; RV64-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s3, 0(sp) # 8-byte Folded Spill ; RV64-NEXT: sd s3, 0(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8 ; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: .cfi_offset s0, -16 ; RV64-NEXT: .cfi_offset s0, -16
; RV64-NEXT: .cfi_offset s1, -24 ; RV64-NEXT: .cfi_offset s1, -24
; RV64-NEXT: .cfi_offset s3, -32 ; RV64-NEXT: .cfi_offset s3, -32
; RV64-NEXT: call bar@plt ; RV64-NEXT: call bar@plt
; RV64-NEXT: mv s3, a0 ; RV64-NEXT: mv s0, a0
; RV64-NEXT: call bar@plt ; RV64-NEXT: call bar@plt
; RV64-NEXT: mv s1, a0 ; RV64-NEXT: mv s1, a0
; RV64-NEXT: call bar@plt ; RV64-NEXT: call bar@plt
; RV64-NEXT: mv s0, a0 ; RV64-NEXT: mv s3, a0
; RV64-NEXT: call bar@plt ; RV64-NEXT: call bar@plt
; RV64-NEXT: addw a1, s3, s1 ; RV64-NEXT: addw a1, s0, s1
; RV64-NEXT: addw a0, s0, a0 ; RV64-NEXT: addw a0, s3, a0
; RV64-NEXT: addw a0, a1, a0 ; RV64-NEXT: addw a0, a1, a0
; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s1, 8(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s3, 0(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s3, 0(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 32 ; RV64-NEXT: addi sp, sp, 32
; RV64-NEXT: ld ra, -8(s2) ; RV64-NEXT: ld ra, -8(s2)
; RV64-NEXT: addi s2, s2, -8 ; RV64-NEXT: addi s2, s2, -8
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llvm/test/CodeGen/RISCV/shifts.ll

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = shl i64 %a, %b %1 = shl i64 %a, %b
ret i64 %1 ret i64 %1
} }
define i128 @lshr128(i128 %a, i128 %b) nounwind { define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: lshr128: ; RV32I-LABEL: lshr128:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a2, 0(a2) ; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw t0, 8(a1) ; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw t4, 12(a1) ; RV32I-NEXT: lw a4, 12(a1)
; RV32I-NEXT: li a6, 64 ; RV32I-NEXT: li a3, 64
; RV32I-NEXT: sub t0, a3, a2
; RV32I-NEXT: li a6, 32
; RV32I-NEXT: sub t1, a6, a2 ; RV32I-NEXT: sub t1, a6, a2
; RV32I-NEXT: li a3, 32
; RV32I-NEXT: sub t5, a3, a2
; RV32I-NEXT: li t2, 31 ; RV32I-NEXT: li t2, 31
; RV32I-NEXT: bltz t5, .LBB6_2 ; RV32I-NEXT: bltz t1, .LBB6_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sll a3, t0, t5 ; RV32I-NEXT: sll t6, a5, t1
; RV32I-NEXT: j .LBB6_3 ; RV32I-NEXT: j .LBB6_3
; RV32I-NEXT: .LBB6_2: ; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: sll a3, t4, t1 ; RV32I-NEXT: sll a6, a4, t0
; RV32I-NEXT: sub a4, t2, t1 ; RV32I-NEXT: sub a7, t2, t0
; RV32I-NEXT: srli a5, t0, 1 ; RV32I-NEXT: srli t3, a5, 1
; RV32I-NEXT: srl a4, a5, a4 ; RV32I-NEXT: srl a7, t3, a7
; RV32I-NEXT: or a3, a3, a4 ; RV32I-NEXT: or t6, a6, a7
; RV32I-NEXT: .LBB6_3: ; RV32I-NEXT: .LBB6_3:
; RV32I-NEXT: lw a5, 4(a1) ; RV32I-NEXT: lw t5, 4(a1)
; RV32I-NEXT: addi t6, a2, -32 ; RV32I-NEXT: addi a6, a2, -32
; RV32I-NEXT: bgez t6, .LBB6_5 ; RV32I-NEXT: bgez a6, .LBB6_5
; RV32I-NEXT: # %bb.4: ; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: srl a4, a5, a2 ; RV32I-NEXT: srl a7, t5, a2
; RV32I-NEXT: or a3, a3, a4 ; RV32I-NEXT: or t6, t6, a7
; RV32I-NEXT: .LBB6_5: ; RV32I-NEXT: .LBB6_5:
; RV32I-NEXT: addi a4, a2, -96 ; RV32I-NEXT: addi t4, a2, -96
; RV32I-NEXT: addi t3, a2, -64 ; RV32I-NEXT: addi t3, a2, -64
; RV32I-NEXT: bltz a4, .LBB6_7 ; RV32I-NEXT: bltz t4, .LBB6_7
; RV32I-NEXT: # %bb.6: ; RV32I-NEXT: # %bb.6:
; RV32I-NEXT: li a7, 0 ; RV32I-NEXT: li a7, 0
; RV32I-NEXT: bgeu a2, a6, .LBB6_8 ; RV32I-NEXT: bgeu a2, a3, .LBB6_8
; RV32I-NEXT: j .LBB6_9 ; RV32I-NEXT: j .LBB6_9
; RV32I-NEXT: .LBB6_7: ; RV32I-NEXT: .LBB6_7:
; RV32I-NEXT: srl a7, t4, t3 ; RV32I-NEXT: srl a7, a4, t3
; RV32I-NEXT: bltu a2, a6, .LBB6_9 ; RV32I-NEXT: bltu a2, a3, .LBB6_9
; RV32I-NEXT: .LBB6_8: ; RV32I-NEXT: .LBB6_8:
; RV32I-NEXT: mv a3, a7 ; RV32I-NEXT: mv t6, a7
; RV32I-NEXT: .LBB6_9: ; RV32I-NEXT: .LBB6_9:
; RV32I-NEXT: mv a7, a5 ; RV32I-NEXT: mv a7, t5
; RV32I-NEXT: beqz a2, .LBB6_11 ; RV32I-NEXT: beqz a2, .LBB6_11
; RV32I-NEXT: # %bb.10: ; RV32I-NEXT: # %bb.10:
; RV32I-NEXT: mv a7, a3 ; RV32I-NEXT: mv a7, t6
; RV32I-NEXT: .LBB6_11: ; RV32I-NEXT: .LBB6_11:
; RV32I-NEXT: lw s0, 0(a1) ; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sub t2, t2, a2 ; RV32I-NEXT: sub t2, t2, a2
; RV32I-NEXT: bltz t6, .LBB6_13 ; RV32I-NEXT: bltz a6, .LBB6_13
; RV32I-NEXT: # %bb.12: ; RV32I-NEXT: # %bb.12:
; RV32I-NEXT: srl a5, a5, t6 ; RV32I-NEXT: srl t5, t5, a6
; RV32I-NEXT: bltz t5, .LBB6_14 ; RV32I-NEXT: bltz t1, .LBB6_14
; RV32I-NEXT: j .LBB6_15 ; RV32I-NEXT: j .LBB6_15
; RV32I-NEXT: .LBB6_13: ; RV32I-NEXT: .LBB6_13:
; RV32I-NEXT: srl a3, s0, a2 ; RV32I-NEXT: srl t6, a1, a2
; RV32I-NEXT: slli a5, a5, 1 ; RV32I-NEXT: slli t5, t5, 1
; RV32I-NEXT: sll a5, a5, t2 ; RV32I-NEXT: sll t5, t5, t2
; RV32I-NEXT: or a5, a3, a5 ; RV32I-NEXT: or t5, t6, t5
; RV32I-NEXT: bgez t5, .LBB6_15 ; RV32I-NEXT: bgez t1, .LBB6_15
; RV32I-NEXT: .LBB6_14: ; RV32I-NEXT: .LBB6_14:
; RV32I-NEXT: sll a3, t0, t1 ; RV32I-NEXT: sll t0, a5, t0
; RV32I-NEXT: or a5, a5, a3 ; RV32I-NEXT: or t5, t5, t0
; RV32I-NEXT: .LBB6_15: ; RV32I-NEXT: .LBB6_15:
; RV32I-NEXT: slli a3, t4, 1 ; RV32I-NEXT: slli t0, a4, 1
; RV32I-NEXT: bltz a4, .LBB6_17 ; RV32I-NEXT: bltz t4, .LBB6_17
; RV32I-NEXT: # %bb.16: ; RV32I-NEXT: # %bb.16:
; RV32I-NEXT: srl a4, t4, a4 ; RV32I-NEXT: srl t1, a4, t4
; RV32I-NEXT: bgeu a2, a6, .LBB6_18 ; RV32I-NEXT: bgeu a2, a3, .LBB6_18
; RV32I-NEXT: j .LBB6_19 ; RV32I-NEXT: j .LBB6_19
; RV32I-NEXT: .LBB6_17: ; RV32I-NEXT: .LBB6_17:
; RV32I-NEXT: li a4, 95 ; RV32I-NEXT: li t1, 95
; RV32I-NEXT: sub a4, a4, a2 ; RV32I-NEXT: sub t1, t1, a2
; RV32I-NEXT: sll a4, a3, a4 ; RV32I-NEXT: sll t1, t0, t1
; RV32I-NEXT: srl a1, t0, t3 ; RV32I-NEXT: srl t3, a5, t3
; RV32I-NEXT: or a4, a1, a4 ; RV32I-NEXT: or t1, t3, t1
; RV32I-NEXT: bltu a2, a6, .LBB6_19 ; RV32I-NEXT: bltu a2, a3, .LBB6_19
; RV32I-NEXT: .LBB6_18: ; RV32I-NEXT: .LBB6_18:
; RV32I-NEXT: mv a5, a4 ; RV32I-NEXT: mv t5, t1
; RV32I-NEXT: .LBB6_19: ; RV32I-NEXT: .LBB6_19:
; RV32I-NEXT: bnez a2, .LBB6_22 ; RV32I-NEXT: bnez a2, .LBB6_22
; RV32I-NEXT: # %bb.20: ; RV32I-NEXT: # %bb.20:
; RV32I-NEXT: bltz t6, .LBB6_23 ; RV32I-NEXT: bltz a6, .LBB6_23
; RV32I-NEXT: .LBB6_21: ; RV32I-NEXT: .LBB6_21:
; RV32I-NEXT: srl a3, t4, t6 ; RV32I-NEXT: srl a5, a4, a6
; RV32I-NEXT: bgeu a2, a6, .LBB6_24 ; RV32I-NEXT: bgeu a2, a3, .LBB6_24
; RV32I-NEXT: j .LBB6_25 ; RV32I-NEXT: j .LBB6_25
; RV32I-NEXT: .LBB6_22: ; RV32I-NEXT: .LBB6_22:
; RV32I-NEXT: mv s0, a5 ; RV32I-NEXT: mv a1, t5
; RV32I-NEXT: bgez t6, .LBB6_21 ; RV32I-NEXT: bgez a6, .LBB6_21
; RV32I-NEXT: .LBB6_23: ; RV32I-NEXT: .LBB6_23:
; RV32I-NEXT: srl a1, t0, a2 ; RV32I-NEXT: srl a5, a5, a2
; RV32I-NEXT: sll a3, a3, t2 ; RV32I-NEXT: sll t0, t0, t2
; RV32I-NEXT: or a3, a1, a3 ; RV32I-NEXT: or a5, a5, t0
; RV32I-NEXT: bltu a2, a6, .LBB6_25 ; RV32I-NEXT: bltu a2, a3, .LBB6_25
; RV32I-NEXT: .LBB6_24: ; RV32I-NEXT: .LBB6_24:
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a5, 0
; RV32I-NEXT: .LBB6_25: ; RV32I-NEXT: .LBB6_25:
; RV32I-NEXT: bltz t6, .LBB6_27 ; RV32I-NEXT: bltz a6, .LBB6_27
; RV32I-NEXT: # %bb.26: ; RV32I-NEXT: # %bb.26:
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: bgeu a2, a6, .LBB6_28 ; RV32I-NEXT: bgeu a2, a3, .LBB6_28
; RV32I-NEXT: j .LBB6_29 ; RV32I-NEXT: j .LBB6_29
; RV32I-NEXT: .LBB6_27: ; RV32I-NEXT: .LBB6_27:
; RV32I-NEXT: srl a4, t4, a2 ; RV32I-NEXT: srl a4, a4, a2
; RV32I-NEXT: bltu a2, a6, .LBB6_29 ; RV32I-NEXT: bltu a2, a3, .LBB6_29
; RV32I-NEXT: .LBB6_28: ; RV32I-NEXT: .LBB6_28:
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: .LBB6_29: ; RV32I-NEXT: .LBB6_29:
; RV32I-NEXT: sw a4, 12(a0) ; RV32I-NEXT: sw a4, 12(a0)
; RV32I-NEXT: sw a3, 8(a0) ; RV32I-NEXT: sw a5, 8(a0)
; RV32I-NEXT: sw s0, 0(a0) ; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw a7, 4(a0) ; RV32I-NEXT: sw a7, 4(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: lshr128: ; RV64I-LABEL: lshr128:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a3, a2, -64 ; RV64I-NEXT: addi a3, a2, -64
; RV64I-NEXT: bltz a3, .LBB6_2 ; RV64I-NEXT: bltz a3, .LBB6_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: srl a0, a1, a3 ; RV64I-NEXT: srl a0, a1, a3
Show All 12 Lines; RV64I-NEXT: ret
ret i128 %1 ret i128 %1
} }
define i128 @ashr128(i128 %a, i128 %b) nounwind { define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: ashr128: ; RV32I-LABEL: ashr128:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a2, 0(a2) ; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw t2, 8(a1) ; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw t5, 12(a1) ; RV32I-NEXT: lw a4, 12(a1)
; RV32I-NEXT: li a6, 64 ; RV32I-NEXT: li a3, 64
; RV32I-NEXT: sub t1, a6, a2 ; RV32I-NEXT: sub t1, a3, a2
; RV32I-NEXT: li a3, 32 ; RV32I-NEXT: li a6, 32
; RV32I-NEXT: sub t6, a3, a2 ; RV32I-NEXT: sub t2, a6, a2
; RV32I-NEXT: li t4, 31 ; RV32I-NEXT: li t4, 31
; RV32I-NEXT: bltz t6, .LBB7_2 ; RV32I-NEXT: bltz t2, .LBB7_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sll s0, t2, t6 ; RV32I-NEXT: sll s0, a5, t2
; RV32I-NEXT: j .LBB7_3 ; RV32I-NEXT: j .LBB7_3
; RV32I-NEXT: .LBB7_2: ; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: sll a3, t5, t1 ; RV32I-NEXT: sll a6, a4, t1
; RV32I-NEXT: sub a4, t4, t1 ; RV32I-NEXT: sub a7, t4, t1
; RV32I-NEXT: srli a5, t2, 1 ; RV32I-NEXT: srli t0, a5, 1
; RV32I-NEXT: srl a4, a5, a4 ; RV32I-NEXT: srl a7, t0, a7
; RV32I-NEXT: or s0, a3, a4 ; RV32I-NEXT: or s0, a6, a7
; RV32I-NEXT: .LBB7_3: ; RV32I-NEXT: .LBB7_3:
; RV32I-NEXT: lw a5, 4(a1) ; RV32I-NEXT: lw t6, 4(a1)
; RV32I-NEXT: addi a3, a2, -32 ; RV32I-NEXT: addi a6, a2, -32
; RV32I-NEXT: bgez a3, .LBB7_5 ; RV32I-NEXT: bgez a6, .LBB7_5
; RV32I-NEXT: # %bb.4: ; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: srl a4, a5, a2 ; RV32I-NEXT: srl a7, t6, a2
; RV32I-NEXT: or s0, s0, a4 ; RV32I-NEXT: or s0, s0, a7
; RV32I-NEXT: .LBB7_5: ; RV32I-NEXT: .LBB7_5:
; RV32I-NEXT: addi t3, a2, -64 ; RV32I-NEXT: addi t3, a2, -64
; RV32I-NEXT: addi a4, a2, -96 ; RV32I-NEXT: addi t5, a2, -96
; RV32I-NEXT: srai a7, t5, 31 ; RV32I-NEXT: srai a7, a4, 31
; RV32I-NEXT: bltz a4, .LBB7_7 ; RV32I-NEXT: bltz t5, .LBB7_7
; RV32I-NEXT: # %bb.6: ; RV32I-NEXT: # %bb.6:
; RV32I-NEXT: mv t0, a7 ; RV32I-NEXT: mv t0, a7
; RV32I-NEXT: bgeu a2, a6, .LBB7_8 ; RV32I-NEXT: bgeu a2, a3, .LBB7_8
; RV32I-NEXT: j .LBB7_9 ; RV32I-NEXT: j .LBB7_9
; RV32I-NEXT: .LBB7_7: ; RV32I-NEXT: .LBB7_7:
; RV32I-NEXT: sra t0, t5, t3 ; RV32I-NEXT: sra t0, a4, t3
; RV32I-NEXT: bltu a2, a6, .LBB7_9 ; RV32I-NEXT: bltu a2, a3, .LBB7_9
; RV32I-NEXT: .LBB7_8: ; RV32I-NEXT: .LBB7_8:
; RV32I-NEXT: mv s0, t0 ; RV32I-NEXT: mv s0, t0
; RV32I-NEXT: .LBB7_9: ; RV32I-NEXT: .LBB7_9:
; RV32I-NEXT: mv t0, a5 ; RV32I-NEXT: mv t0, t6
; RV32I-NEXT: beqz a2, .LBB7_11 ; RV32I-NEXT: beqz a2, .LBB7_11
; RV32I-NEXT: # %bb.10: ; RV32I-NEXT: # %bb.10:
; RV32I-NEXT: mv t0, s0 ; RV32I-NEXT: mv t0, s0
; RV32I-NEXT: .LBB7_11: ; RV32I-NEXT: .LBB7_11:
; RV32I-NEXT: lw s1, 0(a1) ; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sub t4, t4, a2 ; RV32I-NEXT: sub t4, t4, a2
; RV32I-NEXT: bltz a3, .LBB7_13 ; RV32I-NEXT: bltz a6, .LBB7_13
; RV32I-NEXT: # %bb.12: ; RV32I-NEXT: # %bb.12:
; RV32I-NEXT: srl a5, a5, a3 ; RV32I-NEXT: srl t6, t6, a6
; RV32I-NEXT: bltz t6, .LBB7_14 ; RV32I-NEXT: bltz t2, .LBB7_14
; RV32I-NEXT: j .LBB7_15 ; RV32I-NEXT: j .LBB7_15
; RV32I-NEXT: .LBB7_13: ; RV32I-NEXT: .LBB7_13:
; RV32I-NEXT: srl s0, s1, a2 ; RV32I-NEXT: srl s0, a1, a2
; RV32I-NEXT: slli a5, a5, 1 ; RV32I-NEXT: slli t6, t6, 1
; RV32I-NEXT: sll a5, a5, t4 ; RV32I-NEXT: sll t6, t6, t4
; RV32I-NEXT: or a5, s0, a5 ; RV32I-NEXT: or t6, s0, t6
; RV32I-NEXT: bgez t6, .LBB7_15 ; RV32I-NEXT: bgez t2, .LBB7_15
; RV32I-NEXT: .LBB7_14: ; RV32I-NEXT: .LBB7_14:
; RV32I-NEXT: sll s0, t2, t1 ; RV32I-NEXT: sll t1, a5, t1
; RV32I-NEXT: or a5, a5, s0 ; RV32I-NEXT: or t6, t6, t1
; RV32I-NEXT: .LBB7_15: ; RV32I-NEXT: .LBB7_15:
; RV32I-NEXT: slli s0, t5, 1 ; RV32I-NEXT: slli t1, a4, 1
; RV32I-NEXT: bltz a4, .LBB7_17 ; RV32I-NEXT: bltz t5, .LBB7_17
; RV32I-NEXT: # %bb.16: ; RV32I-NEXT: # %bb.16:
; RV32I-NEXT: sra a4, t5, a4 ; RV32I-NEXT: sra t2, a4, t5
; RV32I-NEXT: bgeu a2, a6, .LBB7_18 ; RV32I-NEXT: bgeu a2, a3, .LBB7_18
; RV32I-NEXT: j .LBB7_19 ; RV32I-NEXT: j .LBB7_19
; RV32I-NEXT: .LBB7_17: ; RV32I-NEXT: .LBB7_17:
; RV32I-NEXT: li a4, 95 ; RV32I-NEXT: li t2, 95
; RV32I-NEXT: sub a4, a4, a2 ; RV32I-NEXT: sub t2, t2, a2
; RV32I-NEXT: sll a4, s0, a4 ; RV32I-NEXT: sll t2, t1, t2
; RV32I-NEXT: srl a1, t2, t3 ; RV32I-NEXT: srl t3, a5, t3
; RV32I-NEXT: or a4, a1, a4 ; RV32I-NEXT: or t2, t3, t2
; RV32I-NEXT: bltu a2, a6, .LBB7_19 ; RV32I-NEXT: bltu a2, a3, .LBB7_19
; RV32I-NEXT: .LBB7_18: ; RV32I-NEXT: .LBB7_18:
; RV32I-NEXT: mv a5, a4 ; RV32I-NEXT: mv t6, t2
; RV32I-NEXT: .LBB7_19: ; RV32I-NEXT: .LBB7_19:
; RV32I-NEXT: bnez a2, .LBB7_22 ; RV32I-NEXT: bnez a2, .LBB7_22
; RV32I-NEXT: # %bb.20: ; RV32I-NEXT: # %bb.20:
; RV32I-NEXT: bltz a3, .LBB7_23 ; RV32I-NEXT: bltz a6, .LBB7_23
; RV32I-NEXT: .LBB7_21: ; RV32I-NEXT: .LBB7_21:
; RV32I-NEXT: sra a4, t5, a3 ; RV32I-NEXT: sra a5, a4, a6
; RV32I-NEXT: bgeu a2, a6, .LBB7_24 ; RV32I-NEXT: bgeu a2, a3, .LBB7_24
; RV32I-NEXT: j .LBB7_25 ; RV32I-NEXT: j .LBB7_25
; RV32I-NEXT: .LBB7_22: ; RV32I-NEXT: .LBB7_22:
; RV32I-NEXT: mv s1, a5 ; RV32I-NEXT: mv a1, t6
; RV32I-NEXT: bgez a3, .LBB7_21 ; RV32I-NEXT: bgez a6, .LBB7_21
; RV32I-NEXT: .LBB7_23: ; RV32I-NEXT: .LBB7_23:
; RV32I-NEXT: srl a1, t2, a2 ; RV32I-NEXT: srl a5, a5, a2
; RV32I-NEXT: sll a4, s0, t4 ; RV32I-NEXT: sll t1, t1, t4
; RV32I-NEXT: or a4, a1, a4 ; RV32I-NEXT: or a5, a5, t1
; RV32I-NEXT: bltu a2, a6, .LBB7_25 ; RV32I-NEXT: bltu a2, a3, .LBB7_25
; RV32I-NEXT: .LBB7_24: ; RV32I-NEXT: .LBB7_24:
; RV32I-NEXT: mv a4, a7 ; RV32I-NEXT: mv a5, a7
; RV32I-NEXT: .LBB7_25: ; RV32I-NEXT: .LBB7_25:
; RV32I-NEXT: bltz a3, .LBB7_27 ; RV32I-NEXT: bltz a6, .LBB7_27
; RV32I-NEXT: # %bb.26: ; RV32I-NEXT: # %bb.26:
; RV32I-NEXT: mv a3, a7 ; RV32I-NEXT: mv a4, a7
; RV32I-NEXT: bgeu a2, a6, .LBB7_28 ; RV32I-NEXT: bgeu a2, a3, .LBB7_28
; RV32I-NEXT: j .LBB7_29 ; RV32I-NEXT: j .LBB7_29
; RV32I-NEXT: .LBB7_27: ; RV32I-NEXT: .LBB7_27:
; RV32I-NEXT: sra a3, t5, a2 ; RV32I-NEXT: sra a4, a4, a2
; RV32I-NEXT: bltu a2, a6, .LBB7_29 ; RV32I-NEXT: bltu a2, a3, .LBB7_29
; RV32I-NEXT: .LBB7_28: ; RV32I-NEXT: .LBB7_28:
; RV32I-NEXT: mv a3, a7 ; RV32I-NEXT: mv a4, a7
; RV32I-NEXT: .LBB7_29: ; RV32I-NEXT: .LBB7_29:
; RV32I-NEXT: sw a3, 12(a0) ; RV32I-NEXT: sw a4, 12(a0)
; RV32I-NEXT: sw a4, 8(a0) ; RV32I-NEXT: sw a5, 8(a0)
; RV32I-NEXT: sw s1, 0(a0) ; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw t0, 4(a0) ; RV32I-NEXT: sw t0, 4(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: ashr128: ; RV64I-LABEL: ashr128:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a3, a2, -64 ; RV64I-NEXT: addi a3, a2, -64
; RV64I-NEXT: bltz a3, .LBB7_2 ; RV64I-NEXT: bltz a3, .LBB7_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: ret ; RV64I-NEXT: ret
%1 = ashr i128 %a, %b %1 = ashr i128 %a, %b
ret i128 %1 ret i128 %1
} }
define i128 @shl128(i128 %a, i128 %b) nounwind { define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: shl128: ; RV32I-LABEL: shl128:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw a2, 0(a2) ; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw t0, 4(a1) ; RV32I-NEXT: lw a5, 4(a1)
; RV32I-NEXT: lw t4, 0(a1) ; RV32I-NEXT: lw a4, 0(a1)
; RV32I-NEXT: li a6, 64 ; RV32I-NEXT: li a3, 64
; RV32I-NEXT: sub t0, a3, a2
; RV32I-NEXT: li a6, 32
; RV32I-NEXT: sub t1, a6, a2 ; RV32I-NEXT: sub t1, a6, a2
; RV32I-NEXT: li a3, 32
; RV32I-NEXT: sub t5, a3, a2
; RV32I-NEXT: li t2, 31 ; RV32I-NEXT: li t2, 31
; RV32I-NEXT: bltz t5, .LBB8_2 ; RV32I-NEXT: bltz t1, .LBB8_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srl a3, t0, t5 ; RV32I-NEXT: srl t6, a5, t1
; RV32I-NEXT: j .LBB8_3 ; RV32I-NEXT: j .LBB8_3
; RV32I-NEXT: .LBB8_2: ; RV32I-NEXT: .LBB8_2:
; RV32I-NEXT: srl a3, t4, t1 ; RV32I-NEXT: srl a6, a4, t0
; RV32I-NEXT: sub a4, t2, t1 ; RV32I-NEXT: sub a7, t2, t0
; RV32I-NEXT: slli a5, t0, 1 ; RV32I-NEXT: slli t3, a5, 1
; RV32I-NEXT: sll a4, a5, a4 ; RV32I-NEXT: sll a7, t3, a7
; RV32I-NEXT: or a3, a3, a4 ; RV32I-NEXT: or t6, a6, a7
; RV32I-NEXT: .LBB8_3: ; RV32I-NEXT: .LBB8_3:
; RV32I-NEXT: lw a5, 8(a1) ; RV32I-NEXT: lw t5, 8(a1)
; RV32I-NEXT: addi t6, a2, -32 ; RV32I-NEXT: addi a6, a2, -32
; RV32I-NEXT: bgez t6, .LBB8_5 ; RV32I-NEXT: bgez a6, .LBB8_5
; RV32I-NEXT: # %bb.4: ; RV32I-NEXT: # %bb.4:
; RV32I-NEXT: sll a4, a5, a2 ; RV32I-NEXT: sll a7, t5, a2
; RV32I-NEXT: or a3, a3, a4 ; RV32I-NEXT: or t6, t6, a7
; RV32I-NEXT: .LBB8_5: ; RV32I-NEXT: .LBB8_5:
; RV32I-NEXT: addi a4, a2, -96 ; RV32I-NEXT: addi t4, a2, -96
; RV32I-NEXT: addi t3, a2, -64 ; RV32I-NEXT: addi t3, a2, -64
; RV32I-NEXT: bltz a4, .LBB8_7 ; RV32I-NEXT: bltz t4, .LBB8_7
; RV32I-NEXT: # %bb.6: ; RV32I-NEXT: # %bb.6:
; RV32I-NEXT: li a7, 0 ; RV32I-NEXT: li a7, 0
; RV32I-NEXT: bgeu a2, a6, .LBB8_8 ; RV32I-NEXT: bgeu a2, a3, .LBB8_8
; RV32I-NEXT: j .LBB8_9 ; RV32I-NEXT: j .LBB8_9
; RV32I-NEXT: .LBB8_7: ; RV32I-NEXT: .LBB8_7:
; RV32I-NEXT: sll a7, t4, t3 ; RV32I-NEXT: sll a7, a4, t3
; RV32I-NEXT: bltu a2, a6, .LBB8_9 ; RV32I-NEXT: bltu a2, a3, .LBB8_9
; RV32I-NEXT: .LBB8_8: ; RV32I-NEXT: .LBB8_8:
; RV32I-NEXT: mv a3, a7 ; RV32I-NEXT: mv t6, a7
; RV32I-NEXT: .LBB8_9: ; RV32I-NEXT: .LBB8_9:
; RV32I-NEXT: mv a7, a5 ; RV32I-NEXT: mv a7, t5
; RV32I-NEXT: beqz a2, .LBB8_11 ; RV32I-NEXT: beqz a2, .LBB8_11
; RV32I-NEXT: # %bb.10: ; RV32I-NEXT: # %bb.10:
; RV32I-NEXT: mv a7, a3 ; RV32I-NEXT: mv a7, t6
; RV32I-NEXT: .LBB8_11: ; RV32I-NEXT: .LBB8_11:
; RV32I-NEXT: lw s0, 12(a1) ; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: sub t2, t2, a2 ; RV32I-NEXT: sub t2, t2, a2
; RV32I-NEXT: bltz t6, .LBB8_13 ; RV32I-NEXT: bltz a6, .LBB8_13
; RV32I-NEXT: # %bb.12: ; RV32I-NEXT: # %bb.12:
; RV32I-NEXT: sll a5, a5, t6 ; RV32I-NEXT: sll t5, t5, a6
; RV32I-NEXT: bltz t5, .LBB8_14 ; RV32I-NEXT: bltz t1, .LBB8_14
; RV32I-NEXT: j .LBB8_15 ; RV32I-NEXT: j .LBB8_15
; RV32I-NEXT: .LBB8_13: ; RV32I-NEXT: .LBB8_13:
; RV32I-NEXT: sll a3, s0, a2 ; RV32I-NEXT: sll t6, a1, a2
; RV32I-NEXT: srli a5, a5, 1 ; RV32I-NEXT: srli t5, t5, 1
; RV32I-NEXT: srl a5, a5, t2 ; RV32I-NEXT: srl t5, t5, t2
; RV32I-NEXT: or a5, a3, a5 ; RV32I-NEXT: or t5, t6, t5
; RV32I-NEXT: bgez t5, .LBB8_15 ; RV32I-NEXT: bgez t1, .LBB8_15
; RV32I-NEXT: .LBB8_14: ; RV32I-NEXT: .LBB8_14:
; RV32I-NEXT: srl a3, t0, t1 ; RV32I-NEXT: srl t0, a5, t0
; RV32I-NEXT: or a5, a5, a3 ; RV32I-NEXT: or t5, t5, t0
; RV32I-NEXT: .LBB8_15: ; RV32I-NEXT: .LBB8_15:
; RV32I-NEXT: srli a3, t4, 1 ; RV32I-NEXT: srli t0, a4, 1
; RV32I-NEXT: bltz a4, .LBB8_17 ; RV32I-NEXT: bltz t4, .LBB8_17
; RV32I-NEXT: # %bb.16: ; RV32I-NEXT: # %bb.16:
; RV32I-NEXT: sll a4, t4, a4 ; RV32I-NEXT: sll t1, a4, t4
; RV32I-NEXT: bgeu a2, a6, .LBB8_18 ; RV32I-NEXT: bgeu a2, a3, .LBB8_18
; RV32I-NEXT: j .LBB8_19 ; RV32I-NEXT: j .LBB8_19
; RV32I-NEXT: .LBB8_17: ; RV32I-NEXT: .LBB8_17:
; RV32I-NEXT: li a4, 95 ; RV32I-NEXT: li t1, 95
; RV32I-NEXT: sub a4, a4, a2 ; RV32I-NEXT: sub t1, t1, a2
; RV32I-NEXT: srl a4, a3, a4 ; RV32I-NEXT: srl t1, t0, t1
; RV32I-NEXT: sll a1, t0, t3 ; RV32I-NEXT: sll t3, a5, t3
; RV32I-NEXT: or a4, a1, a4 ; RV32I-NEXT: or t1, t3, t1
; RV32I-NEXT: bltu a2, a6, .LBB8_19 ; RV32I-NEXT: bltu a2, a3, .LBB8_19
; RV32I-NEXT: .LBB8_18: ; RV32I-NEXT: .LBB8_18:
; RV32I-NEXT: mv a5, a4 ; RV32I-NEXT: mv t5, t1
; RV32I-NEXT: .LBB8_19: ; RV32I-NEXT: .LBB8_19:
; RV32I-NEXT: bnez a2, .LBB8_22 ; RV32I-NEXT: bnez a2, .LBB8_22
; RV32I-NEXT: # %bb.20: ; RV32I-NEXT: # %bb.20:
; RV32I-NEXT: bltz t6, .LBB8_23 ; RV32I-NEXT: bltz a6, .LBB8_23
; RV32I-NEXT: .LBB8_21: ; RV32I-NEXT: .LBB8_21:
; RV32I-NEXT: sll a3, t4, t6 ; RV32I-NEXT: sll a5, a4, a6
; RV32I-NEXT: bgeu a2, a6, .LBB8_24 ; RV32I-NEXT: bgeu a2, a3, .LBB8_24
; RV32I-NEXT: j .LBB8_25 ; RV32I-NEXT: j .LBB8_25
; RV32I-NEXT: .LBB8_22: ; RV32I-NEXT: .LBB8_22:
; RV32I-NEXT: mv s0, a5 ; RV32I-NEXT: mv a1, t5
; RV32I-NEXT: bgez t6, .LBB8_21 ; RV32I-NEXT: bgez a6, .LBB8_21
; RV32I-NEXT: .LBB8_23: ; RV32I-NEXT: .LBB8_23:
; RV32I-NEXT: sll a1, t0, a2 ; RV32I-NEXT: sll a5, a5, a2
; RV32I-NEXT: srl a3, a3, t2 ; RV32I-NEXT: srl t0, t0, t2
; RV32I-NEXT: or a3, a1, a3 ; RV32I-NEXT: or a5, a5, t0
; RV32I-NEXT: bltu a2, a6, .LBB8_25 ; RV32I-NEXT: bltu a2, a3, .LBB8_25
; RV32I-NEXT: .LBB8_24: ; RV32I-NEXT: .LBB8_24:
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a5, 0
; RV32I-NEXT: .LBB8_25: ; RV32I-NEXT: .LBB8_25:
; RV32I-NEXT: bltz t6, .LBB8_27 ; RV32I-NEXT: bltz a6, .LBB8_27
; RV32I-NEXT: # %bb.26: ; RV32I-NEXT: # %bb.26:
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: bgeu a2, a6, .LBB8_28 ; RV32I-NEXT: bgeu a2, a3, .LBB8_28
; RV32I-NEXT: j .LBB8_29 ; RV32I-NEXT: j .LBB8_29
; RV32I-NEXT: .LBB8_27: ; RV32I-NEXT: .LBB8_27:
; RV32I-NEXT: sll a4, t4, a2 ; RV32I-NEXT: sll a4, a4, a2
; RV32I-NEXT: bltu a2, a6, .LBB8_29 ; RV32I-NEXT: bltu a2, a3, .LBB8_29
; RV32I-NEXT: .LBB8_28: ; RV32I-NEXT: .LBB8_28:
; RV32I-NEXT: li a4, 0 ; RV32I-NEXT: li a4, 0
; RV32I-NEXT: .LBB8_29: ; RV32I-NEXT: .LBB8_29:
; RV32I-NEXT: sw a4, 0(a0) ; RV32I-NEXT: sw a4, 0(a0)
; RV32I-NEXT: sw a3, 4(a0) ; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: sw s0, 12(a0) ; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: sw a7, 8(a0) ; RV32I-NEXT: sw a7, 8(a0)
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: shl128: ; RV64I-LABEL: shl128:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi a3, a2, -64 ; RV64I-NEXT: addi a3, a2, -64
; RV64I-NEXT: bltz a3, .LBB8_2 ; RV64I-NEXT: bltz a3, .LBB8_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: sll a1, a0, a3 ; RV64I-NEXT: sll a1, a0, a3
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%res = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b) %res = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b)
ret i64 %res ret i64 %res
} }
define i128 @fshr128_minsize(i128 %a, i128 %b) minsize nounwind { define i128 @fshr128_minsize(i128 %a, i128 %b) minsize nounwind {
; RV32I-LABEL: fshr128_minsize: ; RV32I-LABEL: fshr128_minsize:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: lw t2, 8(a1) ; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw a3, 0(a1) ; RV32I-NEXT: lw t2, 0(a1)
; RV32I-NEXT: lw a2, 0(a2) ; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a7, 4(a1) ; RV32I-NEXT: lw a7, 4(a1)
; RV32I-NEXT: lw t1, 12(a1) ; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: andi a1, a2, 64 ; RV32I-NEXT: andi t1, a2, 64
; RV32I-NEXT: mv a5, a7 ; RV32I-NEXT: mv t0, a7
; RV32I-NEXT: mv a6, a3 ; RV32I-NEXT: mv a4, t2
; RV32I-NEXT: beqz a1, .LBB10_2 ; RV32I-NEXT: beqz t1, .LBB10_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a5, t1 ; RV32I-NEXT: mv t0, a1
; RV32I-NEXT: mv a6, t2 ; RV32I-NEXT: mv a4, a3
; RV32I-NEXT: .LBB10_2: ; RV32I-NEXT: .LBB10_2:
; RV32I-NEXT: andi a4, a2, 32 ; RV32I-NEXT: andi a6, a2, 32
; RV32I-NEXT: mv t0, a6 ; RV32I-NEXT: mv a5, a4
; RV32I-NEXT: bnez a4, .LBB10_13 ; RV32I-NEXT: bnez a6, .LBB10_13
; RV32I-NEXT: # %bb.3: ; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: bnez a1, .LBB10_14 ; RV32I-NEXT: bnez t1, .LBB10_14
; RV32I-NEXT: .LBB10_4: ; RV32I-NEXT: .LBB10_4:
; RV32I-NEXT: beqz a4, .LBB10_6 ; RV32I-NEXT: beqz a6, .LBB10_6
; RV32I-NEXT: .LBB10_5: ; RV32I-NEXT: .LBB10_5:
; RV32I-NEXT: mv a5, t2 ; RV32I-NEXT: mv t0, a3
; RV32I-NEXT: .LBB10_6: ; RV32I-NEXT: .LBB10_6:
; RV32I-NEXT: slli t3, a5, 1 ; RV32I-NEXT: slli t3, t0, 1
; RV32I-NEXT: not a3, a2 ; RV32I-NEXT: not t2, a2
; RV32I-NEXT: beqz a1, .LBB10_8 ; RV32I-NEXT: beqz t1, .LBB10_8
; RV32I-NEXT: # %bb.7: ; RV32I-NEXT: # %bb.7:
; RV32I-NEXT: mv t1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB10_8: ; RV32I-NEXT: .LBB10_8:
; RV32I-NEXT: srl a7, t0, a2 ; RV32I-NEXT: srl a7, a5, a2
; RV32I-NEXT: sll a1, t3, a3 ; RV32I-NEXT: sll t1, t3, t2
; RV32I-NEXT: srl a5, a5, a2 ; RV32I-NEXT: srl t0, t0, a2
; RV32I-NEXT: beqz a4, .LBB10_10 ; RV32I-NEXT: beqz a6, .LBB10_10
; RV32I-NEXT: # %bb.9: ; RV32I-NEXT: # %bb.9:
; RV32I-NEXT: mv t2, t1 ; RV32I-NEXT: mv a3, a1
; RV32I-NEXT: .LBB10_10: ; RV32I-NEXT: .LBB10_10:
; RV32I-NEXT: or a7, a1, a7 ; RV32I-NEXT: or a7, t1, a7
; RV32I-NEXT: slli a1, t2, 1 ; RV32I-NEXT: slli t1, a3, 1
; RV32I-NEXT: sll a1, a1, a3 ; RV32I-NEXT: sll t1, t1, t2
; RV32I-NEXT: or a5, a1, a5 ; RV32I-NEXT: or t0, t1, t0
; RV32I-NEXT: srl a1, t2, a2 ; RV32I-NEXT: srl a3, a3, a2
; RV32I-NEXT: beqz a4, .LBB10_12 ; RV32I-NEXT: beqz a6, .LBB10_12
; RV32I-NEXT: # %bb.11: ; RV32I-NEXT: # %bb.11:
; RV32I-NEXT: mv t1, a6 ; RV32I-NEXT: mv a1, a4
; RV32I-NEXT: .LBB10_12: ; RV32I-NEXT: .LBB10_12:
; RV32I-NEXT: slli a4, t1, 1 ; RV32I-NEXT: slli a4, a1, 1
; RV32I-NEXT: sll a4, a4, a3 ; RV32I-NEXT: sll a4, a4, t2
; RV32I-NEXT: or a1, a4, a1 ; RV32I-NEXT: or a3, a4, a3
; RV32I-NEXT: srl a2, t1, a2 ; RV32I-NEXT: srl a1, a1, a2
; RV32I-NEXT: slli a4, t0, 1 ; RV32I-NEXT: slli a2, a5, 1
; RV32I-NEXT: sll a3, a4, a3 ; RV32I-NEXT: sll a2, a2, t2
; RV32I-NEXT: or a2, a3, a2 ; RV32I-NEXT: or a1, a2, a1
; RV32I-NEXT: sw a2, 12(a0) ; RV32I-NEXT: sw a1, 12(a0)
; RV32I-NEXT: sw a1, 8(a0) ; RV32I-NEXT: sw a3, 8(a0)
; RV32I-NEXT: sw a5, 4(a0) ; RV32I-NEXT: sw t0, 4(a0)
; RV32I-NEXT: sw a7, 0(a0) ; RV32I-NEXT: sw a7, 0(a0)
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; RV32I-NEXT: .LBB10_13: ; RV32I-NEXT: .LBB10_13:
; RV32I-NEXT: mv t0, a5 ; RV32I-NEXT: mv a5, t0
; RV32I-NEXT: beqz a1, .LBB10_4 ; RV32I-NEXT: beqz t1, .LBB10_4
; RV32I-NEXT: .LBB10_14: ; RV32I-NEXT: .LBB10_14:
; RV32I-NEXT: mv t2, a3 ; RV32I-NEXT: mv a3, t2
; RV32I-NEXT: bnez a4, .LBB10_5 ; RV32I-NEXT: bnez a6, .LBB10_5
; RV32I-NEXT: j .LBB10_6 ; RV32I-NEXT: j .LBB10_6
; ;
; RV64I-LABEL: fshr128_minsize: ; RV64I-LABEL: fshr128_minsize:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: andi a4, a2, 64 ; RV64I-NEXT: andi a4, a2, 64
; RV64I-NEXT: mv a3, a0 ; RV64I-NEXT: mv a3, a0
; RV64I-NEXT: beqz a4, .LBB10_2 ; RV64I-NEXT: beqz a4, .LBB10_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
Show All 19 Lines

llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

Show First 20 Lines • Show All 300 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s6, 0(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32-NEXT: mv s0, a0 ; RV32-NEXT: mv s0, a0
; RV32-NEXT: lw a0, 4(a0) ; RV32-NEXT: lw a0, 4(a0)
; RV32-NEXT: lbu a1, 12(s0) ; RV32-NEXT: lbu a1, 12(s0)
; RV32-NEXT: lw a2, 8(s0) ; RV32-NEXT: lw a2, 8(s0)
; RV32-NEXT: andi a3, a0, 1 ; RV32-NEXT: andi a3, a0, 1
; RV32-NEXT: neg s2, a3 ; RV32-NEXT: neg s1, a3
; RV32-NEXT: slli a3, a1, 30 ; RV32-NEXT: slli a3, a1, 30
; RV32-NEXT: srli a4, a2, 2 ; RV32-NEXT: srli a4, a2, 2
; RV32-NEXT: or s3, a4, a3 ; RV32-NEXT: or s2, a4, a3
; RV32-NEXT: srli a1, a1, 2 ; RV32-NEXT: srli a1, a1, 2
; RV32-NEXT: andi a1, a1, 1 ; RV32-NEXT: andi a1, a1, 1
; RV32-NEXT: neg s1, a1 ; RV32-NEXT: neg s3, a1
; RV32-NEXT: slli a1, a2, 31 ; RV32-NEXT: slli a1, a2, 31
; RV32-NEXT: srli a0, a0, 1 ; RV32-NEXT: srli a0, a0, 1
; RV32-NEXT: or a0, a0, a1 ; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: lw s4, 0(s0) ; RV32-NEXT: lw s4, 0(s0)
; RV32-NEXT: srli a1, a2, 1 ; RV32-NEXT: srli a1, a2, 1
; RV32-NEXT: andi a1, a1, 1 ; RV32-NEXT: andi a1, a1, 1
; RV32-NEXT: neg a1, a1 ; RV32-NEXT: neg a1, a1
; RV32-NEXT: li a2, 7 ; RV32-NEXT: li a2, 7
; RV32-NEXT: li a3, 0 ; RV32-NEXT: li a3, 0
; RV32-NEXT: call __moddi3@plt ; RV32-NEXT: call __moddi3@plt
; RV32-NEXT: mv s5, a0 ; RV32-NEXT: mv s5, a0
; RV32-NEXT: mv s6, a1 ; RV32-NEXT: mv s6, a1
; RV32-NEXT: li a2, -5 ; RV32-NEXT: li a2, -5
; RV32-NEXT: li a3, -1 ; RV32-NEXT: li a3, -1
; RV32-NEXT: mv a0, s3 ; RV32-NEXT: mv a0, s2
; RV32-NEXT: mv a1, s1 ; RV32-NEXT: mv a1, s3
; RV32-NEXT: call __moddi3@plt ; RV32-NEXT: call __moddi3@plt
; RV32-NEXT: mv s1, a0 ; RV32-NEXT: mv s2, a0
; RV32-NEXT: mv s3, a1 ; RV32-NEXT: mv s3, a1
; RV32-NEXT: li a2, 6 ; RV32-NEXT: li a2, 6
; RV32-NEXT: mv a0, s4 ; RV32-NEXT: mv a0, s4
; RV32-NEXT: mv a1, s2 ; RV32-NEXT: mv a1, s1
; RV32-NEXT: li a3, 0 ; RV32-NEXT: li a3, 0
; RV32-NEXT: call __moddi3@plt ; RV32-NEXT: call __moddi3@plt
; RV32-NEXT: xori a2, s1, 2 ; RV32-NEXT: xori a2, s2, 2
; RV32-NEXT: or a2, a2, s3 ; RV32-NEXT: or a2, a2, s3
; RV32-NEXT: snez a2, a2 ; RV32-NEXT: snez a2, a2
; RV32-NEXT: xori a3, s5, 1 ; RV32-NEXT: xori a3, s5, 1
; RV32-NEXT: or a3, a3, s6 ; RV32-NEXT: or a3, a3, s6
; RV32-NEXT: snez a3, a3 ; RV32-NEXT: snez a3, a3
; RV32-NEXT: or a0, a0, a1 ; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: snez a0, a0 ; RV32-NEXT: snez a0, a0
; RV32-NEXT: neg a1, a3 ; RV32-NEXT: neg a1, a3
▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 Lines
; RV32M-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32M-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32M-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32M-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32M-NEXT: sw s6, 0(sp) # 4-byte Folded Spill ; RV32M-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32M-NEXT: mv s0, a0 ; RV32M-NEXT: mv s0, a0
; RV32M-NEXT: lw a0, 4(a0) ; RV32M-NEXT: lw a0, 4(a0)
; RV32M-NEXT: lbu a1, 12(s0) ; RV32M-NEXT: lbu a1, 12(s0)
; RV32M-NEXT: lw a2, 8(s0) ; RV32M-NEXT: lw a2, 8(s0)
; RV32M-NEXT: andi a3, a0, 1 ; RV32M-NEXT: andi a3, a0, 1
; RV32M-NEXT: neg s2, a3 ; RV32M-NEXT: neg s1, a3
; RV32M-NEXT: slli a3, a1, 30 ; RV32M-NEXT: slli a3, a1, 30
; RV32M-NEXT: srli a4, a2, 2 ; RV32M-NEXT: srli a4, a2, 2
; RV32M-NEXT: or s3, a4, a3 ; RV32M-NEXT: or s2, a4, a3
; RV32M-NEXT: srli a1, a1, 2 ; RV32M-NEXT: srli a1, a1, 2
; RV32M-NEXT: andi a1, a1, 1 ; RV32M-NEXT: andi a1, a1, 1
; RV32M-NEXT: neg s1, a1 ; RV32M-NEXT: neg s3, a1
; RV32M-NEXT: slli a1, a2, 31 ; RV32M-NEXT: slli a1, a2, 31
; RV32M-NEXT: srli a0, a0, 1 ; RV32M-NEXT: srli a0, a0, 1
; RV32M-NEXT: or a0, a0, a1 ; RV32M-NEXT: or a0, a0, a1
; RV32M-NEXT: lw s4, 0(s0) ; RV32M-NEXT: lw s4, 0(s0)
; RV32M-NEXT: srli a1, a2, 1 ; RV32M-NEXT: srli a1, a2, 1
; RV32M-NEXT: andi a1, a1, 1 ; RV32M-NEXT: andi a1, a1, 1
; RV32M-NEXT: neg a1, a1 ; RV32M-NEXT: neg a1, a1
; RV32M-NEXT: li a2, 7 ; RV32M-NEXT: li a2, 7
; RV32M-NEXT: li a3, 0 ; RV32M-NEXT: li a3, 0
; RV32M-NEXT: call __moddi3@plt ; RV32M-NEXT: call __moddi3@plt
; RV32M-NEXT: mv s5, a0 ; RV32M-NEXT: mv s5, a0
; RV32M-NEXT: mv s6, a1 ; RV32M-NEXT: mv s6, a1
; RV32M-NEXT: li a2, -5 ; RV32M-NEXT: li a2, -5
; RV32M-NEXT: li a3, -1 ; RV32M-NEXT: li a3, -1
; RV32M-NEXT: mv a0, s3 ; RV32M-NEXT: mv a0, s2
; RV32M-NEXT: mv a1, s1 ; RV32M-NEXT: mv a1, s3
; RV32M-NEXT: call __moddi3@plt ; RV32M-NEXT: call __moddi3@plt
; RV32M-NEXT: mv s1, a0 ; RV32M-NEXT: mv s2, a0
; RV32M-NEXT: mv s3, a1 ; RV32M-NEXT: mv s3, a1
; RV32M-NEXT: li a2, 6 ; RV32M-NEXT: li a2, 6
; RV32M-NEXT: mv a0, s4 ; RV32M-NEXT: mv a0, s4
; RV32M-NEXT: mv a1, s2 ; RV32M-NEXT: mv a1, s1
; RV32M-NEXT: li a3, 0 ; RV32M-NEXT: li a3, 0
; RV32M-NEXT: call __moddi3@plt ; RV32M-NEXT: call __moddi3@plt
; RV32M-NEXT: xori a2, s1, 2 ; RV32M-NEXT: xori a2, s2, 2
; RV32M-NEXT: or a2, a2, s3 ; RV32M-NEXT: or a2, a2, s3
; RV32M-NEXT: snez a2, a2 ; RV32M-NEXT: snez a2, a2
; RV32M-NEXT: xori a3, s5, 1 ; RV32M-NEXT: xori a3, s5, 1
; RV32M-NEXT: or a3, a3, s6 ; RV32M-NEXT: or a3, a3, s6
; RV32M-NEXT: snez a3, a3 ; RV32M-NEXT: snez a3, a3
; RV32M-NEXT: or a0, a0, a1 ; RV32M-NEXT: or a0, a0, a1
; RV32M-NEXT: snez a0, a0 ; RV32M-NEXT: snez a0, a0
; RV32M-NEXT: neg a1, a3 ; RV32M-NEXT: neg a1, a3
▲ Show 20 Lines • Show All 293 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/srem-vector-lkk.ll

Show All 12 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: lh s0, 12(a1)
; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh s1, 8(a1)
; RV32I-NEXT: lh s3, 8(a1) ; RV32I-NEXT: lh s2, 4(a1)
; RV32I-NEXT: lh s0, 4(a1)
; RV32I-NEXT: lh a2, 0(a1) ; RV32I-NEXT: lh a2, 0(a1)
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: li a1, -124 ; RV32I-NEXT: li a1, -124
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: li a1, 98 ; RV32I-NEXT: li a1, 98
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: li a1, -1003 ; RV32I-NEXT: li a1, -1003
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: sh a0, 6(s1) ; RV32I-NEXT: sh a0, 6(s3)
; RV32I-NEXT: sh s0, 4(s1) ; RV32I-NEXT: sh s1, 4(s3)
; RV32I-NEXT: sh s5, 2(s1) ; RV32I-NEXT: sh s2, 2(s3)
; RV32I-NEXT: sh s4, 0(s1) ; RV32I-NEXT: sh s4, 0(s3)
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_srem_vec_1: ; RV32IM-LABEL: fold_srem_vec_1:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a6, 12(a1) ; RV32IM-NEXT: lh a2, 12(a1)
; RV32IM-NEXT: lh a3, 8(a1) ; RV32IM-NEXT: lh a3, 8(a1)
; RV32IM-NEXT: lh a4, 0(a1) ; RV32IM-NEXT: lh a4, 0(a1)
; RV32IM-NEXT: lh a1, 4(a1) ; RV32IM-NEXT: lh a1, 4(a1)
; RV32IM-NEXT: lui a5, 706409 ; RV32IM-NEXT: lui a5, 706409
; RV32IM-NEXT: addi a5, a5, 389 ; RV32IM-NEXT: addi a5, a5, 389
; RV32IM-NEXT: mulh a5, a4, a5 ; RV32IM-NEXT: mulh a5, a4, a5
; RV32IM-NEXT: add a5, a5, a4 ; RV32IM-NEXT: add a5, a5, a4
; RV32IM-NEXT: srli a2, a5, 31 ; RV32IM-NEXT: srli a6, a5, 31
; RV32IM-NEXT: srli a5, a5, 6 ; RV32IM-NEXT: srli a5, a5, 6
; RV32IM-NEXT: add a2, a5, a2 ; RV32IM-NEXT: add a5, a5, a6
; RV32IM-NEXT: li a5, 95 ; RV32IM-NEXT: li a6, 95
; RV32IM-NEXT: mul a2, a2, a5 ; RV32IM-NEXT: mul a5, a5, a6
; RV32IM-NEXT: sub a2, a4, a2 ; RV32IM-NEXT: sub a4, a4, a5
; RV32IM-NEXT: lui a4, 507375 ; RV32IM-NEXT: lui a5, 507375
; RV32IM-NEXT: addi a4, a4, 1981 ; RV32IM-NEXT: addi a5, a5, 1981
; RV32IM-NEXT: mulh a4, a1, a4 ; RV32IM-NEXT: mulh a5, a1, a5
; RV32IM-NEXT: sub a4, a4, a1 ; RV32IM-NEXT: sub a5, a5, a1
; RV32IM-NEXT: srli a5, a4, 31 ; RV32IM-NEXT: srli a6, a5, 31
; RV32IM-NEXT: srli a4, a4, 6 ; RV32IM-NEXT: srli a5, a5, 6
; RV32IM-NEXT: add a4, a4, a5 ; RV32IM-NEXT: add a5, a5, a6
; RV32IM-NEXT: li a5, -124 ; RV32IM-NEXT: li a6, -124
; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: mul a5, a5, a6
; RV32IM-NEXT: sub a1, a1, a4 ; RV32IM-NEXT: sub a1, a1, a5
; RV32IM-NEXT: lui a4, 342392 ; RV32IM-NEXT: lui a5, 342392
; RV32IM-NEXT: addi a4, a4, 669 ; RV32IM-NEXT: addi a5, a5, 669
; RV32IM-NEXT: mulh a4, a3, a4 ; RV32IM-NEXT: mulh a5, a3, a5
; RV32IM-NEXT: srli a5, a4, 31 ; RV32IM-NEXT: srli a6, a5, 31
; RV32IM-NEXT: srli a4, a4, 5 ; RV32IM-NEXT: srli a5, a5, 5
; RV32IM-NEXT: add a4, a4, a5 ; RV32IM-NEXT: add a5, a5, a6
; RV32IM-NEXT: li a5, 98 ; RV32IM-NEXT: li a6, 98
; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: mul a5, a5, a6
; RV32IM-NEXT: sub a3, a3, a4 ; RV32IM-NEXT: sub a3, a3, a5
; RV32IM-NEXT: lui a4, 780943 ; RV32IM-NEXT: lui a5, 780943
; RV32IM-NEXT: addi a4, a4, 1809 ; RV32IM-NEXT: addi a5, a5, 1809
; RV32IM-NEXT: mulh a4, a6, a4 ; RV32IM-NEXT: mulh a5, a2, a5
; RV32IM-NEXT: srli a5, a4, 31 ; RV32IM-NEXT: srli a6, a5, 31
; RV32IM-NEXT: srli a4, a4, 8 ; RV32IM-NEXT: srli a5, a5, 8
; RV32IM-NEXT: add a4, a4, a5 ; RV32IM-NEXT: add a5, a5, a6
; RV32IM-NEXT: li a5, -1003 ; RV32IM-NEXT: li a6, -1003
; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: mul a5, a5, a6
; RV32IM-NEXT: sub a4, a6, a4 ; RV32IM-NEXT: sub a2, a2, a5
; RV32IM-NEXT: sh a4, 6(a0) ; RV32IM-NEXT: sh a2, 6(a0)
; RV32IM-NEXT: sh a3, 4(a0) ; RV32IM-NEXT: sh a3, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh a2, 0(a0) ; RV32IM-NEXT: sh a4, 0(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_srem_vec_1: ; RV64I-LABEL: fold_srem_vec_1:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lh s0, 24(a1)
; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh s1, 16(a1)
; RV64I-NEXT: lh s3, 16(a1) ; RV64I-NEXT: lh s2, 8(a1)
; RV64I-NEXT: lh s0, 8(a1)
; RV64I-NEXT: lh a2, 0(a1) ; RV64I-NEXT: lh a2, 0(a1)
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: li a1, -124 ; RV64I-NEXT: li a1, -124
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: li a1, 98 ; RV64I-NEXT: li a1, 98
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: li a1, -1003 ; RV64I-NEXT: li a1, -1003
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: sh a0, 6(s1) ; RV64I-NEXT: sh a0, 6(s3)
; RV64I-NEXT: sh s0, 4(s1) ; RV64I-NEXT: sh s1, 4(s3)
; RV64I-NEXT: sh s5, 2(s1) ; RV64I-NEXT: sh s2, 2(s3)
; RV64I-NEXT: sh s4, 0(s1) ; RV64I-NEXT: sh s4, 0(s3)
; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_srem_vec_1: ; RV64IM-LABEL: fold_srem_vec_1:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a2, 0(a1) ; RV64IM-NEXT: lh a2, 0(a1)
; RV64IM-NEXT: lui a3, %hi(.LCPI0_0) ; RV64IM-NEXT: lui a3, %hi(.LCPI0_0)
; RV64IM-NEXT: ld a3, %lo(.LCPI0_0)(a3) ; RV64IM-NEXT: ld a3, %lo(.LCPI0_0)(a3)
; RV64IM-NEXT: lh a6, 24(a1) ; RV64IM-NEXT: lh a4, 24(a1)
; RV64IM-NEXT: lh a7, 16(a1) ; RV64IM-NEXT: lh a5, 16(a1)
; RV64IM-NEXT: lh a1, 8(a1) ; RV64IM-NEXT: lh a1, 8(a1)
; RV64IM-NEXT: mulh a3, a2, a3 ; RV64IM-NEXT: mulh a3, a2, a3
; RV64IM-NEXT: add a3, a3, a2 ; RV64IM-NEXT: add a3, a3, a2
; RV64IM-NEXT: srli a4, a3, 63 ; RV64IM-NEXT: srli a6, a3, 63
; RV64IM-NEXT: srli a3, a3, 6 ; RV64IM-NEXT: srli a3, a3, 6
; RV64IM-NEXT: addw a3, a3, a4 ; RV64IM-NEXT: addw a3, a3, a6
; RV64IM-NEXT: lui a4, %hi(.LCPI0_1) ; RV64IM-NEXT: lui a6, %hi(.LCPI0_1)
; RV64IM-NEXT: ld a4, %lo(.LCPI0_1)(a4) ; RV64IM-NEXT: ld a6, %lo(.LCPI0_1)(a6)
; RV64IM-NEXT: li a5, 95 ; RV64IM-NEXT: li a7, 95
; RV64IM-NEXT: mulw a3, a3, a5 ; RV64IM-NEXT: mulw a3, a3, a7
; RV64IM-NEXT: subw a2, a2, a3 ; RV64IM-NEXT: subw a2, a2, a3
; RV64IM-NEXT: mulh a3, a1, a4 ; RV64IM-NEXT: mulh a3, a1, a6
; RV64IM-NEXT: sub a3, a3, a1 ; RV64IM-NEXT: sub a3, a3, a1
; RV64IM-NEXT: srli a4, a3, 63 ; RV64IM-NEXT: srli a6, a3, 63
; RV64IM-NEXT: srli a3, a3, 6 ; RV64IM-NEXT: srli a3, a3, 6
; RV64IM-NEXT: addw a3, a3, a4 ; RV64IM-NEXT: addw a3, a3, a6
; RV64IM-NEXT: lui a4, %hi(.LCPI0_2) ; RV64IM-NEXT: lui a6, %hi(.LCPI0_2)
; RV64IM-NEXT: ld a4, %lo(.LCPI0_2)(a4) ; RV64IM-NEXT: ld a6, %lo(.LCPI0_2)(a6)
; RV64IM-NEXT: li a5, -124 ; RV64IM-NEXT: li a7, -124
; RV64IM-NEXT: mulw a3, a3, a5 ; RV64IM-NEXT: mulw a3, a3, a7
; RV64IM-NEXT: subw a1, a1, a3 ; RV64IM-NEXT: subw a1, a1, a3
; RV64IM-NEXT: mulh a3, a7, a4 ; RV64IM-NEXT: mulh a3, a5, a6
; RV64IM-NEXT: srli a4, a3, 63 ; RV64IM-NEXT: srli a6, a3, 63
; RV64IM-NEXT: srli a3, a3, 5 ; RV64IM-NEXT: srli a3, a3, 5
; RV64IM-NEXT: addw a3, a3, a4 ; RV64IM-NEXT: addw a3, a3, a6
; RV64IM-NEXT: lui a4, %hi(.LCPI0_3) ; RV64IM-NEXT: lui a6, %hi(.LCPI0_3)
; RV64IM-NEXT: ld a4, %lo(.LCPI0_3)(a4) ; RV64IM-NEXT: ld a6, %lo(.LCPI0_3)(a6)
; RV64IM-NEXT: li a5, 98 ; RV64IM-NEXT: li a7, 98
; RV64IM-NEXT: mulw a3, a3, a5 ; RV64IM-NEXT: mulw a3, a3, a7
; RV64IM-NEXT: subw a3, a7, a3 ; RV64IM-NEXT: subw a3, a5, a3
; RV64IM-NEXT: mulh a4, a6, a4 ; RV64IM-NEXT: mulh a5, a4, a6
; RV64IM-NEXT: srli a5, a4, 63 ; RV64IM-NEXT: srli a6, a5, 63
; RV64IM-NEXT: srli a4, a4, 7 ; RV64IM-NEXT: srli a5, a5, 7
; RV64IM-NEXT: addw a4, a4, a5 ; RV64IM-NEXT: addw a5, a5, a6
; RV64IM-NEXT: li a5, -1003 ; RV64IM-NEXT: li a6, -1003
; RV64IM-NEXT: mulw a4, a4, a5 ; RV64IM-NEXT: mulw a5, a5, a6
; RV64IM-NEXT: subw a4, a6, a4 ; RV64IM-NEXT: subw a4, a4, a5
; RV64IM-NEXT: sh a4, 6(a0) ; RV64IM-NEXT: sh a4, 6(a0)
; RV64IM-NEXT: sh a3, 4(a0) ; RV64IM-NEXT: sh a3, 4(a0)
; RV64IM-NEXT: sh a1, 2(a0) ; RV64IM-NEXT: sh a1, 2(a0)
; RV64IM-NEXT: sh a2, 0(a0) ; RV64IM-NEXT: sh a2, 0(a0)
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003> %1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003>
ret <4 x i16> %1 ret <4 x i16> %1
} }
define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) nounwind { define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) nounwind {
; RV32I-LABEL: fold_srem_vec_2: ; RV32I-LABEL: fold_srem_vec_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: lh s0, 12(a1)
; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh s1, 8(a1)
; RV32I-NEXT: lh s3, 8(a1) ; RV32I-NEXT: lh s2, 4(a1)
; RV32I-NEXT: lh s0, 4(a1)
; RV32I-NEXT: lh a2, 0(a1) ; RV32I-NEXT: lh a2, 0(a1)
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: sh a0, 6(s1) ; RV32I-NEXT: sh a0, 6(s3)
; RV32I-NEXT: sh s0, 4(s1) ; RV32I-NEXT: sh s1, 4(s3)
; RV32I-NEXT: sh s5, 2(s1) ; RV32I-NEXT: sh s2, 2(s3)
; RV32I-NEXT: sh s4, 0(s1) ; RV32I-NEXT: sh s4, 0(s3)
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_srem_vec_2: ; RV32IM-LABEL: fold_srem_vec_2:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a6, 12(a1) ; RV32IM-NEXT: lh a2, 12(a1)
; RV32IM-NEXT: lh a3, 8(a1) ; RV32IM-NEXT: lh a3, 8(a1)
; RV32IM-NEXT: lh a4, 0(a1) ; RV32IM-NEXT: lh a4, 0(a1)
; RV32IM-NEXT: lh a1, 4(a1) ; RV32IM-NEXT: lh a1, 4(a1)
; RV32IM-NEXT: lui a5, 706409 ; RV32IM-NEXT: lui a5, 706409
; RV32IM-NEXT: addi a5, a5, 389 ; RV32IM-NEXT: addi a5, a5, 389
; RV32IM-NEXT: mulh a2, a4, a5 ; RV32IM-NEXT: mulh a6, a4, a5
; RV32IM-NEXT: add a2, a2, a4 ; RV32IM-NEXT: add a6, a6, a4
; RV32IM-NEXT: srli a7, a2, 31 ; RV32IM-NEXT: srli a7, a6, 31
; RV32IM-NEXT: srli a2, a2, 6 ; RV32IM-NEXT: srli a6, a6, 6
; RV32IM-NEXT: add a2, a2, a7 ; RV32IM-NEXT: add a6, a6, a7
; RV32IM-NEXT: li a7, 95 ; RV32IM-NEXT: li a7, 95
; RV32IM-NEXT: mul a2, a2, a7 ; RV32IM-NEXT: mul a6, a6, a7
; RV32IM-NEXT: sub t0, a4, a2 ; RV32IM-NEXT: sub a4, a4, a6
; RV32IM-NEXT: mulh a4, a1, a5 ; RV32IM-NEXT: mulh a6, a1, a5
; RV32IM-NEXT: add a4, a4, a1 ; RV32IM-NEXT: add a6, a6, a1
; RV32IM-NEXT: srli a2, a4, 31 ; RV32IM-NEXT: srli t0, a6, 31
; RV32IM-NEXT: srli a4, a4, 6 ; RV32IM-NEXT: srli a6, a6, 6
; RV32IM-NEXT: add a2, a4, a2 ; RV32IM-NEXT: add a6, a6, t0
; RV32IM-NEXT: mul a2, a2, a7 ; RV32IM-NEXT: mul a6, a6, a7
; RV32IM-NEXT: sub a1, a1, a2 ; RV32IM-NEXT: sub a1, a1, a6
; RV32IM-NEXT: mulh a2, a3, a5 ; RV32IM-NEXT: mulh a6, a3, a5
; RV32IM-NEXT: add a2, a2, a3 ; RV32IM-NEXT: add a6, a6, a3
; RV32IM-NEXT: srli a4, a2, 31 ; RV32IM-NEXT: srli t0, a6, 31
; RV32IM-NEXT: srli a2, a2, 6 ; RV32IM-NEXT: srli a6, a6, 6
; RV32IM-NEXT: add a2, a2, a4 ; RV32IM-NEXT: add a6, a6, t0
; RV32IM-NEXT: mul a2, a2, a7 ; RV32IM-NEXT: mul a6, a6, a7
; RV32IM-NEXT: sub a2, a3, a2 ; RV32IM-NEXT: sub a3, a3, a6
; RV32IM-NEXT: mulh a3, a6, a5 ; RV32IM-NEXT: mulh a5, a2, a5
; RV32IM-NEXT: add a3, a3, a6 ; RV32IM-NEXT: add a5, a5, a2
; RV32IM-NEXT: srli a4, a3, 31 ; RV32IM-NEXT: srli a6, a5, 31
; RV32IM-NEXT: srli a3, a3, 6 ; RV32IM-NEXT: srli a5, a5, 6
; RV32IM-NEXT: add a3, a3, a4 ; RV32IM-NEXT: add a5, a5, a6
; RV32IM-NEXT: mul a3, a3, a7 ; RV32IM-NEXT: mul a5, a5, a7
; RV32IM-NEXT: sub a3, a6, a3 ; RV32IM-NEXT: sub a2, a2, a5
; RV32IM-NEXT: sh a3, 6(a0) ; RV32IM-NEXT: sh a2, 6(a0)
; RV32IM-NEXT: sh a2, 4(a0) ; RV32IM-NEXT: sh a3, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh t0, 0(a0) ; RV32IM-NEXT: sh a4, 0(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_srem_vec_2: ; RV64I-LABEL: fold_srem_vec_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lh s0, 24(a1)
; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh s1, 16(a1)
; RV64I-NEXT: lh s3, 16(a1) ; RV64I-NEXT: lh s2, 8(a1)
; RV64I-NEXT: lh s0, 8(a1)
; RV64I-NEXT: lh a2, 0(a1) ; RV64I-NEXT: lh a2, 0(a1)
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: sh a0, 6(s1) ; RV64I-NEXT: sh a0, 6(s3)
; RV64I-NEXT: sh s0, 4(s1) ; RV64I-NEXT: sh s1, 4(s3)
; RV64I-NEXT: sh s5, 2(s1) ; RV64I-NEXT: sh s2, 2(s3)
; RV64I-NEXT: sh s4, 0(s1) ; RV64I-NEXT: sh s4, 0(s3)
; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_srem_vec_2: ; RV64IM-LABEL: fold_srem_vec_2:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a2, 0(a1) ; RV64IM-NEXT: lh a2, 0(a1)
; RV64IM-NEXT: lui a3, %hi(.LCPI1_0) ; RV64IM-NEXT: lui a3, %hi(.LCPI1_0)
; RV64IM-NEXT: ld a3, %lo(.LCPI1_0)(a3) ; RV64IM-NEXT: ld a3, %lo(.LCPI1_0)(a3)
; RV64IM-NEXT: lh a6, 24(a1) ; RV64IM-NEXT: lh a4, 24(a1)
; RV64IM-NEXT: lh a5, 16(a1) ; RV64IM-NEXT: lh a5, 16(a1)
; RV64IM-NEXT: lh a1, 8(a1) ; RV64IM-NEXT: lh a1, 8(a1)
; RV64IM-NEXT: mulh a4, a2, a3 ; RV64IM-NEXT: mulh a6, a2, a3
; RV64IM-NEXT: add a4, a4, a2 ; RV64IM-NEXT: add a6, a6, a2
; RV64IM-NEXT: srli a7, a4, 63 ; RV64IM-NEXT: srli a7, a6, 63
; RV64IM-NEXT: srli a4, a4, 6 ; RV64IM-NEXT: srli a6, a6, 6
; RV64IM-NEXT: addw a4, a4, a7 ; RV64IM-NEXT: addw a6, a6, a7
; RV64IM-NEXT: li a7, 95 ; RV64IM-NEXT: li a7, 95
; RV64IM-NEXT: mulw a4, a4, a7 ; RV64IM-NEXT: mulw a6, a6, a7
; RV64IM-NEXT: subw t0, a2, a4 ; RV64IM-NEXT: subw a2, a2, a6
; RV64IM-NEXT: mulh a4, a1, a3 ; RV64IM-NEXT: mulh a6, a1, a3
; RV64IM-NEXT: add a4, a4, a1 ; RV64IM-NEXT: add a6, a6, a1
; RV64IM-NEXT: srli a2, a4, 63 ; RV64IM-NEXT: srli t0, a6, 63
; RV64IM-NEXT: srli a4, a4, 6 ; RV64IM-NEXT: srli a6, a6, 6
; RV64IM-NEXT: addw a2, a4, a2 ; RV64IM-NEXT: addw a6, a6, t0
; RV64IM-NEXT: mulw a2, a2, a7 ; RV64IM-NEXT: mulw a6, a6, a7
; RV64IM-NEXT: subw a1, a1, a2 ; RV64IM-NEXT: subw a1, a1, a6
; RV64IM-NEXT: mulh a2, a5, a3 ; RV64IM-NEXT: mulh a6, a5, a3
; RV64IM-NEXT: add a2, a2, a5 ; RV64IM-NEXT: add a6, a6, a5
; RV64IM-NEXT: srli a4, a2, 63 ; RV64IM-NEXT: srli t0, a6, 63
; RV64IM-NEXT: srli a2, a2, 6 ; RV64IM-NEXT: srli a6, a6, 6
; RV64IM-NEXT: addw a2, a2, a4 ; RV64IM-NEXT: addw a6, a6, t0
; RV64IM-NEXT: mulw a2, a2, a7 ; RV64IM-NEXT: mulw a6, a6, a7
; RV64IM-NEXT: subw a2, a5, a2 ; RV64IM-NEXT: subw a5, a5, a6
; RV64IM-NEXT: mulh a3, a6, a3 ; RV64IM-NEXT: mulh a3, a4, a3
; RV64IM-NEXT: add a3, a3, a6 ; RV64IM-NEXT: add a3, a3, a4
; RV64IM-NEXT: srli a4, a3, 63 ; RV64IM-NEXT: srli a6, a3, 63
; RV64IM-NEXT: srli a3, a3, 6 ; RV64IM-NEXT: srli a3, a3, 6
; RV64IM-NEXT: addw a3, a3, a4 ; RV64IM-NEXT: addw a3, a3, a6
; RV64IM-NEXT: mulw a3, a3, a7 ; RV64IM-NEXT: mulw a3, a3, a7
; RV64IM-NEXT: subw a3, a6, a3 ; RV64IM-NEXT: subw a3, a4, a3
; RV64IM-NEXT: sh a3, 6(a0) ; RV64IM-NEXT: sh a3, 6(a0)
; RV64IM-NEXT: sh a2, 4(a0) ; RV64IM-NEXT: sh a5, 4(a0)
; RV64IM-NEXT: sh a1, 2(a0) ; RV64IM-NEXT: sh a1, 2(a0)
; RV64IM-NEXT: sh t0, 0(a0) ; RV64IM-NEXT: sh a2, 0(a0)
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if we can combine srem with sdiv. ; Don't fold if we can combine srem with sdiv.
define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) nounwind { define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) nounwind {
; RV32I-LABEL: combine_srem_sdiv: ; RV32I-LABEL: combine_srem_sdiv:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s9, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: lh s1, 0(a1)
; RV32I-NEXT: lh s2, 0(a1) ; RV32I-NEXT: lh s2, 4(a1)
; RV32I-NEXT: lh s3, 4(a1) ; RV32I-NEXT: lh s3, 8(a1)
; RV32I-NEXT: lh s4, 8(a1) ; RV32I-NEXT: lh s4, 12(a1)
; RV32I-NEXT: lh s1, 12(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: mv s7, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s8, a0 ; RV32I-NEXT: mv s8, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __divsi3@plt
; RV32I-NEXT: mv s9, a0
; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: call __divsi3@plt ; RV32I-NEXT: call __divsi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __divsi3@plt ; RV32I-NEXT: call __divsi3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __divsi3@plt ; RV32I-NEXT: call __divsi3@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __divsi3@plt
; RV32I-NEXT: add a0, s8, a0 ; RV32I-NEXT: add a0, s8, a0
; RV32I-NEXT: add a1, s7, s1 ; RV32I-NEXT: add a1, s7, s2
; RV32I-NEXT: add a2, s6, s4 ; RV32I-NEXT: add a2, s6, s3
; RV32I-NEXT: add a3, s5, s9 ; RV32I-NEXT: add a3, s5, s4
; RV32I-NEXT: sh a3, 6(s0) ; RV32I-NEXT: sh a3, 6(s0)
; RV32I-NEXT: sh a2, 4(s0) ; RV32I-NEXT: sh a2, 4(s0)
; RV32I-NEXT: sh a1, 2(s0) ; RV32I-NEXT: sh a1, 2(s0)
; RV32I-NEXT: sh a0, 0(s0) ; RV32I-NEXT: sh a0, 0(s0)
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: combine_srem_sdiv: ; RV32IM-LABEL: combine_srem_sdiv:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a6, 0(a1) ; RV32IM-NEXT: lh a2, 0(a1)
; RV32IM-NEXT: lh a3, 4(a1) ; RV32IM-NEXT: lh a3, 4(a1)
; RV32IM-NEXT: lh a4, 12(a1) ; RV32IM-NEXT: lh a4, 12(a1)
; RV32IM-NEXT: lh a1, 8(a1) ; RV32IM-NEXT: lh a1, 8(a1)
; RV32IM-NEXT: lui a5, 706409 ; RV32IM-NEXT: lui a5, 706409
; RV32IM-NEXT: addi a5, a5, 389 ; RV32IM-NEXT: addi a5, a5, 389
; RV32IM-NEXT: mulh a2, a4, a5 ; RV32IM-NEXT: mulh a6, a4, a5
; RV32IM-NEXT: add a2, a2, a4 ; RV32IM-NEXT: add a6, a6, a4
; RV32IM-NEXT: srli a7, a2, 31 ; RV32IM-NEXT: srli a7, a6, 31
; RV32IM-NEXT: srai a2, a2, 6 ; RV32IM-NEXT: srai a6, a6, 6
; RV32IM-NEXT: add t0, a2, a7 ; RV32IM-NEXT: add a6, a6, a7
; RV32IM-NEXT: li a7, 95 ; RV32IM-NEXT: li a7, 95
; RV32IM-NEXT: mul a2, t0, a7 ; RV32IM-NEXT: mul t0, a6, a7
; RV32IM-NEXT: sub t1, a4, a2 ; RV32IM-NEXT: sub a4, a4, t0
; RV32IM-NEXT: mulh a4, a1, a5 ; RV32IM-NEXT: mulh t0, a1, a5
; RV32IM-NEXT: add a4, a4, a1 ; RV32IM-NEXT: add t0, t0, a1
; RV32IM-NEXT: srli a2, a4, 31 ; RV32IM-NEXT: srli t1, t0, 31
; RV32IM-NEXT: srai a4, a4, 6 ; RV32IM-NEXT: srai t0, t0, 6
; RV32IM-NEXT: add a2, a4, a2 ; RV32IM-NEXT: add t0, t0, t1
; RV32IM-NEXT: mul a4, a2, a7 ; RV32IM-NEXT: mul t1, t0, a7
; RV32IM-NEXT: sub t2, a1, a4 ; RV32IM-NEXT: sub a1, a1, t1
; RV32IM-NEXT: mulh a4, a3, a5 ; RV32IM-NEXT: mulh t1, a3, a5
; RV32IM-NEXT: add a4, a4, a3 ; RV32IM-NEXT: add t1, t1, a3
; RV32IM-NEXT: srli a1, a4, 31 ; RV32IM-NEXT: srli t2, t1, 31
; RV32IM-NEXT: srai a4, a4, 6 ; RV32IM-NEXT: srai t1, t1, 6
; RV32IM-NEXT: add a1, a4, a1 ; RV32IM-NEXT: add t1, t1, t2
; RV32IM-NEXT: mul a4, a1, a7 ; RV32IM-NEXT: mul t2, t1, a7
; RV32IM-NEXT: sub a3, a3, a4 ; RV32IM-NEXT: sub a3, a3, t2
; RV32IM-NEXT: mulh a4, a6, a5 ; RV32IM-NEXT: mulh a5, a2, a5
; RV32IM-NEXT: add a5, a5, a2
; RV32IM-NEXT: srli t2, a5, 31
; RV32IM-NEXT: srai a5, a5, 6
; RV32IM-NEXT: add a5, a5, t2
; RV32IM-NEXT: mul a7, a5, a7
; RV32IM-NEXT: sub a2, a2, a7
; RV32IM-NEXT: add a2, a2, a5
; RV32IM-NEXT: add a3, a3, t1
; RV32IM-NEXT: add a1, a1, t0
; RV32IM-NEXT: add a4, a4, a6 ; RV32IM-NEXT: add a4, a4, a6
; RV32IM-NEXT: srli a5, a4, 31 ; RV32IM-NEXT: sh a4, 6(a0)
; RV32IM-NEXT: srai a4, a4, 6 ; RV32IM-NEXT: sh a1, 4(a0)
; RV32IM-NEXT: add a4, a4, a5 ; RV32IM-NEXT: sh a3, 2(a0)
; RV32IM-NEXT: mul a5, a4, a7 ; RV32IM-NEXT: sh a2, 0(a0)
; RV32IM-NEXT: sub a5, a6, a5
; RV32IM-NEXT: add a4, a5, a4
; RV32IM-NEXT: add a1, a3, a1
; RV32IM-NEXT: add a2, t2, a2
; RV32IM-NEXT: add a3, t1, t0
; RV32IM-NEXT: sh a3, 6(a0)
; RV32IM-NEXT: sh a2, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh a4, 0(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: combine_srem_sdiv: ; RV64I-LABEL: combine_srem_sdiv:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -96 ; RV64I-NEXT: addi sp, sp, -80
; RV64I-NEXT: sd ra, 88(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 80(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 72(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 64(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 56(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 48(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s4, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s5, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s5, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s6, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s6, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s7, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s7, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s8, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s8, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s9, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lh s1, 0(a1)
; RV64I-NEXT: lh s2, 0(a1) ; RV64I-NEXT: lh s2, 8(a1)
; RV64I-NEXT: lh s3, 8(a1) ; RV64I-NEXT: lh s3, 16(a1)
; RV64I-NEXT: lh s4, 16(a1) ; RV64I-NEXT: lh s4, 24(a1)
; RV64I-NEXT: lh s1, 24(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s5, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s6, a0 ; RV64I-NEXT: mv s6, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s7, a0 ; RV64I-NEXT: mv s7, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s8, a0 ; RV64I-NEXT: mv s8, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: mv s9, a0
; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: call __divdi3@plt ; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __divdi3@plt ; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __divdi3@plt ; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: addw a0, s8, a0 ; RV64I-NEXT: addw a0, s8, a0
; RV64I-NEXT: addw a1, s7, s1 ; RV64I-NEXT: addw a1, s7, s2
; RV64I-NEXT: addw a2, s6, s4 ; RV64I-NEXT: addw a2, s6, s3
; RV64I-NEXT: addw a3, s5, s9 ; RV64I-NEXT: addw a3, s5, s4
; RV64I-NEXT: sh a3, 6(s0) ; RV64I-NEXT: sh a3, 6(s0)
; RV64I-NEXT: sh a2, 4(s0) ; RV64I-NEXT: sh a2, 4(s0)
; RV64I-NEXT: sh a1, 2(s0) ; RV64I-NEXT: sh a1, 2(s0)
; RV64I-NEXT: sh a0, 0(s0) ; RV64I-NEXT: sh a0, 0(s0)
; RV64I-NEXT: ld ra, 88(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 80(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 72(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 64(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 48(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 56(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 48(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s4, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s5, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s5, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s6, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s6, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s7, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s7, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s8, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s8, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s9, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 80
; RV64I-NEXT: addi sp, sp, 96
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: combine_srem_sdiv: ; RV64IM-LABEL: combine_srem_sdiv:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a2, 24(a1) ; RV64IM-NEXT: lh a2, 24(a1)
; RV64IM-NEXT: lui a3, %hi(.LCPI2_0) ; RV64IM-NEXT: lui a3, %hi(.LCPI2_0)
; RV64IM-NEXT: ld a3, %lo(.LCPI2_0)(a3) ; RV64IM-NEXT: ld a3, %lo(.LCPI2_0)(a3)
; RV64IM-NEXT: lh a6, 0(a1) ; RV64IM-NEXT: lh a4, 0(a1)
; RV64IM-NEXT: lh a5, 8(a1) ; RV64IM-NEXT: lh a5, 8(a1)
; RV64IM-NEXT: lh a1, 16(a1) ; RV64IM-NEXT: lh a1, 16(a1)
; RV64IM-NEXT: mulh a4, a2, a3 ; RV64IM-NEXT: mulh a6, a2, a3
; RV64IM-NEXT: add a4, a4, a2 ; RV64IM-NEXT: add a6, a6, a2
; RV64IM-NEXT: srli a7, a4, 63 ; RV64IM-NEXT: srli a7, a6, 63
; RV64IM-NEXT: srai a4, a4, 6 ; RV64IM-NEXT: srai a6, a6, 6
; RV64IM-NEXT: addw t0, a4, a7 ; RV64IM-NEXT: addw a6, a6, a7
; RV64IM-NEXT: li a7, 95 ; RV64IM-NEXT: li a7, 95
; RV64IM-NEXT: mulw a4, t0, a7 ; RV64IM-NEXT: mulw t0, a6, a7
; RV64IM-NEXT: subw t1, a2, a4 ; RV64IM-NEXT: subw a2, a2, t0
; RV64IM-NEXT: mulh a4, a1, a3 ; RV64IM-NEXT: mulh t0, a1, a3
; RV64IM-NEXT: add a4, a4, a1 ; RV64IM-NEXT: add t0, t0, a1
; RV64IM-NEXT: srli a2, a4, 63 ; RV64IM-NEXT: srli t1, t0, 63
; RV64IM-NEXT: srai a4, a4, 6 ; RV64IM-NEXT: srai t0, t0, 6
; RV64IM-NEXT: addw a2, a4, a2 ; RV64IM-NEXT: addw t0, t0, t1
; RV64IM-NEXT: mulw a4, a2, a7 ; RV64IM-NEXT: mulw t1, t0, a7
; RV64IM-NEXT: subw t2, a1, a4 ; RV64IM-NEXT: subw a1, a1, t1
; RV64IM-NEXT: mulh a4, a5, a3 ; RV64IM-NEXT: mulh t1, a5, a3
; RV64IM-NEXT: add a4, a4, a5 ; RV64IM-NEXT: add t1, t1, a5
; RV64IM-NEXT: srli a1, a4, 63 ; RV64IM-NEXT: srli t2, t1, 63
; RV64IM-NEXT: srai a4, a4, 6 ; RV64IM-NEXT: srai t1, t1, 6
; RV64IM-NEXT: addw a1, a4, a1 ; RV64IM-NEXT: addw t1, t1, t2
; RV64IM-NEXT: mulw a4, a1, a7 ; RV64IM-NEXT: mulw t2, t1, a7
; RV64IM-NEXT: subw a4, a5, a4 ; RV64IM-NEXT: subw a5, a5, t2
; RV64IM-NEXT: mulh a3, a6, a3 ; RV64IM-NEXT: mulh a3, a4, a3
; RV64IM-NEXT: add a3, a3, a6 ; RV64IM-NEXT: add a3, a3, a4
; RV64IM-NEXT: srli a5, a3, 63 ; RV64IM-NEXT: srli t2, a3, 63
; RV64IM-NEXT: srai a3, a3, 6 ; RV64IM-NEXT: srai a3, a3, 6
; RV64IM-NEXT: addw a3, a3, a5 ; RV64IM-NEXT: addw a3, a3, t2
; RV64IM-NEXT: mulw a5, a3, a7 ; RV64IM-NEXT: mulw a7, a3, a7
; RV64IM-NEXT: subw a5, a6, a5 ; RV64IM-NEXT: subw a4, a4, a7
; RV64IM-NEXT: addw a3, a5, a3 ; RV64IM-NEXT: addw a3, a4, a3
; RV64IM-NEXT: addw a1, a4, a1 ; RV64IM-NEXT: addw a4, a5, t1
; RV64IM-NEXT: addw a2, t2, a2 ; RV64IM-NEXT: addw a1, a1, t0
; RV64IM-NEXT: addw a4, t1, t0 ; RV64IM-NEXT: addw a2, a2, a6
; RV64IM-NEXT: sh a4, 6(a0) ; RV64IM-NEXT: sh a2, 6(a0)
; RV64IM-NEXT: sh a2, 4(a0) ; RV64IM-NEXT: sh a1, 4(a0)
; RV64IM-NEXT: sh a1, 2(a0) ; RV64IM-NEXT: sh a4, 2(a0)
; RV64IM-NEXT: sh a3, 0(a0) ; RV64IM-NEXT: sh a3, 0(a0)
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
%2 = sdiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %2 = sdiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
%3 = add <4 x i16> %1, %2 %3 = add <4 x i16> %1, %2
ret <4 x i16> %3 ret <4 x i16> %3
} }
Show All 10 Lines
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lh a2, 0(a1) ; RV32I-NEXT: lh a2, 0(a1)
; RV32I-NEXT: lh a0, 12(a1) ; RV32I-NEXT: lh a0, 12(a1)
; RV32I-NEXT: lh a3, 8(a1) ; RV32I-NEXT: lh a3, 8(a1)
; RV32I-NEXT: lh a1, 4(a1) ; RV32I-NEXT: lh a1, 4(a1)
; RV32I-NEXT: srli a4, a2, 26 ; RV32I-NEXT: srli a4, a2, 26
; RV32I-NEXT: add a4, a2, a4 ; RV32I-NEXT: add a4, a2, a4
; RV32I-NEXT: andi a4, a4, -64 ; RV32I-NEXT: andi a4, a4, -64
; RV32I-NEXT: sub s2, a2, a4 ; RV32I-NEXT: sub s1, a2, a4
; RV32I-NEXT: srli a2, a1, 27 ; RV32I-NEXT: srli a2, a1, 27
; RV32I-NEXT: add a2, a1, a2 ; RV32I-NEXT: add a2, a1, a2
; RV32I-NEXT: andi a2, a2, -32 ; RV32I-NEXT: andi a2, a2, -32
; RV32I-NEXT: sub s3, a1, a2 ; RV32I-NEXT: sub s2, a1, a2
; RV32I-NEXT: srli a1, a3, 29 ; RV32I-NEXT: srli a1, a3, 29
; RV32I-NEXT: add a1, a3, a1 ; RV32I-NEXT: add a1, a3, a1
; RV32I-NEXT: andi a1, a1, -8 ; RV32I-NEXT: andi a1, a1, -8
; RV32I-NEXT: sub s1, a3, a1 ; RV32I-NEXT: sub s3, a3, a1
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh a0, 6(s0)
; RV32I-NEXT: sh s1, 4(s0) ; RV32I-NEXT: sh s3, 4(s0)
; RV32I-NEXT: sh s3, 2(s0) ; RV32I-NEXT: sh s2, 2(s0)
; RV32I-NEXT: sh s2, 0(s0) ; RV32I-NEXT: sh s1, 0(s0)
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_srem_power_of_two: ; RV32IM-LABEL: dont_fold_srem_power_of_two:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lh a2, 8(a1) ; RV32IM-NEXT: lh a2, 8(a1)
; RV32IM-NEXT: lh a3, 4(a1) ; RV32IM-NEXT: lh a3, 4(a1)
; RV32IM-NEXT: lh a4, 12(a1) ; RV32IM-NEXT: lh a4, 12(a1)
; RV32IM-NEXT: lh a1, 0(a1) ; RV32IM-NEXT: lh a1, 0(a1)
; RV32IM-NEXT: lui a5, 706409 ; RV32IM-NEXT: lui a5, 706409
; RV32IM-NEXT: addi a5, a5, 389 ; RV32IM-NEXT: addi a5, a5, 389
; RV32IM-NEXT: mulh a5, a4, a5 ; RV32IM-NEXT: mulh a5, a4, a5
; RV32IM-NEXT: add a5, a5, a4 ; RV32IM-NEXT: add a5, a5, a4
; RV32IM-NEXT: srli a6, a5, 31 ; RV32IM-NEXT: srli a6, a5, 31
; RV32IM-NEXT: srli a5, a5, 6 ; RV32IM-NEXT: srli a5, a5, 6
; RV32IM-NEXT: add a6, a5, a6 ; RV32IM-NEXT: add a5, a5, a6
; RV32IM-NEXT: li a5, 95 ; RV32IM-NEXT: li a6, 95
; RV32IM-NEXT: mul a5, a6, a5 ; RV32IM-NEXT: mul a5, a5, a6
; RV32IM-NEXT: sub a4, a4, a5 ; RV32IM-NEXT: sub a4, a4, a5
; RV32IM-NEXT: srli a5, a1, 26 ; RV32IM-NEXT: srli a5, a1, 26
; RV32IM-NEXT: add a5, a1, a5 ; RV32IM-NEXT: add a5, a1, a5
; RV32IM-NEXT: andi a5, a5, -64 ; RV32IM-NEXT: andi a5, a5, -64
; RV32IM-NEXT: sub a1, a1, a5 ; RV32IM-NEXT: sub a1, a1, a5
; RV32IM-NEXT: srli a5, a3, 27 ; RV32IM-NEXT: srli a5, a3, 27
; RV32IM-NEXT: add a5, a3, a5 ; RV32IM-NEXT: add a5, a3, a5
; RV32IM-NEXT: andi a5, a5, -32 ; RV32IM-NEXT: andi a5, a5, -32
Show All 19 Lines
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lh a2, 0(a1) ; RV64I-NEXT: lh a2, 0(a1)
; RV64I-NEXT: lh a0, 24(a1) ; RV64I-NEXT: lh a0, 24(a1)
; RV64I-NEXT: lh a3, 16(a1) ; RV64I-NEXT: lh a3, 16(a1)
; RV64I-NEXT: lh a1, 8(a1) ; RV64I-NEXT: lh a1, 8(a1)
; RV64I-NEXT: srli a4, a2, 58 ; RV64I-NEXT: srli a4, a2, 58
; RV64I-NEXT: add a4, a2, a4 ; RV64I-NEXT: add a4, a2, a4
; RV64I-NEXT: andi a4, a4, -64 ; RV64I-NEXT: andi a4, a4, -64
; RV64I-NEXT: subw s2, a2, a4 ; RV64I-NEXT: subw s1, a2, a4
; RV64I-NEXT: srli a2, a1, 59 ; RV64I-NEXT: srli a2, a1, 59
; RV64I-NEXT: add a2, a1, a2 ; RV64I-NEXT: add a2, a1, a2
; RV64I-NEXT: andi a2, a2, -32 ; RV64I-NEXT: andi a2, a2, -32
; RV64I-NEXT: subw s3, a1, a2 ; RV64I-NEXT: subw s2, a1, a2
; RV64I-NEXT: srli a1, a3, 61 ; RV64I-NEXT: srli a1, a3, 61
; RV64I-NEXT: add a1, a3, a1 ; RV64I-NEXT: add a1, a3, a1
; RV64I-NEXT: andi a1, a1, -8 ; RV64I-NEXT: andi a1, a1, -8
; RV64I-NEXT: subw s1, a3, a1 ; RV64I-NEXT: subw s3, a3, a1
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh a0, 6(s0)
; RV64I-NEXT: sh s1, 4(s0) ; RV64I-NEXT: sh s3, 4(s0)
; RV64I-NEXT: sh s3, 2(s0) ; RV64I-NEXT: sh s2, 2(s0)
; RV64I-NEXT: sh s2, 0(s0) ; RV64I-NEXT: sh s1, 0(s0)
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_srem_power_of_two: ; RV64IM-LABEL: dont_fold_srem_power_of_two:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a2, 24(a1) ; RV64IM-NEXT: lh a2, 24(a1)
; RV64IM-NEXT: lui a3, %hi(.LCPI3_0) ; RV64IM-NEXT: lui a3, %hi(.LCPI3_0)
; RV64IM-NEXT: ld a3, %lo(.LCPI3_0)(a3) ; RV64IM-NEXT: ld a3, %lo(.LCPI3_0)(a3)
; RV64IM-NEXT: lh a4, 16(a1) ; RV64IM-NEXT: lh a4, 16(a1)
; RV64IM-NEXT: lh a5, 8(a1) ; RV64IM-NEXT: lh a5, 8(a1)
; RV64IM-NEXT: lh a1, 0(a1) ; RV64IM-NEXT: lh a1, 0(a1)
; RV64IM-NEXT: mulh a3, a2, a3 ; RV64IM-NEXT: mulh a3, a2, a3
; RV64IM-NEXT: add a3, a3, a2 ; RV64IM-NEXT: add a3, a3, a2
; RV64IM-NEXT: srli a6, a3, 63 ; RV64IM-NEXT: srli a6, a3, 63
; RV64IM-NEXT: srli a3, a3, 6 ; RV64IM-NEXT: srli a3, a3, 6
; RV64IM-NEXT: addw a6, a3, a6 ; RV64IM-NEXT: addw a3, a3, a6
; RV64IM-NEXT: li a3, 95 ; RV64IM-NEXT: li a6, 95
; RV64IM-NEXT: mulw a3, a6, a3 ; RV64IM-NEXT: mulw a3, a3, a6
; RV64IM-NEXT: subw a2, a2, a3 ; RV64IM-NEXT: subw a2, a2, a3
; RV64IM-NEXT: srli a3, a1, 58 ; RV64IM-NEXT: srli a3, a1, 58
; RV64IM-NEXT: add a3, a1, a3 ; RV64IM-NEXT: add a3, a1, a3
; RV64IM-NEXT: andi a3, a3, -64 ; RV64IM-NEXT: andi a3, a3, -64
; RV64IM-NEXT: subw a1, a1, a3 ; RV64IM-NEXT: subw a1, a1, a3
; RV64IM-NEXT: srli a3, a5, 59 ; RV64IM-NEXT: srli a3, a5, 59
; RV64IM-NEXT: add a3, a5, a3 ; RV64IM-NEXT: add a3, a5, a3
; RV64IM-NEXT: andi a3, a3, -32 ; RV64IM-NEXT: andi a3, a3, -32
Show All 16 Lines
; RV32I-LABEL: dont_fold_srem_one: ; RV32I-LABEL: dont_fold_srem_one:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh s0, 12(a1)
; RV32I-NEXT: lh s1, 8(a1) ; RV32I-NEXT: lh s1, 8(a1)
; RV32I-NEXT: lh a2, 4(a1) ; RV32I-NEXT: lh a2, 4(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: li a1, 654 ; RV32I-NEXT: li a1, 654
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: li a1, 23 ; RV32I-NEXT: li a1, 23
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a1, a0, 1327 ; RV32I-NEXT: addi a1, a0, 1327
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh a0, 6(s2)
; RV32I-NEXT: sh s1, 4(s0) ; RV32I-NEXT: sh s1, 4(s2)
; RV32I-NEXT: sh s3, 2(s0) ; RV32I-NEXT: sh s3, 2(s2)
; RV32I-NEXT: sh zero, 0(s0) ; RV32I-NEXT: sh zero, 0(s2)
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; RV64I-LABEL: dont_fold_srem_one: ; RV64I-LABEL: dont_fold_srem_one:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh s0, 24(a1)
; RV64I-NEXT: lh s1, 16(a1) ; RV64I-NEXT: lh s1, 16(a1)
; RV64I-NEXT: lh a2, 8(a1) ; RV64I-NEXT: lh a2, 8(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: li a1, 654 ; RV64I-NEXT: li a1, 654
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: li a1, 23 ; RV64I-NEXT: li a1, 23
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: addiw a1, a0, 1327
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh a0, 6(s2)
; RV64I-NEXT: sh s1, 4(s0) ; RV64I-NEXT: sh s1, 4(s2)
; RV64I-NEXT: sh s3, 2(s0) ; RV64I-NEXT: sh s3, 2(s2)
; RV64I-NEXT: sh zero, 0(s0) ; RV64I-NEXT: sh zero, 0(s2)
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_srem_one: ; RV64IM-LABEL: dont_fold_srem_one:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a2, 16(a1) ; RV64IM-NEXT: lh a2, 16(a1)
; RV64IM-NEXT: lui a3, %hi(.LCPI4_0) ; RV64IM-NEXT: lui a3, %hi(.LCPI4_0)
; RV64IM-NEXT: ld a3, %lo(.LCPI4_0)(a3) ; RV64IM-NEXT: ld a3, %lo(.LCPI4_0)(a3)
; RV64IM-NEXT: lh a6, 24(a1) ; RV64IM-NEXT: lh a4, 24(a1)
; RV64IM-NEXT: lh a1, 8(a1) ; RV64IM-NEXT: lh a1, 8(a1)
; RV64IM-NEXT: mulh a3, a2, a3 ; RV64IM-NEXT: mulh a3, a2, a3
; RV64IM-NEXT: add a3, a3, a2 ; RV64IM-NEXT: add a3, a3, a2
; RV64IM-NEXT: srli a5, a3, 63 ; RV64IM-NEXT: srli a5, a3, 63
; RV64IM-NEXT: srli a3, a3, 4 ; RV64IM-NEXT: srli a3, a3, 4
; RV64IM-NEXT: addw a3, a3, a5 ; RV64IM-NEXT: addw a3, a3, a5
; RV64IM-NEXT: lui a5, %hi(.LCPI4_1) ; RV64IM-NEXT: lui a5, %hi(.LCPI4_1)
; RV64IM-NEXT: ld a5, %lo(.LCPI4_1)(a5) ; RV64IM-NEXT: ld a5, %lo(.LCPI4_1)(a5)
; RV64IM-NEXT: li a4, 23 ; RV64IM-NEXT: li a6, 23
; RV64IM-NEXT: mulw a3, a3, a4 ; RV64IM-NEXT: mulw a3, a3, a6
; RV64IM-NEXT: subw a2, a2, a3 ; RV64IM-NEXT: subw a2, a2, a3
; RV64IM-NEXT: mulh a3, a1, a5 ; RV64IM-NEXT: mulh a3, a1, a5
; RV64IM-NEXT: srli a4, a3, 63 ; RV64IM-NEXT: srli a5, a3, 63
; RV64IM-NEXT: srli a3, a3, 8 ; RV64IM-NEXT: srli a3, a3, 8
; RV64IM-NEXT: addw a3, a3, a4 ; RV64IM-NEXT: addw a3, a3, a5
; RV64IM-NEXT: lui a4, %hi(.LCPI4_2) ; RV64IM-NEXT: lui a5, %hi(.LCPI4_2)
; RV64IM-NEXT: ld a4, %lo(.LCPI4_2)(a4) ; RV64IM-NEXT: ld a5, %lo(.LCPI4_2)(a5)
; RV64IM-NEXT: li a5, 654 ; RV64IM-NEXT: li a6, 654
; RV64IM-NEXT: mulw a3, a3, a5 ; RV64IM-NEXT: mulw a3, a3, a6
; RV64IM-NEXT: subw a1, a1, a3 ; RV64IM-NEXT: subw a1, a1, a3
; RV64IM-NEXT: mulh a3, a6, a4 ; RV64IM-NEXT: mulh a3, a4, a5
; RV64IM-NEXT: srli a4, a3, 63 ; RV64IM-NEXT: srli a5, a3, 63
; RV64IM-NEXT: srli a3, a3, 11 ; RV64IM-NEXT: srli a3, a3, 11
; RV64IM-NEXT: addw a3, a3, a4 ; RV64IM-NEXT: addw a3, a3, a5
; RV64IM-NEXT: lui a4, 1 ; RV64IM-NEXT: lui a5, 1
; RV64IM-NEXT: addiw a4, a4, 1327 ; RV64IM-NEXT: addiw a5, a5, 1327
; RV64IM-NEXT: mulw a3, a3, a4 ; RV64IM-NEXT: mulw a3, a3, a5
; RV64IM-NEXT: subw a3, a6, a3 ; RV64IM-NEXT: subw a3, a4, a3
; RV64IM-NEXT: sh zero, 0(a0) ; RV64IM-NEXT: sh zero, 0(a0)
; RV64IM-NEXT: sh a3, 6(a0) ; RV64IM-NEXT: sh a3, 6(a0)
; RV64IM-NEXT: sh a1, 2(a0) ; RV64IM-NEXT: sh a1, 2(a0)
; RV64IM-NEXT: sh a2, 4(a0) ; RV64IM-NEXT: sh a2, 4(a0)
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423> %1 = srem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is 2^15. ; Don't fold if the divisor is 2^15.
define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind { define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind {
; RV32I-LABEL: dont_fold_urem_i16_smax: ; RV32I-LABEL: dont_fold_urem_i16_smax:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lh a2, 4(a1) ; RV32I-NEXT: lh a2, 4(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lh s2, 12(a1) ; RV32I-NEXT: lh s1, 12(a1)
; RV32I-NEXT: lh a0, 8(a1) ; RV32I-NEXT: lh a0, 8(a1)
; RV32I-NEXT: srli a1, a2, 17 ; RV32I-NEXT: srli a1, a2, 17
; RV32I-NEXT: add a1, a2, a1 ; RV32I-NEXT: add a1, a2, a1
; RV32I-NEXT: lui a3, 8 ; RV32I-NEXT: lui a3, 8
; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: and a1, a1, a3
; RV32I-NEXT: sub s3, a2, a1 ; RV32I-NEXT: sub s3, a2, a1
; RV32I-NEXT: li a1, 23 ; RV32I-NEXT: li a1, 23
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a1, a0, 1327 ; RV32I-NEXT: addi a1, a0, 1327
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __modsi3@plt ; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh a0, 6(s0)
; RV32I-NEXT: sh s1, 4(s0) ; RV32I-NEXT: sh s2, 4(s0)
; RV32I-NEXT: sh zero, 0(s0) ; RV32I-NEXT: sh zero, 0(s0)
; RV32I-NEXT: sh s3, 2(s0) ; RV32I-NEXT: sh s3, 2(s0)
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
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; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lh a2, 8(a1) ; RV64I-NEXT: lh a2, 8(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lh s2, 24(a1) ; RV64I-NEXT: lh s1, 24(a1)
; RV64I-NEXT: lh a0, 16(a1) ; RV64I-NEXT: lh a0, 16(a1)
; RV64I-NEXT: srli a1, a2, 49 ; RV64I-NEXT: srli a1, a2, 49
; RV64I-NEXT: add a1, a2, a1 ; RV64I-NEXT: add a1, a2, a1
; RV64I-NEXT: lui a3, 8 ; RV64I-NEXT: lui a3, 8
; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: and a1, a1, a3
; RV64I-NEXT: subw s3, a2, a1 ; RV64I-NEXT: subw s3, a2, a1
; RV64I-NEXT: li a1, 23 ; RV64I-NEXT: li a1, 23
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: addiw a1, a0, 1327
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh a0, 6(s0)
; RV64I-NEXT: sh s1, 4(s0) ; RV64I-NEXT: sh s2, 4(s0)
; RV64I-NEXT: sh zero, 0(s0) ; RV64I-NEXT: sh zero, 0(s0)
; RV64I-NEXT: sh s3, 2(s0) ; RV64I-NEXT: sh s3, 2(s0)
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_urem_i16_smax: ; RV64IM-LABEL: dont_fold_urem_i16_smax:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lh a2, 16(a1) ; RV64IM-NEXT: lh a2, 16(a1)
; RV64IM-NEXT: lui a3, %hi(.LCPI5_0) ; RV64IM-NEXT: lui a3, %hi(.LCPI5_0)
; RV64IM-NEXT: ld a3, %lo(.LCPI5_0)(a3) ; RV64IM-NEXT: ld a3, %lo(.LCPI5_0)(a3)
; RV64IM-NEXT: lh a4, 24(a1) ; RV64IM-NEXT: lh a4, 24(a1)
; RV64IM-NEXT: mulh a3, a2, a3 ; RV64IM-NEXT: mulh a3, a2, a3
; RV64IM-NEXT: add a3, a3, a2 ; RV64IM-NEXT: add a3, a3, a2
; RV64IM-NEXT: srli a5, a3, 63 ; RV64IM-NEXT: srli a5, a3, 63
; RV64IM-NEXT: srli a3, a3, 4 ; RV64IM-NEXT: srli a3, a3, 4
; RV64IM-NEXT: addw a3, a3, a5 ; RV64IM-NEXT: addw a3, a3, a5
; RV64IM-NEXT: li a6, 23 ; RV64IM-NEXT: li a5, 23
; RV64IM-NEXT: lui a5, %hi(.LCPI5_1) ; RV64IM-NEXT: lui a6, %hi(.LCPI5_1)
; RV64IM-NEXT: ld a5, %lo(.LCPI5_1)(a5) ; RV64IM-NEXT: ld a6, %lo(.LCPI5_1)(a6)
; RV64IM-NEXT: mulw a3, a3, a6 ; RV64IM-NEXT: mulw a3, a3, a5
; RV64IM-NEXT: lh a1, 8(a1) ; RV64IM-NEXT: lh a1, 8(a1)
; RV64IM-NEXT: subw a2, a2, a3 ; RV64IM-NEXT: subw a2, a2, a3
; RV64IM-NEXT: mulh a3, a4, a5 ; RV64IM-NEXT: mulh a3, a4, a6
; RV64IM-NEXT: srli a5, a3, 63 ; RV64IM-NEXT: srli a5, a3, 63
; RV64IM-NEXT: srli a3, a3, 11 ; RV64IM-NEXT: srli a3, a3, 11
; RV64IM-NEXT: addw a3, a3, a5 ; RV64IM-NEXT: addw a3, a3, a5
; RV64IM-NEXT: lui a5, 1 ; RV64IM-NEXT: lui a5, 1
; RV64IM-NEXT: addiw a5, a5, 1327 ; RV64IM-NEXT: addiw a5, a5, 1327
; RV64IM-NEXT: mulw a3, a3, a5 ; RV64IM-NEXT: mulw a3, a3, a5
; RV64IM-NEXT: subw a3, a4, a3 ; RV64IM-NEXT: subw a3, a4, a3
; RV64IM-NEXT: srli a4, a1, 49 ; RV64IM-NEXT: srli a4, a1, 49
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; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s9, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw s0, 24(a1)
; RV32I-NEXT: lw s2, 24(a1) ; RV32I-NEXT: lw s1, 28(a1)
; RV32I-NEXT: lw s3, 28(a1) ; RV32I-NEXT: lw s2, 16(a1)
; RV32I-NEXT: lw s4, 16(a1) ; RV32I-NEXT: lw s3, 20(a1)
; RV32I-NEXT: lw s5, 20(a1) ; RV32I-NEXT: lw s4, 8(a1)
; RV32I-NEXT: lw s6, 8(a1) ; RV32I-NEXT: lw s5, 12(a1)
; RV32I-NEXT: lw s1, 12(a1)
; RV32I-NEXT: lw a3, 0(a1) ; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a1, 4(a1) ; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: li a2, 1 ; RV32I-NEXT: li a2, 1
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __moddi3@plt ; RV32I-NEXT: call __moddi3@plt
; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: mv s7, a0
; RV32I-NEXT: mv s8, a1 ; RV32I-NEXT: mv s8, a1
; RV32I-NEXT: li a2, 654 ; RV32I-NEXT: li a2, 654
; RV32I-NEXT: mv a0, s6
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __moddi3@plt
; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: mv s9, a1
; RV32I-NEXT: li a2, 23
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s5 ; RV32I-NEXT: mv a1, s5
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __moddi3@plt ; RV32I-NEXT: call __moddi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: li a2, 23
; RV32I-NEXT: addi a2, a0, 1327
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __moddi3@plt ; RV32I-NEXT: call __moddi3@plt
; RV32I-NEXT: sw a1, 28(s0) ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: sw a0, 24(s0) ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: sw s1, 20(s0) ; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: sw s4, 16(s0) ; RV32I-NEXT: addi a2, a0, 1327
; RV32I-NEXT: sw s9, 12(s0) ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: sw s6, 8(s0) ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: sw s8, 4(s0) ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: sw s7, 0(s0) ; RV32I-NEXT: call __moddi3@plt
; RV32I-NEXT: sw a1, 28(s6)
; RV32I-NEXT: sw a0, 24(s6)
; RV32I-NEXT: sw s3, 20(s6)
; RV32I-NEXT: sw s2, 16(s6)
; RV32I-NEXT: sw s5, 12(s6)
; RV32I-NEXT: sw s4, 8(s6)
; RV32I-NEXT: sw s8, 4(s6)
; RV32I-NEXT: sw s7, 0(s6)
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_srem_i64: ; RV32IM-LABEL: dont_fold_srem_i64:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -48 ; RV32IM-NEXT: addi sp, sp, -48
; RV32IM-NEXT: sw ra, 44(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s0, 40(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s1, 36(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s2, 32(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s3, 28(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s4, 24(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s5, 20(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s6, 16(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s7, 12(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s8, 8(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s9, 4(sp) # 4-byte Folded Spill ; RV32IM-NEXT: lw s0, 24(a1)
; RV32IM-NEXT: lw s2, 24(a1) ; RV32IM-NEXT: lw s1, 28(a1)
; RV32IM-NEXT: lw s3, 28(a1) ; RV32IM-NEXT: lw s2, 16(a1)
; RV32IM-NEXT: lw s4, 16(a1) ; RV32IM-NEXT: lw s3, 20(a1)
; RV32IM-NEXT: lw s5, 20(a1) ; RV32IM-NEXT: lw s4, 8(a1)
; RV32IM-NEXT: lw s6, 8(a1) ; RV32IM-NEXT: lw s5, 12(a1)
; RV32IM-NEXT: lw s1, 12(a1)
; RV32IM-NEXT: lw a3, 0(a1) ; RV32IM-NEXT: lw a3, 0(a1)
; RV32IM-NEXT: lw a1, 4(a1) ; RV32IM-NEXT: lw a1, 4(a1)
; RV32IM-NEXT: mv s0, a0 ; RV32IM-NEXT: mv s6, a0
; RV32IM-NEXT: li a2, 1 ; RV32IM-NEXT: li a2, 1
; RV32IM-NEXT: mv a0, a3 ; RV32IM-NEXT: mv a0, a3
; RV32IM-NEXT: li a3, 0 ; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __moddi3@plt ; RV32IM-NEXT: call __moddi3@plt
; RV32IM-NEXT: mv s7, a0 ; RV32IM-NEXT: mv s7, a0
; RV32IM-NEXT: mv s8, a1 ; RV32IM-NEXT: mv s8, a1
; RV32IM-NEXT: li a2, 654 ; RV32IM-NEXT: li a2, 654
; RV32IM-NEXT: mv a0, s6
; RV32IM-NEXT: mv a1, s1
; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __moddi3@plt
; RV32IM-NEXT: mv s6, a0
; RV32IM-NEXT: mv s9, a1
; RV32IM-NEXT: li a2, 23
; RV32IM-NEXT: mv a0, s4 ; RV32IM-NEXT: mv a0, s4
; RV32IM-NEXT: mv a1, s5 ; RV32IM-NEXT: mv a1, s5
; RV32IM-NEXT: li a3, 0 ; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __moddi3@plt ; RV32IM-NEXT: call __moddi3@plt
; RV32IM-NEXT: mv s4, a0 ; RV32IM-NEXT: mv s4, a0
; RV32IM-NEXT: mv s1, a1 ; RV32IM-NEXT: mv s5, a1
; RV32IM-NEXT: lui a0, 1 ; RV32IM-NEXT: li a2, 23
; RV32IM-NEXT: addi a2, a0, 1327
; RV32IM-NEXT: mv a0, s2 ; RV32IM-NEXT: mv a0, s2
; RV32IM-NEXT: mv a1, s3 ; RV32IM-NEXT: mv a1, s3
; RV32IM-NEXT: li a3, 0 ; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __moddi3@plt ; RV32IM-NEXT: call __moddi3@plt
; RV32IM-NEXT: sw a1, 28(s0) ; RV32IM-NEXT: mv s2, a0
; RV32IM-NEXT: sw a0, 24(s0) ; RV32IM-NEXT: mv s3, a1
; RV32IM-NEXT: sw s1, 20(s0) ; RV32IM-NEXT: lui a0, 1
; RV32IM-NEXT: sw s4, 16(s0) ; RV32IM-NEXT: addi a2, a0, 1327
; RV32IM-NEXT: sw s9, 12(s0) ; RV32IM-NEXT: mv a0, s0
; RV32IM-NEXT: sw s6, 8(s0) ; RV32IM-NEXT: mv a1, s1
; RV32IM-NEXT: sw s8, 4(s0) ; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: sw s7, 0(s0) ; RV32IM-NEXT: call __moddi3@plt
; RV32IM-NEXT: sw a1, 28(s6)
; RV32IM-NEXT: sw a0, 24(s6)
; RV32IM-NEXT: sw s3, 20(s6)
; RV32IM-NEXT: sw s2, 16(s6)
; RV32IM-NEXT: sw s5, 12(s6)
; RV32IM-NEXT: sw s4, 8(s6)
; RV32IM-NEXT: sw s8, 4(s6)
; RV32IM-NEXT: sw s7, 0(s6)
; RV32IM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s1, 36(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s2, 32(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s3, 28(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s4, 24(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s5, 20(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s6, 16(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s7, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s8, 8(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 48 ; RV32IM-NEXT: addi sp, sp, 48
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_srem_i64: ; RV64I-LABEL: dont_fold_srem_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: ld s2, 24(a1) ; RV64I-NEXT: ld s0, 24(a1)
; RV64I-NEXT: ld s1, 16(a1) ; RV64I-NEXT: ld s1, 16(a1)
; RV64I-NEXT: ld a2, 8(a1) ; RV64I-NEXT: ld a2, 8(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: li a1, 654 ; RV64I-NEXT: li a1, 654
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: li a1, 23 ; RV64I-NEXT: li a1, 23
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: addiw a1, a0, 1327
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __moddi3@plt ; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: sd a0, 24(s0) ; RV64I-NEXT: sd a0, 24(s2)
; RV64I-NEXT: sd s1, 16(s0) ; RV64I-NEXT: sd s1, 16(s2)
; RV64I-NEXT: sd s3, 8(s0) ; RV64I-NEXT: sd s3, 8(s2)
; RV64I-NEXT: sd zero, 0(s0) ; RV64I-NEXT: sd zero, 0(s2)
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_srem_i64: ; RV64IM-LABEL: dont_fold_srem_i64:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: ld a2, 16(a1) ; RV64IM-NEXT: ld a2, 16(a1)
; RV64IM-NEXT: lui a3, %hi(.LCPI6_0) ; RV64IM-NEXT: lui a3, %hi(.LCPI6_0)
; RV64IM-NEXT: ld a3, %lo(.LCPI6_0)(a3) ; RV64IM-NEXT: ld a3, %lo(.LCPI6_0)(a3)
; RV64IM-NEXT: ld a6, 24(a1) ; RV64IM-NEXT: ld a4, 24(a1)
; RV64IM-NEXT: ld a1, 8(a1) ; RV64IM-NEXT: ld a1, 8(a1)
; RV64IM-NEXT: mulh a3, a2, a3 ; RV64IM-NEXT: mulh a3, a2, a3
; RV64IM-NEXT: add a3, a3, a2 ; RV64IM-NEXT: add a3, a3, a2
; RV64IM-NEXT: srli a5, a3, 63 ; RV64IM-NEXT: srli a5, a3, 63
; RV64IM-NEXT: srai a3, a3, 4 ; RV64IM-NEXT: srai a3, a3, 4
; RV64IM-NEXT: add a3, a3, a5 ; RV64IM-NEXT: add a3, a3, a5
; RV64IM-NEXT: lui a5, %hi(.LCPI6_1) ; RV64IM-NEXT: lui a5, %hi(.LCPI6_1)
; RV64IM-NEXT: ld a5, %lo(.LCPI6_1)(a5) ; RV64IM-NEXT: ld a5, %lo(.LCPI6_1)(a5)
; RV64IM-NEXT: li a4, 23 ; RV64IM-NEXT: li a6, 23
; RV64IM-NEXT: mul a3, a3, a4 ; RV64IM-NEXT: mul a3, a3, a6
; RV64IM-NEXT: sub a2, a2, a3 ; RV64IM-NEXT: sub a2, a2, a3
; RV64IM-NEXT: mulh a3, a1, a5 ; RV64IM-NEXT: mulh a3, a1, a5
; RV64IM-NEXT: srli a4, a3, 63 ; RV64IM-NEXT: srli a5, a3, 63
; RV64IM-NEXT: srai a3, a3, 8 ; RV64IM-NEXT: srai a3, a3, 8
; RV64IM-NEXT: add a3, a3, a4 ; RV64IM-NEXT: add a3, a3, a5
; RV64IM-NEXT: lui a4, %hi(.LCPI6_2) ; RV64IM-NEXT: lui a5, %hi(.LCPI6_2)
; RV64IM-NEXT: ld a4, %lo(.LCPI6_2)(a4) ; RV64IM-NEXT: ld a5, %lo(.LCPI6_2)(a5)
; RV64IM-NEXT: li a5, 654 ; RV64IM-NEXT: li a6, 654
; RV64IM-NEXT: mul a3, a3, a5 ; RV64IM-NEXT: mul a3, a3, a6
; RV64IM-NEXT: sub a1, a1, a3 ; RV64IM-NEXT: sub a1, a1, a3
; RV64IM-NEXT: mulh a3, a6, a4 ; RV64IM-NEXT: mulh a3, a4, a5
; RV64IM-NEXT: srli a4, a3, 63 ; RV64IM-NEXT: srli a5, a3, 63
; RV64IM-NEXT: srai a3, a3, 11 ; RV64IM-NEXT: srai a3, a3, 11
; RV64IM-NEXT: add a3, a3, a4 ; RV64IM-NEXT: add a3, a3, a5
; RV64IM-NEXT: lui a4, 1 ; RV64IM-NEXT: lui a5, 1
; RV64IM-NEXT: addiw a4, a4, 1327 ; RV64IM-NEXT: addiw a5, a5, 1327
; RV64IM-NEXT: mul a3, a3, a4 ; RV64IM-NEXT: mul a3, a3, a5
; RV64IM-NEXT: sub a3, a6, a3 ; RV64IM-NEXT: sub a3, a4, a3
; RV64IM-NEXT: sd zero, 0(a0) ; RV64IM-NEXT: sd zero, 0(a0)
; RV64IM-NEXT: sd a3, 24(a0) ; RV64IM-NEXT: sd a3, 24(a0)
; RV64IM-NEXT: sd a1, 8(a0) ; RV64IM-NEXT: sd a1, 8(a0)
; RV64IM-NEXT: sd a2, 16(a0) ; RV64IM-NEXT: sd a2, 16(a0)
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423> %1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1 ret <4 x i64> %1
} }

llvm/test/CodeGen/RISCV/ssub_sat.ll

Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
; RV64IZbbNOZbt-NEXT: .LBB1_2: ; RV64IZbbNOZbt-NEXT: .LBB1_2:
; RV64IZbbNOZbt-NEXT: ret ; RV64IZbbNOZbt-NEXT: ret
; ;
; RV32IZbbZbt-LABEL: func2: ; RV32IZbbZbt-LABEL: func2:
; RV32IZbbZbt: # %bb.0: ; RV32IZbbZbt: # %bb.0:
; RV32IZbbZbt-NEXT: sltu a4, a0, a2 ; RV32IZbbZbt-NEXT: sltu a4, a0, a2
; RV32IZbbZbt-NEXT: sub a5, a1, a3 ; RV32IZbbZbt-NEXT: sub a5, a1, a3
; RV32IZbbZbt-NEXT: sub a4, a5, a4 ; RV32IZbbZbt-NEXT: sub a4, a5, a4
; RV32IZbbZbt-NEXT: srai a6, a4, 31 ; RV32IZbbZbt-NEXT: srai a5, a4, 31
; RV32IZbbZbt-NEXT: lui a5, 524288 ; RV32IZbbZbt-NEXT: lui a6, 524288
; RV32IZbbZbt-NEXT: xor a7, a6, a5 ; RV32IZbbZbt-NEXT: xor a6, a5, a6
; RV32IZbbZbt-NEXT: xor a5, a1, a4 ; RV32IZbbZbt-NEXT: xor a7, a1, a4
; RV32IZbbZbt-NEXT: xor a1, a1, a3 ; RV32IZbbZbt-NEXT: xor a1, a1, a3
; RV32IZbbZbt-NEXT: and a1, a1, a5 ; RV32IZbbZbt-NEXT: and a1, a1, a7
; RV32IZbbZbt-NEXT: slti a3, a1, 0 ; RV32IZbbZbt-NEXT: slti a3, a1, 0
; RV32IZbbZbt-NEXT: cmov a1, a3, a7, a4 ; RV32IZbbZbt-NEXT: cmov a1, a3, a6, a4
; RV32IZbbZbt-NEXT: sub a0, a0, a2 ; RV32IZbbZbt-NEXT: sub a0, a0, a2
; RV32IZbbZbt-NEXT: cmov a0, a3, a6, a0 ; RV32IZbbZbt-NEXT: cmov a0, a3, a5, a0
; RV32IZbbZbt-NEXT: ret ; RV32IZbbZbt-NEXT: ret
; ;
; RV64IZbbZbt-LABEL: func2: ; RV64IZbbZbt-LABEL: func2:
; RV64IZbbZbt: # %bb.0: ; RV64IZbbZbt: # %bb.0:
; RV64IZbbZbt-NEXT: sgtz a2, a1 ; RV64IZbbZbt-NEXT: sgtz a2, a1
; RV64IZbbZbt-NEXT: sub a1, a0, a1 ; RV64IZbbZbt-NEXT: sub a1, a0, a1
; RV64IZbbZbt-NEXT: slt a0, a1, a0 ; RV64IZbbZbt-NEXT: slt a0, a1, a0
; RV64IZbbZbt-NEXT: xor a0, a2, a0 ; RV64IZbbZbt-NEXT: xor a0, a2, a0
▲ Show 20 Lines • Show All 187 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/ssub_sat_plus.ll

Show First 20 Lines • Show All 158 Lines • ▼ Show 20 Lines
; RV64IZbbNOZbt-NEXT: .LBB1_2: ; RV64IZbbNOZbt-NEXT: .LBB1_2:
; RV64IZbbNOZbt-NEXT: ret ; RV64IZbbNOZbt-NEXT: ret
; ;
; RV32IZbbZbt-LABEL: func64: ; RV32IZbbZbt-LABEL: func64:
; RV32IZbbZbt: # %bb.0: ; RV32IZbbZbt: # %bb.0:
; RV32IZbbZbt-NEXT: sltu a2, a0, a4 ; RV32IZbbZbt-NEXT: sltu a2, a0, a4
; RV32IZbbZbt-NEXT: sub a3, a1, a5 ; RV32IZbbZbt-NEXT: sub a3, a1, a5
; RV32IZbbZbt-NEXT: sub a2, a3, a2 ; RV32IZbbZbt-NEXT: sub a2, a3, a2
; RV32IZbbZbt-NEXT: srai a6, a2, 31 ; RV32IZbbZbt-NEXT: srai a3, a2, 31
; RV32IZbbZbt-NEXT: lui a3, 524288 ; RV32IZbbZbt-NEXT: lui a6, 524288
; RV32IZbbZbt-NEXT: xor a7, a6, a3 ; RV32IZbbZbt-NEXT: xor a6, a3, a6
; RV32IZbbZbt-NEXT: xor a3, a1, a2 ; RV32IZbbZbt-NEXT: xor a7, a1, a2
; RV32IZbbZbt-NEXT: xor a1, a1, a5 ; RV32IZbbZbt-NEXT: xor a1, a1, a5
; RV32IZbbZbt-NEXT: and a1, a1, a3 ; RV32IZbbZbt-NEXT: and a1, a1, a7
; RV32IZbbZbt-NEXT: slti a3, a1, 0 ; RV32IZbbZbt-NEXT: slti a5, a1, 0
; RV32IZbbZbt-NEXT: cmov a1, a3, a7, a2 ; RV32IZbbZbt-NEXT: cmov a1, a5, a6, a2
; RV32IZbbZbt-NEXT: sub a0, a0, a4 ; RV32IZbbZbt-NEXT: sub a0, a0, a4
; RV32IZbbZbt-NEXT: cmov a0, a3, a6, a0 ; RV32IZbbZbt-NEXT: cmov a0, a5, a3, a0
; RV32IZbbZbt-NEXT: ret ; RV32IZbbZbt-NEXT: ret
; ;
; RV64IZbbZbt-LABEL: func64: ; RV64IZbbZbt-LABEL: func64:
; RV64IZbbZbt: # %bb.0: ; RV64IZbbZbt: # %bb.0:
; RV64IZbbZbt-NEXT: sgtz a1, a2 ; RV64IZbbZbt-NEXT: sgtz a1, a2
; RV64IZbbZbt-NEXT: sub a2, a0, a2 ; RV64IZbbZbt-NEXT: sub a2, a0, a2
; RV64IZbbZbt-NEXT: slt a0, a2, a0 ; RV64IZbbZbt-NEXT: slt a0, a2, a0
; RV64IZbbZbt-NEXT: xor a0, a1, a0 ; RV64IZbbZbt-NEXT: xor a0, a1, a0
▲ Show 20 Lines • Show All 243 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/stack-store-check.ll

Show All 26 Lines
; CHECK-NEXT: sw s8, 648(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw s8, 648(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s9, 644(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw s9, 644(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s10, 640(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw s10, 640(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s11, 636(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw s11, 636(sp) # 4-byte Folded Spill
; CHECK-NEXT: lui a0, %hi(U) ; CHECK-NEXT: lui a0, %hi(U)
; CHECK-NEXT: lw s6, %lo(U)(a0) ; CHECK-NEXT: lw s6, %lo(U)(a0)
; CHECK-NEXT: lw s7, %lo(U+4)(a0) ; CHECK-NEXT: lw s7, %lo(U+4)(a0)
; CHECK-NEXT: lw s8, %lo(U+8)(a0) ; CHECK-NEXT: lw s8, %lo(U+8)(a0)
; CHECK-NEXT: lw s2, %lo(U+12)(a0) ; CHECK-NEXT: lw s0, %lo(U+12)(a0)
; CHECK-NEXT: sw zero, 612(sp) ; CHECK-NEXT: sw zero, 612(sp)
; CHECK-NEXT: sw zero, 608(sp) ; CHECK-NEXT: sw zero, 608(sp)
; CHECK-NEXT: sw zero, 604(sp) ; CHECK-NEXT: sw zero, 604(sp)
; CHECK-NEXT: sw zero, 600(sp) ; CHECK-NEXT: sw zero, 600(sp)
; CHECK-NEXT: sw s2, 596(sp) ; CHECK-NEXT: sw s0, 596(sp)
; CHECK-NEXT: sw s8, 592(sp) ; CHECK-NEXT: sw s8, 592(sp)
; CHECK-NEXT: sw s7, 588(sp) ; CHECK-NEXT: sw s7, 588(sp)
; CHECK-NEXT: addi a0, sp, 616 ; CHECK-NEXT: addi a0, sp, 616
; CHECK-NEXT: addi a1, sp, 600 ; CHECK-NEXT: addi a1, sp, 600
; CHECK-NEXT: addi a2, sp, 584 ; CHECK-NEXT: addi a2, sp, 584
; CHECK-NEXT: sw s6, 584(sp) ; CHECK-NEXT: sw s6, 584(sp)
; CHECK-NEXT: call __subtf3@plt ; CHECK-NEXT: call __subtf3@plt
; CHECK-NEXT: lw s4, 616(sp) ; CHECK-NEXT: lw s9, 616(sp)
; CHECK-NEXT: lw s5, 620(sp) ; CHECK-NEXT: lw s2, 620(sp)
; CHECK-NEXT: lw s3, 624(sp) ; CHECK-NEXT: lw s3, 624(sp)
; CHECK-NEXT: lw s11, 628(sp) ; CHECK-NEXT: lw s4, 628(sp)
; CHECK-NEXT: sw s2, 548(sp) ; CHECK-NEXT: sw s0, 548(sp)
; CHECK-NEXT: sw s8, 544(sp) ; CHECK-NEXT: sw s8, 544(sp)
; CHECK-NEXT: sw s7, 540(sp) ; CHECK-NEXT: sw s7, 540(sp)
; CHECK-NEXT: sw s6, 536(sp) ; CHECK-NEXT: sw s6, 536(sp)
; CHECK-NEXT: sw s11, 564(sp) ; CHECK-NEXT: sw s4, 564(sp)
; CHECK-NEXT: sw s3, 560(sp) ; CHECK-NEXT: sw s3, 560(sp)
; CHECK-NEXT: sw s5, 556(sp) ; CHECK-NEXT: sw s2, 556(sp)
; CHECK-NEXT: addi a0, sp, 568 ; CHECK-NEXT: addi a0, sp, 568
; CHECK-NEXT: addi a1, sp, 552 ; CHECK-NEXT: addi a1, sp, 552
; CHECK-NEXT: addi a2, sp, 536 ; CHECK-NEXT: addi a2, sp, 536
; CHECK-NEXT: sw s4, 552(sp) ; CHECK-NEXT: sw s9, 552(sp)
; CHECK-NEXT: call __subtf3@plt ; CHECK-NEXT: call __subtf3@plt
; CHECK-NEXT: lw a0, 568(sp) ; CHECK-NEXT: lw a0, 568(sp)
; CHECK-NEXT: sw a0, 40(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw a0, 40(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a0, 572(sp) ; CHECK-NEXT: lw a0, 572(sp)
; CHECK-NEXT: sw a0, 32(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw a0, 32(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a0, 576(sp) ; CHECK-NEXT: lw a0, 576(sp)
; CHECK-NEXT: sw a0, 24(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw a0, 24(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a0, 580(sp) ; CHECK-NEXT: lw a0, 580(sp)
; CHECK-NEXT: sw a0, 48(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw a0, 48(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw zero, 500(sp) ; CHECK-NEXT: sw zero, 500(sp)
; CHECK-NEXT: sw zero, 496(sp) ; CHECK-NEXT: sw zero, 496(sp)
; CHECK-NEXT: sw zero, 492(sp) ; CHECK-NEXT: sw zero, 492(sp)
; CHECK-NEXT: sw zero, 488(sp) ; CHECK-NEXT: sw zero, 488(sp)
; CHECK-NEXT: sw s2, 516(sp) ; CHECK-NEXT: sw s0, 516(sp)
; CHECK-NEXT: sw s8, 512(sp) ; CHECK-NEXT: sw s8, 512(sp)
; CHECK-NEXT: sw s7, 508(sp) ; CHECK-NEXT: sw s7, 508(sp)
; CHECK-NEXT: addi a0, sp, 520 ; CHECK-NEXT: addi a0, sp, 520
; CHECK-NEXT: addi a1, sp, 504 ; CHECK-NEXT: addi a1, sp, 504
; CHECK-NEXT: addi a2, sp, 488 ; CHECK-NEXT: addi a2, sp, 488
; CHECK-NEXT: sw s6, 504(sp) ; CHECK-NEXT: sw s6, 504(sp)
; CHECK-NEXT: call __addtf3@plt ; CHECK-NEXT: call __addtf3@plt
; CHECK-NEXT: lw s9, 520(sp) ; CHECK-NEXT: lw s11, 520(sp)
; CHECK-NEXT: lw s10, 524(sp) ; CHECK-NEXT: lw s10, 524(sp)
; CHECK-NEXT: lw s0, 528(sp) ; CHECK-NEXT: lw s5, 528(sp)
; CHECK-NEXT: sw s0, 20(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw s1, 532(sp) ; CHECK-NEXT: lw s1, 532(sp)
; CHECK-NEXT: sw s1, 16(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw s1, 16(sp) # 4-byte Folded Spill
; CHECK-NEXT: lui a0, %hi(Y1) ; CHECK-NEXT: lui a0, %hi(Y1)
; CHECK-NEXT: lw a1, %lo(Y1)(a0) ; CHECK-NEXT: lw a1, %lo(Y1)(a0)
; CHECK-NEXT: sw a1, 52(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw a1, 52(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a2, %lo(Y1+4)(a0) ; CHECK-NEXT: lw a2, %lo(Y1+4)(a0)
; CHECK-NEXT: sw a2, 12(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw a2, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a3, %lo(Y1+8)(a0) ; CHECK-NEXT: lw a3, %lo(Y1+8)(a0)
; CHECK-NEXT: sw a3, 8(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw a3, 8(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a0, %lo(Y1+12)(a0) ; CHECK-NEXT: lw a0, %lo(Y1+12)(a0)
; CHECK-NEXT: sw a0, 4(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw a0, 4(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw a0, 308(sp) ; CHECK-NEXT: sw a0, 308(sp)
; CHECK-NEXT: sw a3, 304(sp) ; CHECK-NEXT: sw a3, 304(sp)
; CHECK-NEXT: sw a2, 300(sp) ; CHECK-NEXT: sw a2, 300(sp)
; CHECK-NEXT: sw a1, 296(sp) ; CHECK-NEXT: sw a1, 296(sp)
; CHECK-NEXT: sw s11, 324(sp) ; CHECK-NEXT: sw s4, 324(sp)
; CHECK-NEXT: sw s3, 320(sp) ; CHECK-NEXT: sw s3, 320(sp)
; CHECK-NEXT: sw s5, 316(sp) ; CHECK-NEXT: sw s2, 316(sp)
; CHECK-NEXT: addi a0, sp, 328 ; CHECK-NEXT: addi a0, sp, 328
; CHECK-NEXT: addi a1, sp, 312 ; CHECK-NEXT: addi a1, sp, 312
; CHECK-NEXT: addi a2, sp, 296 ; CHECK-NEXT: addi a2, sp, 296
; CHECK-NEXT: sw s4, 312(sp) ; CHECK-NEXT: sw s9, 312(sp)
; CHECK-NEXT: call __multf3@plt ; CHECK-NEXT: call __multf3@plt
; CHECK-NEXT: lw a0, 328(sp) ; CHECK-NEXT: lw a0, 328(sp)
; CHECK-NEXT: sw a0, 44(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw a0, 44(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a0, 332(sp) ; CHECK-NEXT: lw a0, 332(sp)
; CHECK-NEXT: sw a0, 36(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw a0, 36(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw a0, 336(sp) ; CHECK-NEXT: lw a0, 336(sp)
; CHECK-NEXT: sw a0, 28(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw a0, 28(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw s4, 340(sp) ; CHECK-NEXT: lw s9, 340(sp)
; CHECK-NEXT: sw s2, 468(sp) ; CHECK-NEXT: sw s0, 468(sp)
; CHECK-NEXT: sw s8, 464(sp) ; CHECK-NEXT: sw s8, 464(sp)
; CHECK-NEXT: sw s7, 460(sp) ; CHECK-NEXT: sw s7, 460(sp)
; CHECK-NEXT: sw s6, 456(sp) ; CHECK-NEXT: sw s6, 456(sp)
; CHECK-NEXT: sw s1, 452(sp) ; CHECK-NEXT: sw s1, 452(sp)
; CHECK-NEXT: sw s0, 448(sp) ; CHECK-NEXT: sw s5, 448(sp)
; CHECK-NEXT: sw s10, 444(sp) ; CHECK-NEXT: sw s10, 444(sp)
; CHECK-NEXT: addi a0, sp, 472 ; CHECK-NEXT: addi a0, sp, 472
; CHECK-NEXT: addi a1, sp, 456 ; CHECK-NEXT: addi a1, sp, 456
; CHECK-NEXT: addi a2, sp, 440 ; CHECK-NEXT: addi a2, sp, 440
; CHECK-NEXT: sw s9, 440(sp) ; CHECK-NEXT: sw s11, 440(sp)
; CHECK-NEXT: call __addtf3@plt ; CHECK-NEXT: call __addtf3@plt
; CHECK-NEXT: lw a3, 472(sp) ; CHECK-NEXT: lw a3, 472(sp)
; CHECK-NEXT: lw a0, 476(sp) ; CHECK-NEXT: lw a0, 476(sp)
; CHECK-NEXT: lw a1, 480(sp) ; CHECK-NEXT: lw a1, 480(sp)
; CHECK-NEXT: lw a2, 484(sp) ; CHECK-NEXT: lw a2, 484(sp)
; CHECK-NEXT: sw zero, 420(sp) ; CHECK-NEXT: sw zero, 420(sp)
; CHECK-NEXT: sw zero, 416(sp) ; CHECK-NEXT: sw zero, 416(sp)
; CHECK-NEXT: sw zero, 412(sp) ; CHECK-NEXT: sw zero, 412(sp)
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; CHECK-NEXT: lw a1, 436(sp) ; CHECK-NEXT: lw a1, 436(sp)
; CHECK-NEXT: lw a2, 432(sp) ; CHECK-NEXT: lw a2, 432(sp)
; CHECK-NEXT: lw a3, 428(sp) ; CHECK-NEXT: lw a3, 428(sp)
; CHECK-NEXT: lui a4, %hi(X) ; CHECK-NEXT: lui a4, %hi(X)
; CHECK-NEXT: sw a1, %lo(X+12)(a4) ; CHECK-NEXT: sw a1, %lo(X+12)(a4)
; CHECK-NEXT: sw a2, %lo(X+8)(a4) ; CHECK-NEXT: sw a2, %lo(X+8)(a4)
; CHECK-NEXT: sw a3, %lo(X+4)(a4) ; CHECK-NEXT: sw a3, %lo(X+4)(a4)
; CHECK-NEXT: sw a0, %lo(X)(a4) ; CHECK-NEXT: sw a0, %lo(X)(a4)
; CHECK-NEXT: lw s8, 4(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw s4, 4(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s8, 212(sp) ; CHECK-NEXT: sw s4, 212(sp)
; CHECK-NEXT: lw s7, 8(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw s3, 8(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s7, 208(sp) ; CHECK-NEXT: sw s3, 208(sp)
; CHECK-NEXT: lw s11, 12(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw s2, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s11, 204(sp) ; CHECK-NEXT: sw s2, 204(sp)
; CHECK-NEXT: lw a0, 52(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw a0, 52(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 200(sp) ; CHECK-NEXT: sw a0, 200(sp)
; CHECK-NEXT: lw a0, 48(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 228(sp) ; CHECK-NEXT: sw a0, 228(sp)
; CHECK-NEXT: lw s3, 24(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw s1, 24(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s3, 224(sp) ; CHECK-NEXT: sw s1, 224(sp)
; CHECK-NEXT: lw s2, 32(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw s0, 32(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s2, 220(sp) ; CHECK-NEXT: sw s0, 220(sp)
; CHECK-NEXT: addi a0, sp, 232 ; CHECK-NEXT: addi a0, sp, 232
; CHECK-NEXT: addi a1, sp, 216 ; CHECK-NEXT: addi a1, sp, 216
; CHECK-NEXT: addi a2, sp, 200 ; CHECK-NEXT: addi a2, sp, 200
; CHECK-NEXT: lw s1, 40(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw s8, 40(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s1, 216(sp) ; CHECK-NEXT: sw s8, 216(sp)
; CHECK-NEXT: call __multf3@plt ; CHECK-NEXT: call __multf3@plt
; CHECK-NEXT: lw s5, 232(sp) ; CHECK-NEXT: lw s5, 232(sp)
; CHECK-NEXT: lw a0, 236(sp) ; CHECK-NEXT: lw a0, 236(sp)
; CHECK-NEXT: sw a0, 0(sp) # 4-byte Folded Spill ; CHECK-NEXT: sw a0, 0(sp) # 4-byte Folded Spill
; CHECK-NEXT: lw s6, 240(sp) ; CHECK-NEXT: lw s6, 240(sp)
; CHECK-NEXT: lw s0, 244(sp) ; CHECK-NEXT: lw s7, 244(sp)
; CHECK-NEXT: sw zero, 356(sp) ; CHECK-NEXT: sw zero, 356(sp)
; CHECK-NEXT: sw zero, 352(sp) ; CHECK-NEXT: sw zero, 352(sp)
; CHECK-NEXT: sw zero, 348(sp) ; CHECK-NEXT: sw zero, 348(sp)
; CHECK-NEXT: sw zero, 344(sp) ; CHECK-NEXT: sw zero, 344(sp)
; CHECK-NEXT: lw a0, 16(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 372(sp) ; CHECK-NEXT: sw a0, 372(sp)
; CHECK-NEXT: lw a0, 20(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 368(sp) ; CHECK-NEXT: sw a0, 368(sp)
; CHECK-NEXT: sw s10, 364(sp) ; CHECK-NEXT: sw s10, 364(sp)
; CHECK-NEXT: addi a0, sp, 376 ; CHECK-NEXT: addi a0, sp, 376
; CHECK-NEXT: addi a1, sp, 360 ; CHECK-NEXT: addi a1, sp, 360
; CHECK-NEXT: addi a2, sp, 344 ; CHECK-NEXT: addi a2, sp, 344
; CHECK-NEXT: sw s9, 360(sp) ; CHECK-NEXT: sw s11, 360(sp)
; CHECK-NEXT: call __multf3@plt ; CHECK-NEXT: call __multf3@plt
; CHECK-NEXT: lw a0, 376(sp) ; CHECK-NEXT: lw a0, 376(sp)
; CHECK-NEXT: lw a1, 388(sp) ; CHECK-NEXT: lw a1, 388(sp)
; CHECK-NEXT: lw a2, 384(sp) ; CHECK-NEXT: lw a2, 384(sp)
; CHECK-NEXT: lw a3, 380(sp) ; CHECK-NEXT: lw a3, 380(sp)
; CHECK-NEXT: lui a4, %hi(S) ; CHECK-NEXT: lui a4, %hi(S)
; CHECK-NEXT: sw a1, %lo(S+12)(a4) ; CHECK-NEXT: sw a1, %lo(S+12)(a4)
; CHECK-NEXT: sw a2, %lo(S+8)(a4) ; CHECK-NEXT: sw a2, %lo(S+8)(a4)
; CHECK-NEXT: sw a3, %lo(S+4)(a4) ; CHECK-NEXT: sw a3, %lo(S+4)(a4)
; CHECK-NEXT: sw a0, %lo(S)(a4) ; CHECK-NEXT: sw a0, %lo(S)(a4)
; CHECK-NEXT: lw a0, 48(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 260(sp) ; CHECK-NEXT: sw a0, 260(sp)
; CHECK-NEXT: sw s3, 256(sp) ; CHECK-NEXT: sw s1, 256(sp)
; CHECK-NEXT: sw s2, 252(sp) ; CHECK-NEXT: sw s0, 252(sp)
; CHECK-NEXT: sw s1, 248(sp) ; CHECK-NEXT: sw s8, 248(sp)
; CHECK-NEXT: sw s4, 276(sp) ; CHECK-NEXT: sw s9, 276(sp)
; CHECK-NEXT: lw a0, 28(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw a0, 28(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 272(sp) ; CHECK-NEXT: sw a0, 272(sp)
; CHECK-NEXT: lw a0, 36(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw a0, 36(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 268(sp) ; CHECK-NEXT: sw a0, 268(sp)
; CHECK-NEXT: addi a0, sp, 280 ; CHECK-NEXT: addi a0, sp, 280
; CHECK-NEXT: addi a1, sp, 264 ; CHECK-NEXT: addi a1, sp, 264
; CHECK-NEXT: addi a2, sp, 248 ; CHECK-NEXT: addi a2, sp, 248
; CHECK-NEXT: lw a3, 44(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw a3, 44(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a3, 264(sp) ; CHECK-NEXT: sw a3, 264(sp)
; CHECK-NEXT: call __subtf3@plt ; CHECK-NEXT: call __subtf3@plt
; CHECK-NEXT: lw a0, 280(sp) ; CHECK-NEXT: lw a0, 280(sp)
; CHECK-NEXT: lw a1, 292(sp) ; CHECK-NEXT: lw a1, 292(sp)
; CHECK-NEXT: lw a2, 288(sp) ; CHECK-NEXT: lw a2, 288(sp)
; CHECK-NEXT: lw a3, 284(sp) ; CHECK-NEXT: lw a3, 284(sp)
; CHECK-NEXT: lui a4, %hi(T) ; CHECK-NEXT: lui a4, %hi(T)
; CHECK-NEXT: sw a1, %lo(T+12)(a4) ; CHECK-NEXT: sw a1, %lo(T+12)(a4)
; CHECK-NEXT: sw a2, %lo(T+8)(a4) ; CHECK-NEXT: sw a2, %lo(T+8)(a4)
; CHECK-NEXT: sw a3, %lo(T+4)(a4) ; CHECK-NEXT: sw a3, %lo(T+4)(a4)
; CHECK-NEXT: sw a0, %lo(T)(a4) ; CHECK-NEXT: sw a0, %lo(T)(a4)
; CHECK-NEXT: sw zero, 164(sp) ; CHECK-NEXT: sw zero, 164(sp)
; CHECK-NEXT: sw zero, 160(sp) ; CHECK-NEXT: sw zero, 160(sp)
; CHECK-NEXT: sw zero, 156(sp) ; CHECK-NEXT: sw zero, 156(sp)
; CHECK-NEXT: sw zero, 152(sp) ; CHECK-NEXT: sw zero, 152(sp)
; CHECK-NEXT: sw s0, 180(sp) ; CHECK-NEXT: sw s7, 180(sp)
; CHECK-NEXT: sw s6, 176(sp) ; CHECK-NEXT: sw s6, 176(sp)
; CHECK-NEXT: lw a0, 0(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw a0, 0(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 172(sp) ; CHECK-NEXT: sw a0, 172(sp)
; CHECK-NEXT: addi a0, sp, 184 ; CHECK-NEXT: addi a0, sp, 184
; CHECK-NEXT: addi a1, sp, 168 ; CHECK-NEXT: addi a1, sp, 168
; CHECK-NEXT: addi a2, sp, 152 ; CHECK-NEXT: addi a2, sp, 152
; CHECK-NEXT: sw s5, 168(sp) ; CHECK-NEXT: sw s5, 168(sp)
; CHECK-NEXT: call __addtf3@plt ; CHECK-NEXT: call __addtf3@plt
; CHECK-NEXT: lw a0, 184(sp) ; CHECK-NEXT: lw a0, 184(sp)
; CHECK-NEXT: lw a1, 196(sp) ; CHECK-NEXT: lw a1, 196(sp)
; CHECK-NEXT: lw a2, 192(sp) ; CHECK-NEXT: lw a2, 192(sp)
; CHECK-NEXT: lw a3, 188(sp) ; CHECK-NEXT: lw a3, 188(sp)
; CHECK-NEXT: lui a4, %hi(Y) ; CHECK-NEXT: lui a4, %hi(Y)
; CHECK-NEXT: sw a1, %lo(Y+12)(a4) ; CHECK-NEXT: sw a1, %lo(Y+12)(a4)
; CHECK-NEXT: sw a2, %lo(Y+8)(a4) ; CHECK-NEXT: sw a2, %lo(Y+8)(a4)
; CHECK-NEXT: sw a3, %lo(Y+4)(a4) ; CHECK-NEXT: sw a3, %lo(Y+4)(a4)
; CHECK-NEXT: sw a0, %lo(Y)(a4) ; CHECK-NEXT: sw a0, %lo(Y)(a4)
; CHECK-NEXT: sw zero, 116(sp) ; CHECK-NEXT: sw zero, 116(sp)
; CHECK-NEXT: sw zero, 112(sp) ; CHECK-NEXT: sw zero, 112(sp)
; CHECK-NEXT: sw zero, 108(sp) ; CHECK-NEXT: sw zero, 108(sp)
; CHECK-NEXT: sw zero, 104(sp) ; CHECK-NEXT: sw zero, 104(sp)
; CHECK-NEXT: sw s8, 132(sp) ; CHECK-NEXT: sw s4, 132(sp)
; CHECK-NEXT: sw s7, 128(sp) ; CHECK-NEXT: sw s3, 128(sp)
; CHECK-NEXT: sw s11, 124(sp) ; CHECK-NEXT: sw s2, 124(sp)
; CHECK-NEXT: addi a0, sp, 136 ; CHECK-NEXT: addi a0, sp, 136
; CHECK-NEXT: addi a1, sp, 120 ; CHECK-NEXT: addi a1, sp, 120
; CHECK-NEXT: addi a2, sp, 104 ; CHECK-NEXT: addi a2, sp, 104
; CHECK-NEXT: lw a3, 52(sp) # 4-byte Folded Reload ; CHECK-NEXT: lw a3, 52(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a3, 120(sp) ; CHECK-NEXT: sw a3, 120(sp)
; CHECK-NEXT: call __multf3@plt ; CHECK-NEXT: call __multf3@plt
; CHECK-NEXT: lw a3, 136(sp) ; CHECK-NEXT: lw a3, 136(sp)
; CHECK-NEXT: lw a0, 140(sp) ; CHECK-NEXT: lw a0, 140(sp)
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llvm/test/CodeGen/RISCV/tail-calls.ll

Show All 39 Lines
define void @caller_indirect_tail(i32 %a) nounwind { define void @caller_indirect_tail(i32 %a) nounwind {
; CHECK-LABEL: caller_indirect_tail ; CHECK-LABEL: caller_indirect_tail
; CHECK-NOT: call callee_indirect1 ; CHECK-NOT: call callee_indirect1
; CHECK-NOT: call callee_indirect2 ; CHECK-NOT: call callee_indirect2
; CHECK-NOT: tail callee_indirect1 ; CHECK-NOT: tail callee_indirect1
; CHECK-NOT: tail callee_indirect2 ; CHECK-NOT: tail callee_indirect2
; CHECK: lui a0, %hi(callee_indirect2) ; CHECK: lui a0, %hi(callee_indirect2)
; CHECK-NEXT: addi a5, a0, %lo(callee_indirect2) ; CHECK-NEXT: addi t1, a0, %lo(callee_indirect2)
; CHECK-NEXT: jr a5 ; CHECK-NEXT: jr t1
; CHECK: lui a0, %hi(callee_indirect1) ; CHECK: lui a0, %hi(callee_indirect1)
; CHECK-NEXT: addi a5, a0, %lo(callee_indirect1) ; CHECK-NEXT: addi t1, a0, %lo(callee_indirect1)
; CHECK-NEXT: jr a5 ; CHECK-NEXT: jr t1
entry: entry:
%tobool = icmp eq i32 %a, 0 %tobool = icmp eq i32 %a, 0
%callee = select i1 %tobool, void ()* @callee_indirect1, void ()* @callee_indirect2 %callee = select i1 %tobool, void ()* @callee_indirect1, void ()* @callee_indirect2
tail call void %callee() tail call void %callee()
ret void ret void
} }
; Make sure we don't use t0 as the source for jr as that is a hint to pop the ; Make sure we don't use t0 as the source for jr as that is a hint to pop the
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llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RISCV32 ; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RISCV32
define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 { define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 {
; RISCV32-LABEL: muloti_test: ; RISCV32-LABEL: muloti_test:
; RISCV32: # %bb.0: # %start ; RISCV32: # %bb.0: # %start
; RISCV32-NEXT: addi sp, sp, -32 ; RISCV32-NEXT: addi sp, sp, -32
; RISCV32-NEXT: sw s0, 28(sp) # 4-byte Folded Spill ; RISCV32-NEXT: sw s0, 28(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s1, 24(sp) # 4-byte Folded Spill ; RISCV32-NEXT: sw s1, 24(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s2, 20(sp) # 4-byte Folded Spill ; RISCV32-NEXT: sw s2, 20(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s3, 16(sp) # 4-byte Folded Spill ; RISCV32-NEXT: sw s3, 16(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s4, 12(sp) # 4-byte Folded Spill ; RISCV32-NEXT: sw s4, 12(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s5, 8(sp) # 4-byte Folded Spill ; RISCV32-NEXT: lw a3, 12(a1)
; RISCV32-NEXT: sw s6, 4(sp) # 4-byte Folded Spill
; RISCV32-NEXT: lw a6, 12(a1)
; RISCV32-NEXT: lw a7, 12(a2) ; RISCV32-NEXT: lw a7, 12(a2)
; RISCV32-NEXT: lw t3, 8(a1) ; RISCV32-NEXT: lw a6, 8(a1)
; RISCV32-NEXT: lw a4, 0(a2) ; RISCV32-NEXT: lw a4, 0(a2)
; RISCV32-NEXT: lw a5, 0(a1) ; RISCV32-NEXT: lw a5, 0(a1)
; RISCV32-NEXT: lw a3, 4(a1) ; RISCV32-NEXT: lw t3, 4(a1)
; RISCV32-NEXT: lw s2, 8(a2) ; RISCV32-NEXT: lw t0, 8(a2)
; RISCV32-NEXT: lw a2, 4(a2) ; RISCV32-NEXT: lw a2, 4(a2)
; RISCV32-NEXT: mulhu a1, a5, a4 ; RISCV32-NEXT: mulhu a1, a5, a4
; RISCV32-NEXT: mul s1, a3, a4 ; RISCV32-NEXT: mul t1, t3, a4
; RISCV32-NEXT: add a1, s1, a1 ; RISCV32-NEXT: add a1, t1, a1
; RISCV32-NEXT: sltu s1, a1, s1 ; RISCV32-NEXT: sltu t1, a1, t1
; RISCV32-NEXT: mulhu s0, a3, a4 ; RISCV32-NEXT: mulhu t2, t3, a4
; RISCV32-NEXT: add t4, s0, s1 ; RISCV32-NEXT: add t4, t2, t1
; RISCV32-NEXT: mul s0, a5, a2 ; RISCV32-NEXT: mul t1, a5, a2
; RISCV32-NEXT: add t0, s0, a1 ; RISCV32-NEXT: add a1, t1, a1
; RISCV32-NEXT: sltu a1, t0, s0 ; RISCV32-NEXT: sltu t1, a1, t1
; RISCV32-NEXT: mulhu s0, a5, a2 ; RISCV32-NEXT: mulhu t2, a5, a2
; RISCV32-NEXT: add a1, s0, a1 ; RISCV32-NEXT: add t1, t2, t1
; RISCV32-NEXT: add a1, t4, a1 ; RISCV32-NEXT: add t5, t4, t1
; RISCV32-NEXT: mul s0, a3, a2 ; RISCV32-NEXT: mul t6, t3, a2
; RISCV32-NEXT: add s1, s0, a1 ; RISCV32-NEXT: add s0, t6, t5
; RISCV32-NEXT: mul t1, s2, a5 ; RISCV32-NEXT: mul t1, t0, a5
; RISCV32-NEXT: mul s3, t3, a4 ; RISCV32-NEXT: mul s3, a6, a4
; RISCV32-NEXT: add s4, s3, t1 ; RISCV32-NEXT: add s4, s3, t1
; RISCV32-NEXT: add t1, s1, s4 ; RISCV32-NEXT: add t1, s0, s4
; RISCV32-NEXT: sltu t2, t1, s1 ; RISCV32-NEXT: sltu t2, t1, s0
; RISCV32-NEXT: sltu s1, s1, s0 ; RISCV32-NEXT: sltu t6, s0, t6
; RISCV32-NEXT: sltu a1, a1, t4 ; RISCV32-NEXT: sltu t4, t5, t4
; RISCV32-NEXT: mulhu s0, a3, a2 ; RISCV32-NEXT: mulhu t5, t3, a2
; RISCV32-NEXT: add a1, s0, a1 ; RISCV32-NEXT: add t4, t5, t4
; RISCV32-NEXT: add s0, a1, s1 ; RISCV32-NEXT: add s0, t4, t6
; RISCV32-NEXT: mul a1, a3, s2 ; RISCV32-NEXT: mul t4, t3, t0
; RISCV32-NEXT: mul s1, a7, a5 ; RISCV32-NEXT: mul t5, a7, a5
; RISCV32-NEXT: add a1, s1, a1 ; RISCV32-NEXT: add t4, t5, t4
; RISCV32-NEXT: mulhu s5, s2, a5 ; RISCV32-NEXT: mulhu s1, t0, a5
; RISCV32-NEXT: add s6, s5, a1 ; RISCV32-NEXT: add s2, s1, t4
; RISCV32-NEXT: mul s1, a2, t3 ; RISCV32-NEXT: mul t4, a2, a6
; RISCV32-NEXT: mul a1, a6, a4 ; RISCV32-NEXT: mul t5, a3, a4
; RISCV32-NEXT: add a1, a1, s1 ; RISCV32-NEXT: add t4, t5, t4
; RISCV32-NEXT: mulhu t5, t3, a4 ; RISCV32-NEXT: mulhu t5, a6, a4
; RISCV32-NEXT: add t6, t5, a1 ; RISCV32-NEXT: add t6, t5, t4
; RISCV32-NEXT: add a1, t6, s6 ; RISCV32-NEXT: add t4, t6, s2
; RISCV32-NEXT: sltu s1, s4, s3 ; RISCV32-NEXT: sltu s3, s4, s3
; RISCV32-NEXT: add a1, a1, s1 ; RISCV32-NEXT: add t4, t4, s3
; RISCV32-NEXT: add a1, s0, a1 ; RISCV32-NEXT: add t4, s0, t4
; RISCV32-NEXT: add t4, a1, t2 ; RISCV32-NEXT: add t4, t4, t2
; RISCV32-NEXT: beq t4, s0, .LBB0_2 ; RISCV32-NEXT: beq t4, s0, .LBB0_2
; RISCV32-NEXT: # %bb.1: # %start ; RISCV32-NEXT: # %bb.1: # %start
; RISCV32-NEXT: sltu t2, t4, s0 ; RISCV32-NEXT: sltu t2, t4, s0
; RISCV32-NEXT: .LBB0_2: # %start ; RISCV32-NEXT: .LBB0_2: # %start
; RISCV32-NEXT: sltu a1, s6, s5 ; RISCV32-NEXT: sltu s0, s2, s1
; RISCV32-NEXT: snez s1, t3
; RISCV32-NEXT: snez s2, a7
; RISCV32-NEXT: and s1, s2, s1
; RISCV32-NEXT: mulhu s2, a7, a5
; RISCV32-NEXT: snez s2, s2
; RISCV32-NEXT: or s1, s1, s2
; RISCV32-NEXT: mulhu t3, t3, t0
; RISCV32-NEXT: snez t3, t3
; RISCV32-NEXT: or t3, s1, t3
; RISCV32-NEXT: or t3, t3, s0
; RISCV32-NEXT: sltu t5, t6, t5
; RISCV32-NEXT: snez t6, a2
; RISCV32-NEXT: snez s0, a3 ; RISCV32-NEXT: snez s0, a3
; RISCV32-NEXT: snez s1, a7 ; RISCV32-NEXT: and t6, s0, t6
; RISCV32-NEXT: and s0, s1, s0 ; RISCV32-NEXT: mulhu s0, a3, a4
; RISCV32-NEXT: mulhu s1, a7, a5
; RISCV32-NEXT: snez s1, s1
; RISCV32-NEXT: or s0, s0, s1
; RISCV32-NEXT: mulhu a3, a3, s2
; RISCV32-NEXT: snez a3, a3
; RISCV32-NEXT: or a3, s0, a3
; RISCV32-NEXT: or a1, a3, a1
; RISCV32-NEXT: sltu a3, t6, t5
; RISCV32-NEXT: snez s1, a2
; RISCV32-NEXT: snez s0, a6
; RISCV32-NEXT: and s1, s0, s1
; RISCV32-NEXT: mulhu s0, a6, a4
; RISCV32-NEXT: snez s0, s0 ; RISCV32-NEXT: snez s0, s0
; RISCV32-NEXT: or s1, s1, s0 ; RISCV32-NEXT: or t6, t6, s0
; RISCV32-NEXT: mulhu a2, a2, t3 ; RISCV32-NEXT: mulhu a2, a2, a6
; RISCV32-NEXT: snez a2, a2 ; RISCV32-NEXT: snez a2, a2
; RISCV32-NEXT: or a2, s1, a2 ; RISCV32-NEXT: or a2, t6, a2
; RISCV32-NEXT: or a2, a2, a3 ; RISCV32-NEXT: or a2, a2, t5
; RISCV32-NEXT: or a3, s2, a7 ; RISCV32-NEXT: or a7, t0, a7
; RISCV32-NEXT: snez a7, a7
; RISCV32-NEXT: or a3, a6, a3
; RISCV32-NEXT: snez a3, a3 ; RISCV32-NEXT: snez a3, a3
; RISCV32-NEXT: or s1, t3, a6 ; RISCV32-NEXT: and a3, a3, a7
; RISCV32-NEXT: snez s1, s1
; RISCV32-NEXT: and a3, s1, a3
; RISCV32-NEXT: or a2, a3, a2 ; RISCV32-NEXT: or a2, a3, a2
; RISCV32-NEXT: or a1, a2, a1 ; RISCV32-NEXT: or a2, a2, t3
; RISCV32-NEXT: or a1, a1, t2 ; RISCV32-NEXT: or a2, a2, t2
; RISCV32-NEXT: mul a2, a5, a4 ; RISCV32-NEXT: mul a3, a5, a4
; RISCV32-NEXT: andi a1, a1, 1 ; RISCV32-NEXT: andi a2, a2, 1
; RISCV32-NEXT: sw a2, 0(a0) ; RISCV32-NEXT: sw a3, 0(a0)
; RISCV32-NEXT: sw t0, 4(a0) ; RISCV32-NEXT: sw a1, 4(a0)
; RISCV32-NEXT: sw t1, 8(a0) ; RISCV32-NEXT: sw t1, 8(a0)
; RISCV32-NEXT: sw t4, 12(a0) ; RISCV32-NEXT: sw t4, 12(a0)
; RISCV32-NEXT: sb a1, 16(a0) ; RISCV32-NEXT: sb a2, 16(a0)
; RISCV32-NEXT: lw s0, 28(sp) # 4-byte Folded Reload ; RISCV32-NEXT: lw s0, 28(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s1, 24(sp) # 4-byte Folded Reload ; RISCV32-NEXT: lw s1, 24(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s2, 20(sp) # 4-byte Folded Reload ; RISCV32-NEXT: lw s2, 20(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s3, 16(sp) # 4-byte Folded Reload ; RISCV32-NEXT: lw s3, 16(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s4, 12(sp) # 4-byte Folded Reload ; RISCV32-NEXT: lw s4, 12(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s5, 8(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s6, 4(sp) # 4-byte Folded Reload
; RISCV32-NEXT: addi sp, sp, 32 ; RISCV32-NEXT: addi sp, sp, 32
; RISCV32-NEXT: ret ; RISCV32-NEXT: ret
start: start:
%0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2 %0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
%1 = extractvalue { i128, i1 } %0, 0 %1 = extractvalue { i128, i1 } %0, 0
%2 = extractvalue { i128, i1 } %0, 1 %2 = extractvalue { i128, i1 } %0, 1
%3 = zext i1 %2 to i8 %3 = zext i1 %2 to i8
%4 = insertvalue { i128, i8 } undef, i128 %1, 0 %4 = insertvalue { i128, i8 } undef, i128 %1, 0
Show All 10 Lines

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

Show First 20 Lines • Show All 388 Lines • ▼ Show 20 Lines
; RV64-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: mv s0, a0 ; RV64-NEXT: mv s0, a0
; RV64-NEXT: lbu a0, 4(a0) ; RV64-NEXT: lbu a0, 4(a0)
; RV64-NEXT: lwu a1, 0(s0) ; RV64-NEXT: lwu a1, 0(s0)
; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: srli s2, a0, 11 ; RV64-NEXT: srli s1, a0, 11
; RV64-NEXT: srli s1, a0, 22 ; RV64-NEXT: srli s2, a0, 22
; RV64-NEXT: andi a0, a0, 2047 ; RV64-NEXT: andi a0, a0, 2047
; RV64-NEXT: li a1, 683 ; RV64-NEXT: li a1, 683
; RV64-NEXT: call __muldi3@plt ; RV64-NEXT: call __muldi3@plt
; RV64-NEXT: slli a1, a0, 10 ; RV64-NEXT: slli a1, a0, 10
; RV64-NEXT: slli a0, a0, 53 ; RV64-NEXT: slli a0, a0, 53
; RV64-NEXT: srli a0, a0, 54 ; RV64-NEXT: srli a0, a0, 54
; RV64-NEXT: or a0, a0, a1 ; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: andi a0, a0, 2047 ; RV64-NEXT: andi a0, a0, 2047
; RV64-NEXT: li a1, 341 ; RV64-NEXT: li a1, 341
; RV64-NEXT: sltu s3, a1, a0 ; RV64-NEXT: sltu s3, a1, a0
; RV64-NEXT: li a1, 819 ; RV64-NEXT: li a1, 819
; RV64-NEXT: mv a0, s1 ; RV64-NEXT: mv a0, s2
; RV64-NEXT: call __muldi3@plt ; RV64-NEXT: call __muldi3@plt
; RV64-NEXT: addiw a0, a0, -1638 ; RV64-NEXT: addiw a0, a0, -1638
; RV64-NEXT: andi a0, a0, 2047 ; RV64-NEXT: andi a0, a0, 2047
; RV64-NEXT: li a1, 1 ; RV64-NEXT: li a1, 1
; RV64-NEXT: sltu s1, a1, a0 ; RV64-NEXT: sltu s2, a1, a0
; RV64-NEXT: li a1, 1463 ; RV64-NEXT: li a1, 1463
; RV64-NEXT: mv a0, s2 ; RV64-NEXT: mv a0, s1
; RV64-NEXT: call __muldi3@plt ; RV64-NEXT: call __muldi3@plt
; RV64-NEXT: addiw a0, a0, -1463 ; RV64-NEXT: addiw a0, a0, -1463
; RV64-NEXT: andi a0, a0, 2047 ; RV64-NEXT: andi a0, a0, 2047
; RV64-NEXT: li a1, 292 ; RV64-NEXT: li a1, 292
; RV64-NEXT: sltu a0, a1, a0 ; RV64-NEXT: sltu a0, a1, a0
; RV64-NEXT: negw a1, s3 ; RV64-NEXT: negw a1, s3
; RV64-NEXT: negw a0, a0 ; RV64-NEXT: negw a0, a0
; RV64-NEXT: andi a1, a1, 2047 ; RV64-NEXT: andi a1, a1, 2047
; RV64-NEXT: andi a0, a0, 2047 ; RV64-NEXT: andi a0, a0, 2047
; RV64-NEXT: slli a0, a0, 11 ; RV64-NEXT: slli a0, a0, 11
; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: slli a1, s1, 22 ; RV64-NEXT: slli a1, s2, 22
; RV64-NEXT: sub a0, a0, a1 ; RV64-NEXT: sub a0, a0, a1
; RV64-NEXT: sw a0, 0(s0) ; RV64-NEXT: sw a0, 0(s0)
; RV64-NEXT: slli a0, a0, 31 ; RV64-NEXT: slli a0, a0, 31
; RV64-NEXT: srli a0, a0, 63 ; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: sb a0, 4(s0) ; RV64-NEXT: sb a0, 4(s0)
; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 231 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/urem-vector-lkk.ll

Show All 13 Lines
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: lhu s0, 12(a1)
; RV32I-NEXT: lhu s2, 12(a1) ; RV32I-NEXT: lhu s1, 8(a1)
; RV32I-NEXT: lhu s3, 8(a1) ; RV32I-NEXT: lhu s2, 4(a1)
; RV32I-NEXT: lhu s0, 4(a1)
; RV32I-NEXT: lhu a2, 0(a1) ; RV32I-NEXT: lhu a2, 0(a1)
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: li a1, 124 ; RV32I-NEXT: li a1, 124
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: li a1, 98 ; RV32I-NEXT: li a1, 98
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: li a1, 1003 ; RV32I-NEXT: li a1, 1003
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: sh a0, 6(s1) ; RV32I-NEXT: sh a0, 6(s3)
; RV32I-NEXT: sh s0, 4(s1) ; RV32I-NEXT: sh s1, 4(s3)
; RV32I-NEXT: sh s5, 2(s1) ; RV32I-NEXT: sh s2, 2(s3)
; RV32I-NEXT: sh s4, 0(s1) ; RV32I-NEXT: sh s4, 0(s3)
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_urem_vec_1: ; RV32IM-LABEL: fold_urem_vec_1:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lhu a6, 12(a1) ; RV32IM-NEXT: lhu a2, 12(a1)
; RV32IM-NEXT: lhu a3, 8(a1) ; RV32IM-NEXT: lhu a3, 8(a1)
; RV32IM-NEXT: lhu a4, 0(a1) ; RV32IM-NEXT: lhu a4, 0(a1)
; RV32IM-NEXT: lhu a1, 4(a1) ; RV32IM-NEXT: lhu a1, 4(a1)
; RV32IM-NEXT: lui a5, 364242 ; RV32IM-NEXT: lui a5, 364242
; RV32IM-NEXT: addi a5, a5, 777 ; RV32IM-NEXT: addi a5, a5, 777
; RV32IM-NEXT: mulhu a5, a4, a5 ; RV32IM-NEXT: mulhu a5, a4, a5
; RV32IM-NEXT: sub a2, a4, a5 ; RV32IM-NEXT: sub a6, a4, a5
; RV32IM-NEXT: srli a2, a2, 1 ; RV32IM-NEXT: srli a6, a6, 1
; RV32IM-NEXT: add a2, a2, a5 ; RV32IM-NEXT: add a5, a6, a5
; RV32IM-NEXT: srli a2, a2, 6 ; RV32IM-NEXT: srli a5, a5, 6
; RV32IM-NEXT: li a5, 95 ; RV32IM-NEXT: li a6, 95
; RV32IM-NEXT: mul a2, a2, a5 ; RV32IM-NEXT: mul a5, a5, a6
; RV32IM-NEXT: sub a2, a4, a2 ; RV32IM-NEXT: sub a4, a4, a5
; RV32IM-NEXT: srli a4, a1, 2 ; RV32IM-NEXT: srli a5, a1, 2
; RV32IM-NEXT: lui a5, 135300 ; RV32IM-NEXT: lui a6, 135300
; RV32IM-NEXT: addi a5, a5, 529 ; RV32IM-NEXT: addi a6, a6, 529
; RV32IM-NEXT: mulhu a4, a4, a5 ; RV32IM-NEXT: mulhu a5, a5, a6
; RV32IM-NEXT: srli a4, a4, 2 ; RV32IM-NEXT: srli a5, a5, 2
; RV32IM-NEXT: li a5, 124 ; RV32IM-NEXT: li a6, 124
; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: mul a5, a5, a6
; RV32IM-NEXT: sub a1, a1, a4 ; RV32IM-NEXT: sub a1, a1, a5
; RV32IM-NEXT: lui a4, 342392 ; RV32IM-NEXT: lui a5, 342392
; RV32IM-NEXT: addi a4, a4, 669 ; RV32IM-NEXT: addi a5, a5, 669
; RV32IM-NEXT: mulhu a4, a3, a4 ; RV32IM-NEXT: mulhu a5, a3, a5
; RV32IM-NEXT: srli a4, a4, 5 ; RV32IM-NEXT: srli a5, a5, 5
; RV32IM-NEXT: li a5, 98 ; RV32IM-NEXT: li a6, 98
; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: mul a5, a5, a6
; RV32IM-NEXT: sub a3, a3, a4 ; RV32IM-NEXT: sub a3, a3, a5
; RV32IM-NEXT: lui a4, 267633 ; RV32IM-NEXT: lui a5, 267633
; RV32IM-NEXT: addi a4, a4, -1809 ; RV32IM-NEXT: addi a5, a5, -1809
; RV32IM-NEXT: mulhu a4, a6, a4 ; RV32IM-NEXT: mulhu a5, a2, a5
; RV32IM-NEXT: srli a4, a4, 8 ; RV32IM-NEXT: srli a5, a5, 8
; RV32IM-NEXT: li a5, 1003 ; RV32IM-NEXT: li a6, 1003
; RV32IM-NEXT: mul a4, a4, a5 ; RV32IM-NEXT: mul a5, a5, a6
; RV32IM-NEXT: sub a4, a6, a4 ; RV32IM-NEXT: sub a2, a2, a5
; RV32IM-NEXT: sh a4, 6(a0) ; RV32IM-NEXT: sh a2, 6(a0)
; RV32IM-NEXT: sh a3, 4(a0) ; RV32IM-NEXT: sh a3, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh a2, 0(a0) ; RV32IM-NEXT: sh a4, 0(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_urem_vec_1: ; RV64I-LABEL: fold_urem_vec_1:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lhu s0, 24(a1)
; RV64I-NEXT: lhu s2, 24(a1) ; RV64I-NEXT: lhu s1, 16(a1)
; RV64I-NEXT: lhu s3, 16(a1) ; RV64I-NEXT: lhu s2, 8(a1)
; RV64I-NEXT: lhu s0, 8(a1)
; RV64I-NEXT: lhu a2, 0(a1) ; RV64I-NEXT: lhu a2, 0(a1)
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: li a1, 124 ; RV64I-NEXT: li a1, 124
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: li a1, 98 ; RV64I-NEXT: li a1, 98
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: li a1, 1003 ; RV64I-NEXT: li a1, 1003
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: sh a0, 6(s1) ; RV64I-NEXT: sh a0, 6(s3)
; RV64I-NEXT: sh s0, 4(s1) ; RV64I-NEXT: sh s1, 4(s3)
; RV64I-NEXT: sh s5, 2(s1) ; RV64I-NEXT: sh s2, 2(s3)
; RV64I-NEXT: sh s4, 0(s1) ; RV64I-NEXT: sh s4, 0(s3)
; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_urem_vec_1: ; RV64IM-LABEL: fold_urem_vec_1:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lhu a2, 0(a1) ; RV64IM-NEXT: lhu a2, 0(a1)
; RV64IM-NEXT: lui a3, %hi(.LCPI0_0) ; RV64IM-NEXT: lui a3, %hi(.LCPI0_0)
; RV64IM-NEXT: ld a3, %lo(.LCPI0_0)(a3) ; RV64IM-NEXT: ld a3, %lo(.LCPI0_0)(a3)
; RV64IM-NEXT: lhu a6, 24(a1) ; RV64IM-NEXT: lhu a4, 24(a1)
; RV64IM-NEXT: lhu a5, 16(a1) ; RV64IM-NEXT: lhu a5, 16(a1)
; RV64IM-NEXT: lhu a1, 8(a1) ; RV64IM-NEXT: lhu a1, 8(a1)
; RV64IM-NEXT: mulhu a3, a2, a3 ; RV64IM-NEXT: mulhu a3, a2, a3
; RV64IM-NEXT: sub a4, a2, a3 ; RV64IM-NEXT: sub a6, a2, a3
; RV64IM-NEXT: srli a4, a4, 1 ; RV64IM-NEXT: srli a6, a6, 1
; RV64IM-NEXT: add a3, a4, a3 ; RV64IM-NEXT: add a3, a6, a3
; RV64IM-NEXT: srli a3, a3, 6 ; RV64IM-NEXT: srli a3, a3, 6
; RV64IM-NEXT: li a7, 95 ; RV64IM-NEXT: li a6, 95
; RV64IM-NEXT: lui a4, %hi(.LCPI0_1) ; RV64IM-NEXT: lui a7, %hi(.LCPI0_1)
; RV64IM-NEXT: ld a4, %lo(.LCPI0_1)(a4) ; RV64IM-NEXT: ld a7, %lo(.LCPI0_1)(a7)
; RV64IM-NEXT: mulw a3, a3, a7 ; RV64IM-NEXT: mulw a3, a3, a6
; RV64IM-NEXT: subw t0, a2, a3 ; RV64IM-NEXT: subw a2, a2, a3
; RV64IM-NEXT: srli a3, a1, 2 ; RV64IM-NEXT: srli a3, a1, 2
; RV64IM-NEXT: mulhu a3, a3, a4 ; RV64IM-NEXT: mulhu a3, a3, a7
; RV64IM-NEXT: srli a3, a3, 3 ; RV64IM-NEXT: srli a3, a3, 3
; RV64IM-NEXT: li a7, 124 ; RV64IM-NEXT: li a6, 124
; RV64IM-NEXT: lui a4, %hi(.LCPI0_2) ; RV64IM-NEXT: lui a7, %hi(.LCPI0_2)
; RV64IM-NEXT: ld a4, %lo(.LCPI0_2)(a4) ; RV64IM-NEXT: ld a7, %lo(.LCPI0_2)(a7)
; RV64IM-NEXT: mulw a3, a3, a7 ; RV64IM-NEXT: mulw a3, a3, a6
; RV64IM-NEXT: subw a1, a1, a3 ; RV64IM-NEXT: subw a1, a1, a3
; RV64IM-NEXT: srli a3, a5, 1 ; RV64IM-NEXT: srli a3, a5, 1
; RV64IM-NEXT: mulhu a3, a3, a4 ; RV64IM-NEXT: mulhu a3, a3, a7
; RV64IM-NEXT: srli a3, a3, 4 ; RV64IM-NEXT: srli a3, a3, 4
; RV64IM-NEXT: lui a4, %hi(.LCPI0_3) ; RV64IM-NEXT: lui a6, %hi(.LCPI0_3)
; RV64IM-NEXT: ld a4, %lo(.LCPI0_3)(a4) ; RV64IM-NEXT: ld a6, %lo(.LCPI0_3)(a6)
; RV64IM-NEXT: li a2, 98 ; RV64IM-NEXT: li a7, 98
; RV64IM-NEXT: mulw a2, a3, a2 ; RV64IM-NEXT: mulw a3, a3, a7
; RV64IM-NEXT: subw a2, a5, a2 ; RV64IM-NEXT: subw a3, a5, a3
; RV64IM-NEXT: mulhu a3, a6, a4 ; RV64IM-NEXT: mulhu a5, a4, a6
; RV64IM-NEXT: srli a3, a3, 7 ; RV64IM-NEXT: srli a5, a5, 7
; RV64IM-NEXT: li a4, 1003 ; RV64IM-NEXT: li a6, 1003
; RV64IM-NEXT: mulw a3, a3, a4 ; RV64IM-NEXT: mulw a5, a5, a6
; RV64IM-NEXT: subw a3, a6, a3 ; RV64IM-NEXT: subw a4, a4, a5
; RV64IM-NEXT: sh a3, 6(a0) ; RV64IM-NEXT: sh a4, 6(a0)
; RV64IM-NEXT: sh a2, 4(a0) ; RV64IM-NEXT: sh a3, 4(a0)
; RV64IM-NEXT: sh a1, 2(a0) ; RV64IM-NEXT: sh a1, 2(a0)
; RV64IM-NEXT: sh t0, 0(a0) ; RV64IM-NEXT: sh a2, 0(a0)
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003> %1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>
ret <4 x i16> %1 ret <4 x i16> %1
} }
define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) nounwind { define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) nounwind {
; RV32I-LABEL: fold_urem_vec_2: ; RV32I-LABEL: fold_urem_vec_2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: lhu s0, 12(a1)
; RV32I-NEXT: lhu s2, 12(a1) ; RV32I-NEXT: lhu s1, 8(a1)
; RV32I-NEXT: lhu s3, 8(a1) ; RV32I-NEXT: lhu s2, 4(a1)
; RV32I-NEXT: lhu s0, 4(a1)
; RV32I-NEXT: lhu a2, 0(a1) ; RV32I-NEXT: lhu a2, 0(a1)
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: sh a0, 6(s1) ; RV32I-NEXT: sh a0, 6(s3)
; RV32I-NEXT: sh s0, 4(s1) ; RV32I-NEXT: sh s1, 4(s3)
; RV32I-NEXT: sh s5, 2(s1) ; RV32I-NEXT: sh s2, 2(s3)
; RV32I-NEXT: sh s4, 0(s1) ; RV32I-NEXT: sh s4, 0(s3)
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: fold_urem_vec_2: ; RV32IM-LABEL: fold_urem_vec_2:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lhu a6, 12(a1) ; RV32IM-NEXT: lhu a2, 12(a1)
; RV32IM-NEXT: lhu a7, 8(a1) ; RV32IM-NEXT: lhu a3, 8(a1)
; RV32IM-NEXT: lhu a4, 0(a1) ; RV32IM-NEXT: lhu a4, 0(a1)
; RV32IM-NEXT: lhu a1, 4(a1) ; RV32IM-NEXT: lhu a1, 4(a1)
; RV32IM-NEXT: lui a5, 364242 ; RV32IM-NEXT: lui a5, 364242
; RV32IM-NEXT: addi a5, a5, 777 ; RV32IM-NEXT: addi a5, a5, 777
; RV32IM-NEXT: mulhu a2, a4, a5 ; RV32IM-NEXT: mulhu a6, a4, a5
; RV32IM-NEXT: sub a3, a4, a2 ; RV32IM-NEXT: sub a7, a4, a6
; RV32IM-NEXT: srli a3, a3, 1 ; RV32IM-NEXT: srli a7, a7, 1
; RV32IM-NEXT: add a2, a3, a2 ; RV32IM-NEXT: add a6, a7, a6
; RV32IM-NEXT: srli a2, a2, 6 ; RV32IM-NEXT: srli a6, a6, 6
; RV32IM-NEXT: li a3, 95 ; RV32IM-NEXT: li a7, 95
; RV32IM-NEXT: mul a2, a2, a3 ; RV32IM-NEXT: mul a6, a6, a7
; RV32IM-NEXT: sub t0, a4, a2 ; RV32IM-NEXT: sub a4, a4, a6
; RV32IM-NEXT: mulhu a4, a1, a5 ; RV32IM-NEXT: mulhu a6, a1, a5
; RV32IM-NEXT: sub a2, a1, a4 ; RV32IM-NEXT: sub t0, a1, a6
; RV32IM-NEXT: srli a2, a2, 1 ; RV32IM-NEXT: srli t0, t0, 1
; RV32IM-NEXT: add a2, a2, a4 ; RV32IM-NEXT: add a6, t0, a6
; RV32IM-NEXT: srli a2, a2, 6 ; RV32IM-NEXT: srli a6, a6, 6
; RV32IM-NEXT: mul a2, a2, a3 ; RV32IM-NEXT: mul a6, a6, a7
; RV32IM-NEXT: sub a1, a1, a2 ; RV32IM-NEXT: sub a1, a1, a6
; RV32IM-NEXT: mulhu a2, a7, a5 ; RV32IM-NEXT: mulhu a6, a3, a5
; RV32IM-NEXT: sub a4, a7, a2 ; RV32IM-NEXT: sub t0, a3, a6
; RV32IM-NEXT: srli a4, a4, 1 ; RV32IM-NEXT: srli t0, t0, 1
; RV32IM-NEXT: add a2, a4, a2 ; RV32IM-NEXT: add a6, t0, a6
; RV32IM-NEXT: srli a2, a2, 6 ; RV32IM-NEXT: srli a6, a6, 6
; RV32IM-NEXT: mul a2, a2, a3 ; RV32IM-NEXT: mul a6, a6, a7
; RV32IM-NEXT: sub a2, a7, a2 ; RV32IM-NEXT: sub a3, a3, a6
; RV32IM-NEXT: mulhu a4, a6, a5 ; RV32IM-NEXT: mulhu a5, a2, a5
; RV32IM-NEXT: sub a5, a6, a4 ; RV32IM-NEXT: sub a6, a2, a5
; RV32IM-NEXT: srli a5, a5, 1 ; RV32IM-NEXT: srli a6, a6, 1
; RV32IM-NEXT: add a4, a5, a4 ; RV32IM-NEXT: add a5, a6, a5
; RV32IM-NEXT: srli a4, a4, 6 ; RV32IM-NEXT: srli a5, a5, 6
; RV32IM-NEXT: mul a3, a4, a3 ; RV32IM-NEXT: mul a5, a5, a7
; RV32IM-NEXT: sub a3, a6, a3 ; RV32IM-NEXT: sub a2, a2, a5
; RV32IM-NEXT: sh a3, 6(a0) ; RV32IM-NEXT: sh a2, 6(a0)
; RV32IM-NEXT: sh a2, 4(a0) ; RV32IM-NEXT: sh a3, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a1, 2(a0)
; RV32IM-NEXT: sh t0, 0(a0) ; RV32IM-NEXT: sh a4, 0(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: fold_urem_vec_2: ; RV64I-LABEL: fold_urem_vec_2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lhu s0, 24(a1)
; RV64I-NEXT: lhu s2, 24(a1) ; RV64I-NEXT: lhu s1, 16(a1)
; RV64I-NEXT: lhu s3, 16(a1) ; RV64I-NEXT: lhu s2, 8(a1)
; RV64I-NEXT: lhu s0, 8(a1)
; RV64I-NEXT: lhu a2, 0(a1) ; RV64I-NEXT: lhu a2, 0(a1)
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: sh a0, 6(s1) ; RV64I-NEXT: sh a0, 6(s3)
; RV64I-NEXT: sh s0, 4(s1) ; RV64I-NEXT: sh s1, 4(s3)
; RV64I-NEXT: sh s5, 2(s1) ; RV64I-NEXT: sh s2, 2(s3)
; RV64I-NEXT: sh s4, 0(s1) ; RV64I-NEXT: sh s4, 0(s3)
; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: fold_urem_vec_2: ; RV64IM-LABEL: fold_urem_vec_2:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lhu a2, 0(a1) ; RV64IM-NEXT: lhu a2, 0(a1)
; RV64IM-NEXT: lui a3, %hi(.LCPI1_0) ; RV64IM-NEXT: lui a3, %hi(.LCPI1_0)
; RV64IM-NEXT: ld a3, %lo(.LCPI1_0)(a3) ; RV64IM-NEXT: ld a3, %lo(.LCPI1_0)(a3)
; RV64IM-NEXT: lhu a6, 24(a1) ; RV64IM-NEXT: lhu a4, 24(a1)
; RV64IM-NEXT: lhu a7, 16(a1) ; RV64IM-NEXT: lhu a5, 16(a1)
; RV64IM-NEXT: lhu a1, 8(a1) ; RV64IM-NEXT: lhu a1, 8(a1)
; RV64IM-NEXT: mulhu a4, a2, a3 ; RV64IM-NEXT: mulhu a6, a2, a3
; RV64IM-NEXT: sub a5, a2, a4 ; RV64IM-NEXT: sub a7, a2, a6
; RV64IM-NEXT: srli a5, a5, 1 ; RV64IM-NEXT: srli a7, a7, 1
; RV64IM-NEXT: add a4, a5, a4 ; RV64IM-NEXT: add a6, a7, a6
; RV64IM-NEXT: srli a4, a4, 6 ; RV64IM-NEXT: srli a6, a6, 6
; RV64IM-NEXT: li a5, 95 ; RV64IM-NEXT: li a7, 95
; RV64IM-NEXT: mulw a4, a4, a5 ; RV64IM-NEXT: mulw a6, a6, a7
; RV64IM-NEXT: subw t0, a2, a4 ; RV64IM-NEXT: subw a2, a2, a6
; RV64IM-NEXT: mulhu a4, a1, a3 ; RV64IM-NEXT: mulhu a6, a1, a3
; RV64IM-NEXT: sub a2, a1, a4 ; RV64IM-NEXT: sub t0, a1, a6
; RV64IM-NEXT: srli a2, a2, 1 ; RV64IM-NEXT: srli t0, t0, 1
; RV64IM-NEXT: add a2, a2, a4 ; RV64IM-NEXT: add a6, t0, a6
; RV64IM-NEXT: srli a2, a2, 6 ; RV64IM-NEXT: srli a6, a6, 6
; RV64IM-NEXT: mulw a2, a2, a5 ; RV64IM-NEXT: mulw a6, a6, a7
; RV64IM-NEXT: subw a1, a1, a2 ; RV64IM-NEXT: subw a1, a1, a6
; RV64IM-NEXT: mulhu a2, a7, a3 ; RV64IM-NEXT: mulhu a6, a5, a3
; RV64IM-NEXT: sub a4, a7, a2 ; RV64IM-NEXT: sub t0, a5, a6
; RV64IM-NEXT: srli a4, a4, 1 ; RV64IM-NEXT: srli t0, t0, 1
; RV64IM-NEXT: add a2, a4, a2 ; RV64IM-NEXT: add a6, t0, a6
; RV64IM-NEXT: srli a2, a2, 6 ; RV64IM-NEXT: srli a6, a6, 6
; RV64IM-NEXT: mulw a2, a2, a5 ; RV64IM-NEXT: mulw a6, a6, a7
; RV64IM-NEXT: subw a2, a7, a2 ; RV64IM-NEXT: subw a5, a5, a6
; RV64IM-NEXT: mulhu a3, a6, a3 ; RV64IM-NEXT: mulhu a3, a4, a3
; RV64IM-NEXT: sub a4, a6, a3 ; RV64IM-NEXT: sub a6, a4, a3
; RV64IM-NEXT: srli a4, a4, 1 ; RV64IM-NEXT: srli a6, a6, 1
; RV64IM-NEXT: add a3, a4, a3 ; RV64IM-NEXT: add a3, a6, a3
; RV64IM-NEXT: srli a3, a3, 6 ; RV64IM-NEXT: srli a3, a3, 6
; RV64IM-NEXT: mulw a3, a3, a5 ; RV64IM-NEXT: mulw a3, a3, a7
; RV64IM-NEXT: subw a3, a6, a3 ; RV64IM-NEXT: subw a3, a4, a3
; RV64IM-NEXT: sh a3, 6(a0) ; RV64IM-NEXT: sh a3, 6(a0)
; RV64IM-NEXT: sh a2, 4(a0) ; RV64IM-NEXT: sh a5, 4(a0)
; RV64IM-NEXT: sh a1, 2(a0) ; RV64IM-NEXT: sh a1, 2(a0)
; RV64IM-NEXT: sh t0, 0(a0) ; RV64IM-NEXT: sh a2, 0(a0)
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if we can combine urem with udiv. ; Don't fold if we can combine urem with udiv.
define <4 x i16> @combine_urem_udiv(<4 x i16> %x) nounwind { define <4 x i16> @combine_urem_udiv(<4 x i16> %x) nounwind {
; RV32I-LABEL: combine_urem_udiv: ; RV32I-LABEL: combine_urem_udiv:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48 ; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s9, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: lhu s1, 0(a1)
; RV32I-NEXT: lhu s2, 0(a1) ; RV32I-NEXT: lhu s2, 4(a1)
; RV32I-NEXT: lhu s3, 4(a1) ; RV32I-NEXT: lhu s3, 8(a1)
; RV32I-NEXT: lhu s4, 8(a1) ; RV32I-NEXT: lhu s4, 12(a1)
; RV32I-NEXT: lhu s1, 12(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s5, a0 ; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s6, a0 ; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: mv s7, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s8, a0 ; RV32I-NEXT: mv s8, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __udivsi3@plt
; RV32I-NEXT: mv s9, a0
; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: call __udivsi3@plt ; RV32I-NEXT: call __udivsi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s3 ; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __udivsi3@plt ; RV32I-NEXT: call __udivsi3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __udivsi3@plt ; RV32I-NEXT: call __udivsi3@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __udivsi3@plt
; RV32I-NEXT: add a0, s8, a0 ; RV32I-NEXT: add a0, s8, a0
; RV32I-NEXT: add a1, s7, s1 ; RV32I-NEXT: add a1, s7, s2
; RV32I-NEXT: add a2, s6, s4 ; RV32I-NEXT: add a2, s6, s3
; RV32I-NEXT: add a3, s5, s9 ; RV32I-NEXT: add a3, s5, s4
; RV32I-NEXT: sh a3, 6(s0) ; RV32I-NEXT: sh a3, 6(s0)
; RV32I-NEXT: sh a2, 4(s0) ; RV32I-NEXT: sh a2, 4(s0)
; RV32I-NEXT: sh a1, 2(s0) ; RV32I-NEXT: sh a1, 2(s0)
; RV32I-NEXT: sh a0, 0(s0) ; RV32I-NEXT: sh a0, 0(s0)
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: combine_urem_udiv: ; RV32IM-LABEL: combine_urem_udiv:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lhu a6, 0(a1) ; RV32IM-NEXT: lhu a2, 0(a1)
; RV32IM-NEXT: lhu a7, 4(a1) ; RV32IM-NEXT: lhu a3, 4(a1)
; RV32IM-NEXT: lhu a4, 12(a1) ; RV32IM-NEXT: lhu a4, 12(a1)
; RV32IM-NEXT: lhu a1, 8(a1) ; RV32IM-NEXT: lhu a1, 8(a1)
; RV32IM-NEXT: lui a5, 364242 ; RV32IM-NEXT: lui a5, 364242
; RV32IM-NEXT: addi a5, a5, 777 ; RV32IM-NEXT: addi a5, a5, 777
; RV32IM-NEXT: mulhu a2, a4, a5 ; RV32IM-NEXT: mulhu a6, a4, a5
; RV32IM-NEXT: sub a3, a4, a2 ; RV32IM-NEXT: sub a7, a4, a6
; RV32IM-NEXT: srli a3, a3, 1 ; RV32IM-NEXT: srli a7, a7, 1
; RV32IM-NEXT: add a2, a3, a2 ; RV32IM-NEXT: add a6, a7, a6
; RV32IM-NEXT: srli t3, a2, 6 ; RV32IM-NEXT: srli a6, a6, 6
; RV32IM-NEXT: li t0, 95 ; RV32IM-NEXT: li a7, 95
; RV32IM-NEXT: mul a3, t3, t0 ; RV32IM-NEXT: mul t0, a6, a7
; RV32IM-NEXT: sub t1, a4, a3 ; RV32IM-NEXT: sub a4, a4, t0
; RV32IM-NEXT: mulhu a4, a1, a5 ; RV32IM-NEXT: mulhu t0, a1, a5
; RV32IM-NEXT: sub a3, a1, a4 ; RV32IM-NEXT: sub t1, a1, t0
; RV32IM-NEXT: srli a3, a3, 1 ; RV32IM-NEXT: srli t1, t1, 1
; RV32IM-NEXT: add a3, a3, a4 ; RV32IM-NEXT: add t0, t1, t0
; RV32IM-NEXT: srli a3, a3, 6 ; RV32IM-NEXT: srli t0, t0, 6
; RV32IM-NEXT: mul a4, a3, t0 ; RV32IM-NEXT: mul t1, t0, a7
; RV32IM-NEXT: sub t2, a1, a4 ; RV32IM-NEXT: sub a1, a1, t1
; RV32IM-NEXT: mulhu a4, a7, a5 ; RV32IM-NEXT: mulhu t1, a3, a5
; RV32IM-NEXT: sub a1, a7, a4 ; RV32IM-NEXT: sub t2, a3, t1
; RV32IM-NEXT: srli a1, a1, 1 ; RV32IM-NEXT: srli t2, t2, 1
; RV32IM-NEXT: add a1, a1, a4 ; RV32IM-NEXT: add t1, t2, t1
; RV32IM-NEXT: srli a1, a1, 6 ; RV32IM-NEXT: srli t1, t1, 6
; RV32IM-NEXT: mul a4, a1, t0 ; RV32IM-NEXT: mul t2, t1, a7
; RV32IM-NEXT: sub a4, a7, a4 ; RV32IM-NEXT: sub a3, a3, t2
; RV32IM-NEXT: mulhu a5, a6, a5 ; RV32IM-NEXT: mulhu a5, a2, a5
; RV32IM-NEXT: sub a2, a6, a5 ; RV32IM-NEXT: sub t2, a2, a5
; RV32IM-NEXT: srli a2, a2, 1 ; RV32IM-NEXT: srli t2, t2, 1
; RV32IM-NEXT: add a5, t2, a5
; RV32IM-NEXT: srli a5, a5, 6
; RV32IM-NEXT: mul a7, a5, a7
; RV32IM-NEXT: sub a2, a2, a7
; RV32IM-NEXT: add a2, a2, a5 ; RV32IM-NEXT: add a2, a2, a5
; RV32IM-NEXT: srli a2, a2, 6 ; RV32IM-NEXT: add a3, a3, t1
; RV32IM-NEXT: mul a5, a2, t0 ; RV32IM-NEXT: add a1, a1, t0
; RV32IM-NEXT: sub a5, a6, a5 ; RV32IM-NEXT: add a4, a4, a6
; RV32IM-NEXT: add a2, a5, a2
; RV32IM-NEXT: add a1, a4, a1
; RV32IM-NEXT: add a3, t2, a3
; RV32IM-NEXT: add a4, t1, t3
; RV32IM-NEXT: sh a4, 6(a0) ; RV32IM-NEXT: sh a4, 6(a0)
; RV32IM-NEXT: sh a3, 4(a0) ; RV32IM-NEXT: sh a1, 4(a0)
; RV32IM-NEXT: sh a1, 2(a0) ; RV32IM-NEXT: sh a3, 2(a0)
; RV32IM-NEXT: sh a2, 0(a0) ; RV32IM-NEXT: sh a2, 0(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: combine_urem_udiv: ; RV64I-LABEL: combine_urem_udiv:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -96 ; RV64I-NEXT: addi sp, sp, -80
; RV64I-NEXT: sd ra, 88(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 80(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 72(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 64(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 56(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 48(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s4, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s5, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s5, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s6, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s6, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s7, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s7, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s8, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s8, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s9, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: lhu s1, 0(a1)
; RV64I-NEXT: lhu s2, 0(a1) ; RV64I-NEXT: lhu s2, 8(a1)
; RV64I-NEXT: lhu s3, 8(a1) ; RV64I-NEXT: lhu s3, 16(a1)
; RV64I-NEXT: lhu s4, 16(a1) ; RV64I-NEXT: lhu s4, 24(a1)
; RV64I-NEXT: lhu s1, 24(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s5, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s6, a0 ; RV64I-NEXT: mv s6, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s7, a0 ; RV64I-NEXT: mv s7, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s8, a0 ; RV64I-NEXT: mv s8, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __udivdi3@plt
; RV64I-NEXT: mv s9, a0
; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s4 ; RV64I-NEXT: mv a0, s4
; RV64I-NEXT: call __udivdi3@plt ; RV64I-NEXT: call __udivdi3@plt
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s3 ; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __udivdi3@plt ; RV64I-NEXT: call __udivdi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __udivdi3@plt ; RV64I-NEXT: call __udivdi3@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __udivdi3@plt
; RV64I-NEXT: addw a0, s8, a0 ; RV64I-NEXT: addw a0, s8, a0
; RV64I-NEXT: addw a1, s7, s1 ; RV64I-NEXT: addw a1, s7, s2
; RV64I-NEXT: addw a2, s6, s4 ; RV64I-NEXT: addw a2, s6, s3
; RV64I-NEXT: addw a3, s5, s9 ; RV64I-NEXT: addw a3, s5, s4
; RV64I-NEXT: sh a3, 6(s0) ; RV64I-NEXT: sh a3, 6(s0)
; RV64I-NEXT: sh a2, 4(s0) ; RV64I-NEXT: sh a2, 4(s0)
; RV64I-NEXT: sh a1, 2(s0) ; RV64I-NEXT: sh a1, 2(s0)
; RV64I-NEXT: sh a0, 0(s0) ; RV64I-NEXT: sh a0, 0(s0)
; RV64I-NEXT: ld ra, 88(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 80(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 72(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 64(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 48(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 56(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 48(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s4, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s5, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s5, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s6, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s6, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s7, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s7, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s8, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s8, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s9, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 80
; RV64I-NEXT: addi sp, sp, 96
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: combine_urem_udiv: ; RV64IM-LABEL: combine_urem_udiv:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lhu a2, 24(a1) ; RV64IM-NEXT: lhu a2, 24(a1)
; RV64IM-NEXT: lui a3, %hi(.LCPI2_0) ; RV64IM-NEXT: lui a3, %hi(.LCPI2_0)
; RV64IM-NEXT: ld a3, %lo(.LCPI2_0)(a3) ; RV64IM-NEXT: ld a3, %lo(.LCPI2_0)(a3)
; RV64IM-NEXT: lhu a6, 0(a1) ; RV64IM-NEXT: lhu a4, 0(a1)
; RV64IM-NEXT: lhu a7, 8(a1) ; RV64IM-NEXT: lhu a5, 8(a1)
; RV64IM-NEXT: lhu a1, 16(a1) ; RV64IM-NEXT: lhu a1, 16(a1)
; RV64IM-NEXT: mulhu a4, a2, a3 ; RV64IM-NEXT: mulhu a6, a2, a3
; RV64IM-NEXT: sub a5, a2, a4 ; RV64IM-NEXT: sub a7, a2, a6
; RV64IM-NEXT: srli a5, a5, 1 ; RV64IM-NEXT: srli a7, a7, 1
; RV64IM-NEXT: add a4, a5, a4 ; RV64IM-NEXT: add a6, a7, a6
; RV64IM-NEXT: srli t3, a4, 6 ; RV64IM-NEXT: srli a6, a6, 6
; RV64IM-NEXT: li t0, 95 ; RV64IM-NEXT: li a7, 95
; RV64IM-NEXT: mulw a5, t3, t0 ; RV64IM-NEXT: mulw t0, a6, a7
; RV64IM-NEXT: subw t1, a2, a5 ; RV64IM-NEXT: subw a2, a2, t0
; RV64IM-NEXT: mulhu a5, a1, a3 ; RV64IM-NEXT: mulhu t0, a1, a3
; RV64IM-NEXT: sub a2, a1, a5 ; RV64IM-NEXT: sub t1, a1, t0
; RV64IM-NEXT: srli a2, a2, 1 ; RV64IM-NEXT: srli t1, t1, 1
; RV64IM-NEXT: add a2, a2, a5 ; RV64IM-NEXT: add t0, t1, t0
; RV64IM-NEXT: srli a2, a2, 6 ; RV64IM-NEXT: srli t0, t0, 6
; RV64IM-NEXT: mulw a5, a2, t0 ; RV64IM-NEXT: mulw t1, t0, a7
; RV64IM-NEXT: subw t2, a1, a5 ; RV64IM-NEXT: subw a1, a1, t1
; RV64IM-NEXT: mulhu a5, a7, a3 ; RV64IM-NEXT: mulhu t1, a5, a3
; RV64IM-NEXT: sub a1, a7, a5 ; RV64IM-NEXT: sub t2, a5, t1
; RV64IM-NEXT: srli a1, a1, 1 ; RV64IM-NEXT: srli t2, t2, 1
; RV64IM-NEXT: add a1, a1, a5 ; RV64IM-NEXT: add t1, t2, t1
; RV64IM-NEXT: srli a1, a1, 6 ; RV64IM-NEXT: srli t1, t1, 6
; RV64IM-NEXT: mulw a5, a1, t0 ; RV64IM-NEXT: mulw t2, t1, a7
; RV64IM-NEXT: subw a5, a7, a5 ; RV64IM-NEXT: subw a5, a5, t2
; RV64IM-NEXT: mulhu a3, a6, a3 ; RV64IM-NEXT: mulhu a3, a4, a3
; RV64IM-NEXT: sub a4, a6, a3 ; RV64IM-NEXT: sub t2, a4, a3
; RV64IM-NEXT: srli a4, a4, 1 ; RV64IM-NEXT: srli t2, t2, 1
; RV64IM-NEXT: add a3, a4, a3 ; RV64IM-NEXT: add a3, t2, a3
; RV64IM-NEXT: srli a3, a3, 6 ; RV64IM-NEXT: srli a3, a3, 6
; RV64IM-NEXT: mulw a4, a3, t0 ; RV64IM-NEXT: mulw a7, a3, a7
; RV64IM-NEXT: subw a4, a6, a4 ; RV64IM-NEXT: subw a4, a4, a7
; RV64IM-NEXT: addw a3, a4, a3 ; RV64IM-NEXT: addw a3, a4, a3
; RV64IM-NEXT: addw a1, a5, a1 ; RV64IM-NEXT: addw a4, a5, t1
; RV64IM-NEXT: addw a2, t2, a2 ; RV64IM-NEXT: addw a1, a1, t0
; RV64IM-NEXT: addw a4, t1, t3 ; RV64IM-NEXT: addw a2, a2, a6
; RV64IM-NEXT: sh a4, 6(a0) ; RV64IM-NEXT: sh a2, 6(a0)
; RV64IM-NEXT: sh a2, 4(a0) ; RV64IM-NEXT: sh a1, 4(a0)
; RV64IM-NEXT: sh a1, 2(a0) ; RV64IM-NEXT: sh a4, 2(a0)
; RV64IM-NEXT: sh a3, 0(a0) ; RV64IM-NEXT: sh a3, 0(a0)
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
%2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95> %2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
%3 = add <4 x i16> %1, %2 %3 = add <4 x i16> %1, %2
ret <4 x i16> %3 ret <4 x i16> %3
} }
; Don't fold for divisors that are a power of two. ; Don't fold for divisors that are a power of two.
define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) nounwind { define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) nounwind {
; RV32I-LABEL: dont_fold_urem_power_of_two: ; RV32I-LABEL: dont_fold_urem_power_of_two:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lhu s2, 8(a1) ; RV32I-NEXT: lhu s1, 8(a1)
; RV32I-NEXT: lhu s3, 4(a1) ; RV32I-NEXT: lhu s2, 4(a1)
; RV32I-NEXT: lhu s1, 0(a1) ; RV32I-NEXT: lhu s3, 0(a1)
; RV32I-NEXT: lhu a2, 12(a1) ; RV32I-NEXT: lhu a2, 12(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 95 ; RV32I-NEXT: li a1, 95
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: andi a1, s1, 63 ; RV32I-NEXT: andi a1, s3, 63
; RV32I-NEXT: andi a2, s3, 31 ; RV32I-NEXT: andi a2, s2, 31
; RV32I-NEXT: andi a3, s2, 7 ; RV32I-NEXT: andi a3, s1, 7
; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh a0, 6(s0)
; RV32I-NEXT: sh a3, 4(s0) ; RV32I-NEXT: sh a3, 4(s0)
; RV32I-NEXT: sh a2, 2(s0) ; RV32I-NEXT: sh a2, 2(s0)
; RV32I-NEXT: sh a1, 0(s0) ; RV32I-NEXT: sh a1, 0(s0)
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_urem_power_of_two: ; RV32IM-LABEL: dont_fold_urem_power_of_two:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: lhu a6, 8(a1) ; RV32IM-NEXT: lhu a2, 8(a1)
; RV32IM-NEXT: lhu a3, 4(a1) ; RV32IM-NEXT: lhu a3, 4(a1)
; RV32IM-NEXT: lhu a4, 12(a1) ; RV32IM-NEXT: lhu a4, 12(a1)
; RV32IM-NEXT: lhu a1, 0(a1) ; RV32IM-NEXT: lhu a1, 0(a1)
; RV32IM-NEXT: lui a5, 364242 ; RV32IM-NEXT: lui a5, 364242
; RV32IM-NEXT: addi a5, a5, 777 ; RV32IM-NEXT: addi a5, a5, 777
; RV32IM-NEXT: mulhu a5, a4, a5 ; RV32IM-NEXT: mulhu a5, a4, a5
; RV32IM-NEXT: sub a2, a4, a5 ; RV32IM-NEXT: sub a6, a4, a5
; RV32IM-NEXT: srli a2, a2, 1 ; RV32IM-NEXT: srli a6, a6, 1
; RV32IM-NEXT: add a2, a2, a5 ; RV32IM-NEXT: add a5, a6, a5
; RV32IM-NEXT: srli a2, a2, 6 ; RV32IM-NEXT: srli a5, a5, 6
; RV32IM-NEXT: li a5, 95 ; RV32IM-NEXT: li a6, 95
; RV32IM-NEXT: mul a2, a2, a5 ; RV32IM-NEXT: mul a5, a5, a6
; RV32IM-NEXT: sub a2, a4, a2 ; RV32IM-NEXT: sub a4, a4, a5
; RV32IM-NEXT: andi a1, a1, 63 ; RV32IM-NEXT: andi a1, a1, 63
; RV32IM-NEXT: andi a3, a3, 31 ; RV32IM-NEXT: andi a3, a3, 31
; RV32IM-NEXT: andi a4, a6, 7 ; RV32IM-NEXT: andi a2, a2, 7
; RV32IM-NEXT: sh a4, 4(a0) ; RV32IM-NEXT: sh a2, 4(a0)
; RV32IM-NEXT: sh a3, 2(a0) ; RV32IM-NEXT: sh a3, 2(a0)
; RV32IM-NEXT: sh a1, 0(a0) ; RV32IM-NEXT: sh a1, 0(a0)
; RV32IM-NEXT: sh a2, 6(a0) ; RV32IM-NEXT: sh a4, 6(a0)
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_urem_power_of_two: ; RV64I-LABEL: dont_fold_urem_power_of_two:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lhu s2, 16(a1) ; RV64I-NEXT: lhu s1, 16(a1)
; RV64I-NEXT: lhu s3, 8(a1) ; RV64I-NEXT: lhu s2, 8(a1)
; RV64I-NEXT: lhu s1, 0(a1) ; RV64I-NEXT: lhu s3, 0(a1)
; RV64I-NEXT: lhu a2, 24(a1) ; RV64I-NEXT: lhu a2, 24(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 95 ; RV64I-NEXT: li a1, 95
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: andi a1, s1, 63 ; RV64I-NEXT: andi a1, s3, 63
; RV64I-NEXT: andi a2, s3, 31 ; RV64I-NEXT: andi a2, s2, 31
; RV64I-NEXT: andi a3, s2, 7 ; RV64I-NEXT: andi a3, s1, 7
; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh a0, 6(s0)
; RV64I-NEXT: sh a3, 4(s0) ; RV64I-NEXT: sh a3, 4(s0)
; RV64I-NEXT: sh a2, 2(s0) ; RV64I-NEXT: sh a2, 2(s0)
; RV64I-NEXT: sh a1, 0(s0) ; RV64I-NEXT: sh a1, 0(s0)
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_urem_power_of_two: ; RV64IM-LABEL: dont_fold_urem_power_of_two:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lhu a2, 24(a1) ; RV64IM-NEXT: lhu a2, 24(a1)
; RV64IM-NEXT: lui a3, %hi(.LCPI3_0) ; RV64IM-NEXT: lui a3, %hi(.LCPI3_0)
; RV64IM-NEXT: ld a3, %lo(.LCPI3_0)(a3) ; RV64IM-NEXT: ld a3, %lo(.LCPI3_0)(a3)
; RV64IM-NEXT: lhu a6, 16(a1) ; RV64IM-NEXT: lhu a4, 16(a1)
; RV64IM-NEXT: lhu a5, 8(a1) ; RV64IM-NEXT: lhu a5, 8(a1)
; RV64IM-NEXT: lhu a1, 0(a1) ; RV64IM-NEXT: lhu a1, 0(a1)
; RV64IM-NEXT: mulhu a3, a2, a3 ; RV64IM-NEXT: mulhu a3, a2, a3
; RV64IM-NEXT: sub a4, a2, a3 ; RV64IM-NEXT: sub a6, a2, a3
; RV64IM-NEXT: srli a4, a4, 1 ; RV64IM-NEXT: srli a6, a6, 1
; RV64IM-NEXT: add a3, a4, a3 ; RV64IM-NEXT: add a3, a6, a3
; RV64IM-NEXT: srli a3, a3, 6 ; RV64IM-NEXT: srli a3, a3, 6
; RV64IM-NEXT: li a4, 95 ; RV64IM-NEXT: li a6, 95
; RV64IM-NEXT: mulw a3, a3, a4 ; RV64IM-NEXT: mulw a3, a3, a6
; RV64IM-NEXT: subw a2, a2, a3 ; RV64IM-NEXT: subw a2, a2, a3
; RV64IM-NEXT: andi a1, a1, 63 ; RV64IM-NEXT: andi a1, a1, 63
; RV64IM-NEXT: andi a3, a5, 31 ; RV64IM-NEXT: andi a3, a5, 31
; RV64IM-NEXT: andi a4, a6, 7 ; RV64IM-NEXT: andi a4, a4, 7
; RV64IM-NEXT: sh a4, 4(a0) ; RV64IM-NEXT: sh a4, 4(a0)
; RV64IM-NEXT: sh a3, 2(a0) ; RV64IM-NEXT: sh a3, 2(a0)
; RV64IM-NEXT: sh a1, 0(a0) ; RV64IM-NEXT: sh a1, 0(a0)
; RV64IM-NEXT: sh a2, 6(a0) ; RV64IM-NEXT: sh a2, 6(a0)
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95> %1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is one. ; Don't fold if the divisor is one.
define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) nounwind { define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) nounwind {
; RV32I-LABEL: dont_fold_urem_one: ; RV32I-LABEL: dont_fold_urem_one:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lhu s2, 12(a1) ; RV32I-NEXT: lhu s0, 12(a1)
; RV32I-NEXT: lhu s1, 8(a1) ; RV32I-NEXT: lhu s1, 8(a1)
; RV32I-NEXT: lhu a2, 4(a1) ; RV32I-NEXT: lhu a2, 4(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: li a1, 654 ; RV32I-NEXT: li a1, 654
; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: li a1, 23 ; RV32I-NEXT: li a1, 23
; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a1, a0, 1327 ; RV32I-NEXT: addi a1, a0, 1327
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __umodsi3@plt ; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: sh a0, 6(s0) ; RV32I-NEXT: sh a0, 6(s2)
; RV32I-NEXT: sh s1, 4(s0) ; RV32I-NEXT: sh s1, 4(s2)
; RV32I-NEXT: sh s3, 2(s0) ; RV32I-NEXT: sh s3, 2(s2)
; RV32I-NEXT: sh zero, 0(s0) ; RV32I-NEXT: sh zero, 0(s2)
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
Show All 34 Lines
; RV64I-LABEL: dont_fold_urem_one: ; RV64I-LABEL: dont_fold_urem_one:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lhu s2, 24(a1) ; RV64I-NEXT: lhu s0, 24(a1)
; RV64I-NEXT: lhu s1, 16(a1) ; RV64I-NEXT: lhu s1, 16(a1)
; RV64I-NEXT: lhu a2, 8(a1) ; RV64I-NEXT: lhu a2, 8(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: li a1, 654 ; RV64I-NEXT: li a1, 654
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: li a1, 23 ; RV64I-NEXT: li a1, 23
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: addiw a1, a0, 1327
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: sh a0, 6(s0) ; RV64I-NEXT: sh a0, 6(s2)
; RV64I-NEXT: sh s1, 4(s0) ; RV64I-NEXT: sh s1, 4(s2)
; RV64I-NEXT: sh s3, 2(s0) ; RV64I-NEXT: sh s3, 2(s2)
; RV64I-NEXT: sh zero, 0(s0) ; RV64I-NEXT: sh zero, 0(s2)
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_urem_one: ; RV64IM-LABEL: dont_fold_urem_one:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: lhu a2, 16(a1) ; RV64IM-NEXT: lhu a2, 16(a1)
; RV64IM-NEXT: lui a3, %hi(.LCPI4_0) ; RV64IM-NEXT: lui a3, %hi(.LCPI4_0)
; RV64IM-NEXT: ld a3, %lo(.LCPI4_0)(a3) ; RV64IM-NEXT: ld a3, %lo(.LCPI4_0)(a3)
; RV64IM-NEXT: lhu a4, 24(a1) ; RV64IM-NEXT: lhu a4, 24(a1)
; RV64IM-NEXT: lhu a1, 8(a1) ; RV64IM-NEXT: lhu a1, 8(a1)
; RV64IM-NEXT: mulhu a3, a2, a3 ; RV64IM-NEXT: mulhu a3, a2, a3
; RV64IM-NEXT: sub a5, a2, a3 ; RV64IM-NEXT: sub a5, a2, a3
; RV64IM-NEXT: srli a5, a5, 1 ; RV64IM-NEXT: srli a5, a5, 1
; RV64IM-NEXT: add a3, a5, a3 ; RV64IM-NEXT: add a3, a5, a3
; RV64IM-NEXT: srli a3, a3, 4 ; RV64IM-NEXT: srli a3, a3, 4
; RV64IM-NEXT: li a6, 23 ; RV64IM-NEXT: li a5, 23
; RV64IM-NEXT: lui a5, %hi(.LCPI4_1) ; RV64IM-NEXT: lui a6, %hi(.LCPI4_1)
; RV64IM-NEXT: ld a5, %lo(.LCPI4_1)(a5) ; RV64IM-NEXT: ld a6, %lo(.LCPI4_1)(a6)
; RV64IM-NEXT: mulw a3, a3, a6 ; RV64IM-NEXT: mulw a3, a3, a5
; RV64IM-NEXT: subw a6, a2, a3 ; RV64IM-NEXT: subw a2, a2, a3
; RV64IM-NEXT: srli a3, a1, 1 ; RV64IM-NEXT: srli a3, a1, 1
; RV64IM-NEXT: mulhu a3, a3, a5 ; RV64IM-NEXT: mulhu a3, a3, a6
; RV64IM-NEXT: srli a3, a3, 7 ; RV64IM-NEXT: srli a3, a3, 7
; RV64IM-NEXT: lui a5, %hi(.LCPI4_2) ; RV64IM-NEXT: lui a5, %hi(.LCPI4_2)
; RV64IM-NEXT: ld a5, %lo(.LCPI4_2)(a5) ; RV64IM-NEXT: ld a5, %lo(.LCPI4_2)(a5)
; RV64IM-NEXT: li a2, 654 ; RV64IM-NEXT: li a6, 654
; RV64IM-NEXT: mulw a2, a3, a2 ; RV64IM-NEXT: mulw a3, a3, a6
; RV64IM-NEXT: subw a1, a1, a2 ; RV64IM-NEXT: subw a1, a1, a3
; RV64IM-NEXT: mulhu a2, a4, a5 ; RV64IM-NEXT: mulhu a3, a4, a5
; RV64IM-NEXT: srli a2, a2, 12 ; RV64IM-NEXT: srli a3, a3, 12
; RV64IM-NEXT: lui a3, 1 ; RV64IM-NEXT: lui a5, 1
; RV64IM-NEXT: addiw a3, a3, 1327 ; RV64IM-NEXT: addiw a5, a5, 1327
; RV64IM-NEXT: mulw a2, a2, a3 ; RV64IM-NEXT: mulw a3, a3, a5
; RV64IM-NEXT: subw a2, a4, a2 ; RV64IM-NEXT: subw a3, a4, a3
; RV64IM-NEXT: sh zero, 0(a0) ; RV64IM-NEXT: sh zero, 0(a0)
; RV64IM-NEXT: sh a2, 6(a0) ; RV64IM-NEXT: sh a3, 6(a0)
; RV64IM-NEXT: sh a1, 2(a0) ; RV64IM-NEXT: sh a1, 2(a0)
; RV64IM-NEXT: sh a6, 4(a0) ; RV64IM-NEXT: sh a2, 4(a0)
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423> %1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
ret <4 x i16> %1 ret <4 x i16> %1
} }
; Don't fold if the divisor is 2^16. ; Don't fold if the divisor is 2^16.
define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind { define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) nounwind {
; CHECK-LABEL: dont_fold_urem_i16_smax: ; CHECK-LABEL: dont_fold_urem_i16_smax:
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; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s9, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw s0, 24(a1)
; RV32I-NEXT: lw s2, 24(a1) ; RV32I-NEXT: lw s1, 28(a1)
; RV32I-NEXT: lw s3, 28(a1) ; RV32I-NEXT: lw s2, 16(a1)
; RV32I-NEXT: lw s4, 16(a1) ; RV32I-NEXT: lw s3, 20(a1)
; RV32I-NEXT: lw s5, 20(a1) ; RV32I-NEXT: lw s4, 8(a1)
; RV32I-NEXT: lw s6, 8(a1) ; RV32I-NEXT: lw s5, 12(a1)
; RV32I-NEXT: lw s1, 12(a1)
; RV32I-NEXT: lw a3, 0(a1) ; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a1, 4(a1) ; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: mv s0, a0 ; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: li a2, 1 ; RV32I-NEXT: li a2, 1
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __umoddi3@plt ; RV32I-NEXT: call __umoddi3@plt
; RV32I-NEXT: mv s7, a0 ; RV32I-NEXT: mv s7, a0
; RV32I-NEXT: mv s8, a1 ; RV32I-NEXT: mv s8, a1
; RV32I-NEXT: li a2, 654 ; RV32I-NEXT: li a2, 654
; RV32I-NEXT: mv a0, s6
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __umoddi3@plt
; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: mv s9, a1
; RV32I-NEXT: li a2, 23
; RV32I-NEXT: mv a0, s4 ; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s5 ; RV32I-NEXT: mv a1, s5
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __umoddi3@plt ; RV32I-NEXT: call __umoddi3@plt
; RV32I-NEXT: mv s4, a0 ; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: lui a0, 1 ; RV32I-NEXT: li a2, 23
; RV32I-NEXT: addi a2, a0, 1327
; RV32I-NEXT: mv a0, s2 ; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __umoddi3@plt ; RV32I-NEXT: call __umoddi3@plt
; RV32I-NEXT: sw a1, 28(s0) ; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: sw a0, 24(s0) ; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: sw s1, 20(s0) ; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: sw s4, 16(s0) ; RV32I-NEXT: addi a2, a0, 1327
; RV32I-NEXT: sw s9, 12(s0) ; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: sw s6, 8(s0) ; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: sw s8, 4(s0) ; RV32I-NEXT: li a3, 0
; RV32I-NEXT: sw s7, 0(s0) ; RV32I-NEXT: call __umoddi3@plt
; RV32I-NEXT: sw a1, 28(s6)
; RV32I-NEXT: sw a0, 24(s6)
; RV32I-NEXT: sw s3, 20(s6)
; RV32I-NEXT: sw s2, 16(s6)
; RV32I-NEXT: sw s5, 12(s6)
; RV32I-NEXT: sw s4, 8(s6)
; RV32I-NEXT: sw s8, 4(s6)
; RV32I-NEXT: sw s7, 0(s6)
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48 ; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IM-LABEL: dont_fold_urem_i64: ; RV32IM-LABEL: dont_fold_urem_i64:
; RV32IM: # %bb.0: ; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -48 ; RV32IM-NEXT: addi sp, sp, -48
; RV32IM-NEXT: sw ra, 44(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s0, 40(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s1, 36(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s2, 32(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s3, 28(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s4, 24(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s5, 20(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s6, 16(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s7, 12(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s8, 8(sp) # 4-byte Folded Spill ; RV32IM-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s9, 4(sp) # 4-byte Folded Spill ; RV32IM-NEXT: lw s0, 24(a1)
; RV32IM-NEXT: lw s2, 24(a1) ; RV32IM-NEXT: lw s1, 28(a1)
; RV32IM-NEXT: lw s3, 28(a1) ; RV32IM-NEXT: lw s2, 16(a1)
; RV32IM-NEXT: lw s4, 16(a1) ; RV32IM-NEXT: lw s3, 20(a1)
; RV32IM-NEXT: lw s5, 20(a1) ; RV32IM-NEXT: lw s4, 8(a1)
; RV32IM-NEXT: lw s6, 8(a1) ; RV32IM-NEXT: lw s5, 12(a1)
; RV32IM-NEXT: lw s1, 12(a1)
; RV32IM-NEXT: lw a3, 0(a1) ; RV32IM-NEXT: lw a3, 0(a1)
; RV32IM-NEXT: lw a1, 4(a1) ; RV32IM-NEXT: lw a1, 4(a1)
; RV32IM-NEXT: mv s0, a0 ; RV32IM-NEXT: mv s6, a0
; RV32IM-NEXT: li a2, 1 ; RV32IM-NEXT: li a2, 1
; RV32IM-NEXT: mv a0, a3 ; RV32IM-NEXT: mv a0, a3
; RV32IM-NEXT: li a3, 0 ; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __umoddi3@plt ; RV32IM-NEXT: call __umoddi3@plt
; RV32IM-NEXT: mv s7, a0 ; RV32IM-NEXT: mv s7, a0
; RV32IM-NEXT: mv s8, a1 ; RV32IM-NEXT: mv s8, a1
; RV32IM-NEXT: li a2, 654 ; RV32IM-NEXT: li a2, 654
; RV32IM-NEXT: mv a0, s6
; RV32IM-NEXT: mv a1, s1
; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __umoddi3@plt
; RV32IM-NEXT: mv s6, a0
; RV32IM-NEXT: mv s9, a1
; RV32IM-NEXT: li a2, 23
; RV32IM-NEXT: mv a0, s4 ; RV32IM-NEXT: mv a0, s4
; RV32IM-NEXT: mv a1, s5 ; RV32IM-NEXT: mv a1, s5
; RV32IM-NEXT: li a3, 0 ; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __umoddi3@plt ; RV32IM-NEXT: call __umoddi3@plt
; RV32IM-NEXT: mv s4, a0 ; RV32IM-NEXT: mv s4, a0
; RV32IM-NEXT: mv s1, a1 ; RV32IM-NEXT: mv s5, a1
; RV32IM-NEXT: lui a0, 1 ; RV32IM-NEXT: li a2, 23
; RV32IM-NEXT: addi a2, a0, 1327
; RV32IM-NEXT: mv a0, s2 ; RV32IM-NEXT: mv a0, s2
; RV32IM-NEXT: mv a1, s3 ; RV32IM-NEXT: mv a1, s3
; RV32IM-NEXT: li a3, 0 ; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __umoddi3@plt ; RV32IM-NEXT: call __umoddi3@plt
; RV32IM-NEXT: sw a1, 28(s0) ; RV32IM-NEXT: mv s2, a0
; RV32IM-NEXT: sw a0, 24(s0) ; RV32IM-NEXT: mv s3, a1
; RV32IM-NEXT: sw s1, 20(s0) ; RV32IM-NEXT: lui a0, 1
; RV32IM-NEXT: sw s4, 16(s0) ; RV32IM-NEXT: addi a2, a0, 1327
; RV32IM-NEXT: sw s9, 12(s0) ; RV32IM-NEXT: mv a0, s0
; RV32IM-NEXT: sw s6, 8(s0) ; RV32IM-NEXT: mv a1, s1
; RV32IM-NEXT: sw s8, 4(s0) ; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: sw s7, 0(s0) ; RV32IM-NEXT: call __umoddi3@plt
; RV32IM-NEXT: sw a1, 28(s6)
; RV32IM-NEXT: sw a0, 24(s6)
; RV32IM-NEXT: sw s3, 20(s6)
; RV32IM-NEXT: sw s2, 16(s6)
; RV32IM-NEXT: sw s5, 12(s6)
; RV32IM-NEXT: sw s4, 8(s6)
; RV32IM-NEXT: sw s8, 4(s6)
; RV32IM-NEXT: sw s7, 0(s6)
; RV32IM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s0, 40(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s1, 36(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s2, 32(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s3, 28(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s4, 24(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s5, 20(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s6, 16(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s7, 12(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s8, 8(sp) # 4-byte Folded Reload ; RV32IM-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 48 ; RV32IM-NEXT: addi sp, sp, 48
; RV32IM-NEXT: ret ; RV32IM-NEXT: ret
; ;
; RV64I-LABEL: dont_fold_urem_i64: ; RV64I-LABEL: dont_fold_urem_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48 ; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: ld s2, 24(a1) ; RV64I-NEXT: ld s0, 24(a1)
; RV64I-NEXT: ld s1, 16(a1) ; RV64I-NEXT: ld s1, 16(a1)
; RV64I-NEXT: ld a2, 8(a1) ; RV64I-NEXT: ld a2, 8(a1)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: li a1, 654 ; RV64I-NEXT: li a1, 654
; RV64I-NEXT: mv a0, a2 ; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: li a1, 23 ; RV64I-NEXT: li a1, 23
; RV64I-NEXT: mv a0, s1 ; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 1 ; RV64I-NEXT: lui a0, 1
; RV64I-NEXT: addiw a1, a0, 1327 ; RV64I-NEXT: addiw a1, a0, 1327
; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __umoddi3@plt ; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: sd a0, 24(s0) ; RV64I-NEXT: sd a0, 24(s2)
; RV64I-NEXT: sd s1, 16(s0) ; RV64I-NEXT: sd s1, 16(s2)
; RV64I-NEXT: sd s3, 8(s0) ; RV64I-NEXT: sd s3, 8(s2)
; RV64I-NEXT: sd zero, 0(s0) ; RV64I-NEXT: sd zero, 0(s2)
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48 ; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IM-LABEL: dont_fold_urem_i64: ; RV64IM-LABEL: dont_fold_urem_i64:
; RV64IM: # %bb.0: ; RV64IM: # %bb.0:
; RV64IM-NEXT: ld a2, 16(a1) ; RV64IM-NEXT: ld a2, 16(a1)
; RV64IM-NEXT: lui a3, %hi(.LCPI6_0) ; RV64IM-NEXT: lui a3, %hi(.LCPI6_0)
; RV64IM-NEXT: ld a3, %lo(.LCPI6_0)(a3) ; RV64IM-NEXT: ld a3, %lo(.LCPI6_0)(a3)
; RV64IM-NEXT: ld a4, 24(a1) ; RV64IM-NEXT: ld a4, 24(a1)
; RV64IM-NEXT: ld a1, 8(a1) ; RV64IM-NEXT: ld a1, 8(a1)
; RV64IM-NEXT: mulhu a3, a2, a3 ; RV64IM-NEXT: mulhu a3, a2, a3
; RV64IM-NEXT: sub a5, a2, a3 ; RV64IM-NEXT: sub a5, a2, a3
; RV64IM-NEXT: srli a5, a5, 1 ; RV64IM-NEXT: srli a5, a5, 1
; RV64IM-NEXT: add a3, a5, a3 ; RV64IM-NEXT: add a3, a5, a3
; RV64IM-NEXT: srli a3, a3, 4 ; RV64IM-NEXT: srli a3, a3, 4
; RV64IM-NEXT: li a6, 23 ; RV64IM-NEXT: li a5, 23
; RV64IM-NEXT: lui a5, %hi(.LCPI6_1) ; RV64IM-NEXT: lui a6, %hi(.LCPI6_1)
; RV64IM-NEXT: ld a5, %lo(.LCPI6_1)(a5) ; RV64IM-NEXT: ld a6, %lo(.LCPI6_1)(a6)
; RV64IM-NEXT: mul a3, a3, a6 ; RV64IM-NEXT: mul a3, a3, a5
; RV64IM-NEXT: sub a6, a2, a3 ; RV64IM-NEXT: sub a2, a2, a3
; RV64IM-NEXT: srli a3, a1, 1 ; RV64IM-NEXT: srli a3, a1, 1
; RV64IM-NEXT: mulhu a3, a3, a5 ; RV64IM-NEXT: mulhu a3, a3, a6
; RV64IM-NEXT: srli a3, a3, 7 ; RV64IM-NEXT: srli a3, a3, 7
; RV64IM-NEXT: lui a5, %hi(.LCPI6_2) ; RV64IM-NEXT: lui a5, %hi(.LCPI6_2)
; RV64IM-NEXT: ld a5, %lo(.LCPI6_2)(a5) ; RV64IM-NEXT: ld a5, %lo(.LCPI6_2)(a5)
; RV64IM-NEXT: li a2, 654 ; RV64IM-NEXT: li a6, 654
; RV64IM-NEXT: mul a2, a3, a2 ; RV64IM-NEXT: mul a3, a3, a6
; RV64IM-NEXT: sub a1, a1, a2 ; RV64IM-NEXT: sub a1, a1, a3
; RV64IM-NEXT: mulhu a2, a4, a5 ; RV64IM-NEXT: mulhu a3, a4, a5
; RV64IM-NEXT: srli a2, a2, 12 ; RV64IM-NEXT: srli a3, a3, 12
; RV64IM-NEXT: lui a3, 1 ; RV64IM-NEXT: lui a5, 1
; RV64IM-NEXT: addiw a3, a3, 1327 ; RV64IM-NEXT: addiw a5, a5, 1327
; RV64IM-NEXT: mul a2, a2, a3 ; RV64IM-NEXT: mul a3, a3, a5
; RV64IM-NEXT: sub a2, a4, a2 ; RV64IM-NEXT: sub a3, a4, a3
; RV64IM-NEXT: sd zero, 0(a0) ; RV64IM-NEXT: sd zero, 0(a0)
; RV64IM-NEXT: sd a2, 24(a0) ; RV64IM-NEXT: sd a3, 24(a0)
; RV64IM-NEXT: sd a1, 8(a0) ; RV64IM-NEXT: sd a1, 8(a0)
; RV64IM-NEXT: sd a6, 16(a0) ; RV64IM-NEXT: sd a2, 16(a0)
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423> %1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1 ret <4 x i64> %1
} }

llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll

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define void @vec3_setcc_crash(<3 x i8>* %in, <3 x i8>* %out) { define void @vec3_setcc_crash(<3 x i8>* %in, <3 x i8>* %out) {
; RV32-LABEL: vec3_setcc_crash: ; RV32-LABEL: vec3_setcc_crash:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: lw a0, 0(a0) ; RV32-NEXT: lw a0, 0(a0)
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: and a2, a0, a2 ; RV32-NEXT: and a2, a0, a2
; RV32-NEXT: slli a3, a2, 16 ; RV32-NEXT: slli a3, a2, 16
; RV32-NEXT: srai a6, a3, 24 ; RV32-NEXT: srai a3, a3, 24
; RV32-NEXT: slli a4, a0, 24 ; RV32-NEXT: slli a4, a0, 24
; RV32-NEXT: srai a3, a4, 24 ; RV32-NEXT: srai a6, a4, 24
; RV32-NEXT: slli a4, a0, 8 ; RV32-NEXT: slli a4, a0, 8
; RV32-NEXT: mv a5, a0 ; RV32-NEXT: mv a5, a0
; RV32-NEXT: bgtz a3, .LBB0_2 ; RV32-NEXT: bgtz a6, .LBB0_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a5, 0 ; RV32-NEXT: li a5, 0
; RV32-NEXT: .LBB0_2: ; RV32-NEXT: .LBB0_2:
; RV32-NEXT: srai a4, a4, 24 ; RV32-NEXT: srai a4, a4, 24
; RV32-NEXT: andi a5, a5, 255 ; RV32-NEXT: andi a5, a5, 255
; RV32-NEXT: bgtz a6, .LBB0_4 ; RV32-NEXT: bgtz a3, .LBB0_4
; RV32-NEXT: # %bb.3: ; RV32-NEXT: # %bb.3:
; RV32-NEXT: li a2, 0 ; RV32-NEXT: li a2, 0
; RV32-NEXT: j .LBB0_5 ; RV32-NEXT: j .LBB0_5
; RV32-NEXT: .LBB0_4: ; RV32-NEXT: .LBB0_4:
; RV32-NEXT: srli a2, a2, 8 ; RV32-NEXT: srli a2, a2, 8
; RV32-NEXT: .LBB0_5: ; RV32-NEXT: .LBB0_5:
; RV32-NEXT: slli a2, a2, 8 ; RV32-NEXT: slli a2, a2, 8
; RV32-NEXT: or a2, a5, a2 ; RV32-NEXT: or a2, a5, a2
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; ;
; RV64-LABEL: vec3_setcc_crash: ; RV64-LABEL: vec3_setcc_crash:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lwu a0, 0(a0) ; RV64-NEXT: lwu a0, 0(a0)
; RV64-NEXT: lui a2, 16 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: addiw a2, a2, -256 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: and a2, a0, a2 ; RV64-NEXT: and a2, a0, a2
; RV64-NEXT: slli a3, a2, 48 ; RV64-NEXT: slli a3, a2, 48
; RV64-NEXT: srai a6, a3, 56 ; RV64-NEXT: srai a3, a3, 56
; RV64-NEXT: slli a4, a0, 56 ; RV64-NEXT: slli a4, a0, 56
; RV64-NEXT: srai a3, a4, 56 ; RV64-NEXT: srai a6, a4, 56
; RV64-NEXT: slli a4, a0, 40 ; RV64-NEXT: slli a4, a0, 40
; RV64-NEXT: mv a5, a0 ; RV64-NEXT: mv a5, a0
; RV64-NEXT: bgtz a3, .LBB0_2 ; RV64-NEXT: bgtz a6, .LBB0_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a5, 0 ; RV64-NEXT: li a5, 0
; RV64-NEXT: .LBB0_2: ; RV64-NEXT: .LBB0_2:
; RV64-NEXT: srai a4, a4, 56 ; RV64-NEXT: srai a4, a4, 56
; RV64-NEXT: andi a5, a5, 255 ; RV64-NEXT: andi a5, a5, 255
; RV64-NEXT: bgtz a6, .LBB0_4 ; RV64-NEXT: bgtz a3, .LBB0_4
; RV64-NEXT: # %bb.3: ; RV64-NEXT: # %bb.3:
; RV64-NEXT: li a2, 0 ; RV64-NEXT: li a2, 0
; RV64-NEXT: j .LBB0_5 ; RV64-NEXT: j .LBB0_5
; RV64-NEXT: .LBB0_4: ; RV64-NEXT: .LBB0_4:
; RV64-NEXT: srli a2, a2, 8 ; RV64-NEXT: srli a2, a2, 8
; RV64-NEXT: .LBB0_5: ; RV64-NEXT: .LBB0_5:
; RV64-NEXT: slli a2, a2, 8 ; RV64-NEXT: slli a2, a2, 8
; RV64-NEXT: or a2, a5, a2 ; RV64-NEXT: or a2, a5, a2
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llvm/test/CodeGen/RISCV/xaluo.ll

Show First 20 Lines • Show All 561 Lines • ▼ Show 20 Linesentry:
%obit = extractvalue {i32, i1} %t, 1 %obit = extractvalue {i32, i1} %t, 1
store i32 %val, i32* %res store i32 %val, i32* %res
ret i1 %obit ret i1 %obit
} }
define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) { define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) {
; RV32-LABEL: ssubo.i64: ; RV32-LABEL: ssubo.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: sltu a6, a0, a2 ; RV32-NEXT: sltu a5, a0, a2
; RV32-NEXT: sub a5, a1, a3 ; RV32-NEXT: sub a6, a1, a3
; RV32-NEXT: sub a5, a5, a6 ; RV32-NEXT: sub a5, a6, a5
; RV32-NEXT: xor a6, a1, a5 ; RV32-NEXT: xor a6, a1, a5
; RV32-NEXT: xor a1, a1, a3 ; RV32-NEXT: xor a1, a1, a3
; RV32-NEXT: and a1, a1, a6 ; RV32-NEXT: and a1, a1, a6
; RV32-NEXT: slti a1, a1, 0 ; RV32-NEXT: slti a1, a1, 0
; RV32-NEXT: sub a0, a0, a2 ; RV32-NEXT: sub a0, a0, a2
; RV32-NEXT: sw a0, 0(a4) ; RV32-NEXT: sw a0, 0(a4)
; RV32-NEXT: sw a5, 4(a4) ; RV32-NEXT: sw a5, 4(a4)
; RV32-NEXT: mv a0, a1 ; RV32-NEXT: mv a0, a1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: ssubo.i64: ; RV64-LABEL: ssubo.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: sgtz a3, a1 ; RV64-NEXT: sgtz a3, a1
; RV64-NEXT: sub a1, a0, a1 ; RV64-NEXT: sub a1, a0, a1
; RV64-NEXT: slt a0, a1, a0 ; RV64-NEXT: slt a0, a1, a0
; RV64-NEXT: xor a0, a3, a0 ; RV64-NEXT: xor a0, a3, a0
; RV64-NEXT: sd a1, 0(a2) ; RV64-NEXT: sd a1, 0(a2)
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZBA-LABEL: ssubo.i64: ; RV32ZBA-LABEL: ssubo.i64:
; RV32ZBA: # %bb.0: # %entry ; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: sltu a6, a0, a2 ; RV32ZBA-NEXT: sltu a5, a0, a2
; RV32ZBA-NEXT: sub a5, a1, a3 ; RV32ZBA-NEXT: sub a6, a1, a3
; RV32ZBA-NEXT: sub a5, a5, a6 ; RV32ZBA-NEXT: sub a5, a6, a5
; RV32ZBA-NEXT: xor a6, a1, a5 ; RV32ZBA-NEXT: xor a6, a1, a5
; RV32ZBA-NEXT: xor a1, a1, a3 ; RV32ZBA-NEXT: xor a1, a1, a3
; RV32ZBA-NEXT: and a1, a1, a6 ; RV32ZBA-NEXT: and a1, a1, a6
; RV32ZBA-NEXT: slti a1, a1, 0 ; RV32ZBA-NEXT: slti a1, a1, 0
; RV32ZBA-NEXT: sub a0, a0, a2 ; RV32ZBA-NEXT: sub a0, a0, a2
; RV32ZBA-NEXT: sw a0, 0(a4) ; RV32ZBA-NEXT: sw a0, 0(a4)
; RV32ZBA-NEXT: sw a5, 4(a4) ; RV32ZBA-NEXT: sw a5, 4(a4)
; RV32ZBA-NEXT: mv a0, a1 ; RV32ZBA-NEXT: mv a0, a1
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define zeroext i1 @smulo.i64(i64 %v1, i64 %v2, i64* %res) { define zeroext i1 @smulo.i64(i64 %v1, i64 %v2, i64* %res) {
; RV32-LABEL: smulo.i64: ; RV32-LABEL: smulo.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s1, 8(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s2, 4(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s3, 0(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset s0, -4 ; RV32-NEXT: .cfi_offset s0, -4
; RV32-NEXT: .cfi_offset s1, -8 ; RV32-NEXT: .cfi_offset s1, -8
; RV32-NEXT: .cfi_offset s2, -12 ; RV32-NEXT: mulhu a5, a0, a2
; RV32-NEXT: .cfi_offset s3, -16 ; RV32-NEXT: mul a6, a1, a2
; RV32-NEXT: mulhu a6, a0, a2 ; RV32-NEXT: add a5, a6, a5
; RV32-NEXT: mul a5, a1, a2 ; RV32-NEXT: sltu a6, a5, a6
; RV32-NEXT: add a6, a5, a6 ; RV32-NEXT: mulhu a7, a1, a2
; RV32-NEXT: sltu a7, a6, a5 ; RV32-NEXT: add a6, a7, a6
; RV32-NEXT: mulhu a5, a1, a2 ; RV32-NEXT: mul a7, a0, a3
; RV32-NEXT: add a7, a5, a7 ; RV32-NEXT: add a5, a7, a5
; RV32-NEXT: mul a5, a0, a3 ; RV32-NEXT: sltu a7, a5, a7
; RV32-NEXT: add a6, a5, a6 ; RV32-NEXT: mulhu t0, a0, a3
; RV32-NEXT: sltu t0, a6, a5 ; RV32-NEXT: add a7, t0, a7
; RV32-NEXT: mulhu a5, a0, a3 ; RV32-NEXT: add a7, a6, a7
; RV32-NEXT: add a5, a5, t0 ; RV32-NEXT: mul t0, a1, a3
; RV32-NEXT: add t0, a7, a5 ; RV32-NEXT: add t1, t0, a7
; RV32-NEXT: mul t1, a1, a3
; RV32-NEXT: add a5, t1, t0
; RV32-NEXT: srai t2, a1, 31 ; RV32-NEXT: srai t2, a1, 31
; RV32-NEXT: mul t3, a2, t2 ; RV32-NEXT: mul t3, a2, t2
; RV32-NEXT: srai t4, a3, 31 ; RV32-NEXT: srai t4, a3, 31
; RV32-NEXT: mul t5, t4, a0 ; RV32-NEXT: mul t5, t4, a0
; RV32-NEXT: add t6, t5, t3 ; RV32-NEXT: add t6, t5, t3
; RV32-NEXT: add s3, a5, t6 ; RV32-NEXT: add s0, t1, t6
; RV32-NEXT: sltu s2, s3, a5 ; RV32-NEXT: sltu s1, s0, t1
; RV32-NEXT: sltu a5, a5, t1 ; RV32-NEXT: sltu t0, t1, t0
; RV32-NEXT: sltu s1, t0, a7 ; RV32-NEXT: sltu a6, a7, a6
; RV32-NEXT: mulhu s0, a1, a3 ; RV32-NEXT: mulhu a7, a1, a3
; RV32-NEXT: add s1, s0, s1 ; RV32-NEXT: add a6, a7, a6
; RV32-NEXT: add a5, s1, a5 ; RV32-NEXT: add a6, a6, t0
; RV32-NEXT: mulhu s1, a2, t2 ; RV32-NEXT: mulhu a7, a2, t2
; RV32-NEXT: add s1, s1, t3 ; RV32-NEXT: add a7, a7, t3
; RV32-NEXT: mul a3, a3, t2 ; RV32-NEXT: mul a3, a3, t2
; RV32-NEXT: add a3, s1, a3 ; RV32-NEXT: add a3, a7, a3
; RV32-NEXT: mul a1, t4, a1 ; RV32-NEXT: mul a1, t4, a1
; RV32-NEXT: mulhu s1, t4, a0 ; RV32-NEXT: mulhu a7, t4, a0
; RV32-NEXT: add a1, s1, a1 ; RV32-NEXT: add a1, a7, a1
; RV32-NEXT: add a1, a1, t5 ; RV32-NEXT: add a1, a1, t5
; RV32-NEXT: add a1, a1, a3 ; RV32-NEXT: add a1, a1, a3
; RV32-NEXT: sltu a3, t6, t5 ; RV32-NEXT: sltu a3, t6, t5
; RV32-NEXT: add a1, a1, a3 ; RV32-NEXT: add a1, a1, a3
; RV32-NEXT: add a1, a5, a1 ; RV32-NEXT: add a1, a6, a1
; RV32-NEXT: add a1, a1, s2 ; RV32-NEXT: add a1, a1, s1
; RV32-NEXT: srai a3, a6, 31 ; RV32-NEXT: srai a3, a5, 31
; RV32-NEXT: xor a1, a1, a3 ; RV32-NEXT: xor a1, a1, a3
; RV32-NEXT: xor a3, s3, a3 ; RV32-NEXT: xor a3, s0, a3
; RV32-NEXT: or a1, a3, a1 ; RV32-NEXT: or a1, a3, a1
; RV32-NEXT: snez a1, a1 ; RV32-NEXT: snez a1, a1
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: sw a0, 0(a4) ; RV32-NEXT: sw a0, 0(a4)
; RV32-NEXT: sw a6, 4(a4) ; RV32-NEXT: sw a5, 4(a4)
; RV32-NEXT: mv a0, a1 ; RV32-NEXT: mv a0, a1
; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s3, 0(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: smulo.i64: ; RV64-LABEL: smulo.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: mulh a3, a0, a1 ; RV64-NEXT: mulh a3, a0, a1
; RV64-NEXT: mul a1, a0, a1 ; RV64-NEXT: mul a1, a0, a1
; RV64-NEXT: srai a0, a1, 63 ; RV64-NEXT: srai a0, a1, 63
; RV64-NEXT: xor a0, a3, a0 ; RV64-NEXT: xor a0, a3, a0
; RV64-NEXT: snez a0, a0 ; RV64-NEXT: snez a0, a0
; RV64-NEXT: sd a1, 0(a2) ; RV64-NEXT: sd a1, 0(a2)
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZBA-LABEL: smulo.i64: ; RV32ZBA-LABEL: smulo.i64:
; RV32ZBA: # %bb.0: # %entry ; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: addi sp, sp, -16 ; RV32ZBA-NEXT: addi sp, sp, -16
; RV32ZBA-NEXT: .cfi_def_cfa_offset 16 ; RV32ZBA-NEXT: .cfi_def_cfa_offset 16
; RV32ZBA-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32ZBA-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32ZBA-NEXT: sw s1, 8(sp) # 4-byte Folded Spill ; RV32ZBA-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32ZBA-NEXT: sw s2, 4(sp) # 4-byte Folded Spill
; RV32ZBA-NEXT: sw s3, 0(sp) # 4-byte Folded Spill
; RV32ZBA-NEXT: .cfi_offset s0, -4 ; RV32ZBA-NEXT: .cfi_offset s0, -4
; RV32ZBA-NEXT: .cfi_offset s1, -8 ; RV32ZBA-NEXT: .cfi_offset s1, -8
; RV32ZBA-NEXT: .cfi_offset s2, -12 ; RV32ZBA-NEXT: mulhu a5, a0, a2
; RV32ZBA-NEXT: .cfi_offset s3, -16 ; RV32ZBA-NEXT: mul a6, a1, a2
; RV32ZBA-NEXT: mulhu a6, a0, a2 ; RV32ZBA-NEXT: add a5, a6, a5
; RV32ZBA-NEXT: mul a5, a1, a2 ; RV32ZBA-NEXT: sltu a6, a5, a6
; RV32ZBA-NEXT: add a6, a5, a6 ; RV32ZBA-NEXT: mulhu a7, a1, a2
; RV32ZBA-NEXT: sltu a7, a6, a5 ; RV32ZBA-NEXT: add a6, a7, a6
; RV32ZBA-NEXT: mulhu a5, a1, a2 ; RV32ZBA-NEXT: mul a7, a0, a3
; RV32ZBA-NEXT: add a7, a5, a7 ; RV32ZBA-NEXT: add a5, a7, a5
; RV32ZBA-NEXT: mul a5, a0, a3 ; RV32ZBA-NEXT: sltu a7, a5, a7
; RV32ZBA-NEXT: add a6, a5, a6 ; RV32ZBA-NEXT: mulhu t0, a0, a3
; RV32ZBA-NEXT: sltu t0, a6, a5 ; RV32ZBA-NEXT: add a7, t0, a7
; RV32ZBA-NEXT: mulhu a5, a0, a3 ; RV32ZBA-NEXT: add a7, a6, a7
; RV32ZBA-NEXT: add a5, a5, t0 ; RV32ZBA-NEXT: mul t0, a1, a3
; RV32ZBA-NEXT: add t0, a7, a5 ; RV32ZBA-NEXT: add t1, t0, a7
; RV32ZBA-NEXT: mul t1, a1, a3
; RV32ZBA-NEXT: add a5, t1, t0
; RV32ZBA-NEXT: srai t2, a1, 31 ; RV32ZBA-NEXT: srai t2, a1, 31
; RV32ZBA-NEXT: mul t3, a2, t2 ; RV32ZBA-NEXT: mul t3, a2, t2
; RV32ZBA-NEXT: srai t4, a3, 31 ; RV32ZBA-NEXT: srai t4, a3, 31
; RV32ZBA-NEXT: mul t5, t4, a0 ; RV32ZBA-NEXT: mul t5, t4, a0
; RV32ZBA-NEXT: add t6, t5, t3 ; RV32ZBA-NEXT: add t6, t5, t3
; RV32ZBA-NEXT: add s3, a5, t6 ; RV32ZBA-NEXT: add s0, t1, t6
; RV32ZBA-NEXT: sltu s2, s3, a5 ; RV32ZBA-NEXT: sltu s1, s0, t1
; RV32ZBA-NEXT: sltu a5, a5, t1 ; RV32ZBA-NEXT: sltu t0, t1, t0
; RV32ZBA-NEXT: sltu s1, t0, a7 ; RV32ZBA-NEXT: sltu a6, a7, a6
; RV32ZBA-NEXT: mulhu s0, a1, a3 ; RV32ZBA-NEXT: mulhu a7, a1, a3
; RV32ZBA-NEXT: add s1, s0, s1 ; RV32ZBA-NEXT: add a6, a7, a6
; RV32ZBA-NEXT: add a5, s1, a5 ; RV32ZBA-NEXT: add a6, a6, t0
; RV32ZBA-NEXT: mulhu s1, a2, t2 ; RV32ZBA-NEXT: mulhu a7, a2, t2
; RV32ZBA-NEXT: add s1, s1, t3 ; RV32ZBA-NEXT: add a7, a7, t3
; RV32ZBA-NEXT: mul a3, a3, t2 ; RV32ZBA-NEXT: mul a3, a3, t2
; RV32ZBA-NEXT: add a3, s1, a3 ; RV32ZBA-NEXT: add a3, a7, a3
; RV32ZBA-NEXT: mul a1, t4, a1 ; RV32ZBA-NEXT: mul a1, t4, a1
; RV32ZBA-NEXT: mulhu s1, t4, a0 ; RV32ZBA-NEXT: mulhu a7, t4, a0
; RV32ZBA-NEXT: add a1, s1, a1 ; RV32ZBA-NEXT: add a1, a7, a1
; RV32ZBA-NEXT: add a1, a1, t5 ; RV32ZBA-NEXT: add a1, a1, t5
; RV32ZBA-NEXT: add a1, a1, a3 ; RV32ZBA-NEXT: add a1, a1, a3
; RV32ZBA-NEXT: sltu a3, t6, t5 ; RV32ZBA-NEXT: sltu a3, t6, t5
; RV32ZBA-NEXT: add a1, a1, a3 ; RV32ZBA-NEXT: add a1, a1, a3
; RV32ZBA-NEXT: add a1, a5, a1 ; RV32ZBA-NEXT: add a1, a6, a1
; RV32ZBA-NEXT: add a1, a1, s2 ; RV32ZBA-NEXT: add a1, a1, s1
; RV32ZBA-NEXT: srai a3, a6, 31 ; RV32ZBA-NEXT: srai a3, a5, 31
; RV32ZBA-NEXT: xor a1, a1, a3 ; RV32ZBA-NEXT: xor a1, a1, a3
; RV32ZBA-NEXT: xor a3, s3, a3 ; RV32ZBA-NEXT: xor a3, s0, a3
; RV32ZBA-NEXT: or a1, a3, a1 ; RV32ZBA-NEXT: or a1, a3, a1
; RV32ZBA-NEXT: snez a1, a1 ; RV32ZBA-NEXT: snez a1, a1
; RV32ZBA-NEXT: mul a0, a0, a2 ; RV32ZBA-NEXT: mul a0, a0, a2
; RV32ZBA-NEXT: sw a0, 0(a4) ; RV32ZBA-NEXT: sw a0, 0(a4)
; RV32ZBA-NEXT: sw a6, 4(a4) ; RV32ZBA-NEXT: sw a5, 4(a4)
; RV32ZBA-NEXT: mv a0, a1 ; RV32ZBA-NEXT: mv a0, a1
; RV32ZBA-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32ZBA-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32ZBA-NEXT: lw s1, 8(sp) # 4-byte Folded Reload ; RV32ZBA-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32ZBA-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
; RV32ZBA-NEXT: lw s3, 0(sp) # 4-byte Folded Reload
; RV32ZBA-NEXT: addi sp, sp, 16 ; RV32ZBA-NEXT: addi sp, sp, 16
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
; ;
; RV64ZBA-LABEL: smulo.i64: ; RV64ZBA-LABEL: smulo.i64:
; RV64ZBA: # %bb.0: # %entry ; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: mulh a3, a0, a1 ; RV64ZBA-NEXT: mulh a3, a0, a1
; RV64ZBA-NEXT: mul a1, a0, a1 ; RV64ZBA-NEXT: mul a1, a0, a1
; RV64ZBA-NEXT: srai a0, a1, 63 ; RV64ZBA-NEXT: srai a0, a1, 63
; RV64ZBA-NEXT: xor a0, a3, a0 ; RV64ZBA-NEXT: xor a0, a3, a0
; RV64ZBA-NEXT: snez a0, a0 ; RV64ZBA-NEXT: snez a0, a0
; RV64ZBA-NEXT: sd a1, 0(a2) ; RV64ZBA-NEXT: sd a1, 0(a2)
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
entry: entry:
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2) %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0 %val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1 %obit = extractvalue {i64, i1} %t, 1
store i64 %val, i64* %res store i64 %val, i64* %res
ret i1 %obit ret i1 %obit
} }
define zeroext i1 @smulo2.i64(i64 %v1, i64* %res) { define zeroext i1 @smulo2.i64(i64 %v1, i64* %res) {
; RV32-LABEL: smulo2.i64: ; RV32-LABEL: smulo2.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: li a7, 13 ; RV32-NEXT: li a3, 13
; RV32-NEXT: mulhu a4, a0, a7 ; RV32-NEXT: mulhu a4, a0, a3
; RV32-NEXT: mul a5, a1, a7 ; RV32-NEXT: mul a5, a1, a3
; RV32-NEXT: add t0, a5, a4 ; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: sltu a6, t0, a5 ; RV32-NEXT: sltu a5, a4, a5
; RV32-NEXT: mulhu a5, a1, a7 ; RV32-NEXT: mulhu a6, a1, a3
; RV32-NEXT: add a5, a5, a6 ; RV32-NEXT: add a5, a6, a5
; RV32-NEXT: srai a1, a1, 31 ; RV32-NEXT: srai a1, a1, 31
; RV32-NEXT: mul a3, a1, a7 ; RV32-NEXT: mul a6, a1, a3
; RV32-NEXT: add a3, a5, a3 ; RV32-NEXT: add a6, a5, a6
; RV32-NEXT: srai a4, t0, 31 ; RV32-NEXT: srai a7, a4, 31
; RV32-NEXT: xor a6, a3, a4 ; RV32-NEXT: xor t0, a6, a7
; RV32-NEXT: sltu a3, a3, a5 ; RV32-NEXT: sltu a5, a6, a5
; RV32-NEXT: mulh a1, a1, a7 ; RV32-NEXT: mulh a1, a1, a3
; RV32-NEXT: add a1, a1, a3 ; RV32-NEXT: add a1, a1, a5
; RV32-NEXT: xor a1, a1, a4 ; RV32-NEXT: xor a1, a1, a7
; RV32-NEXT: or a1, a6, a1 ; RV32-NEXT: or a1, t0, a1
; RV32-NEXT: snez a1, a1 ; RV32-NEXT: snez a1, a1
; RV32-NEXT: mul a0, a0, a7 ; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: sw a0, 0(a2) ; RV32-NEXT: sw a0, 0(a2)
; RV32-NEXT: sw t0, 4(a2) ; RV32-NEXT: sw a4, 4(a2)
; RV32-NEXT: mv a0, a1 ; RV32-NEXT: mv a0, a1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: smulo2.i64: ; RV64-LABEL: smulo2.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: li a2, 13 ; RV64-NEXT: li a2, 13
; RV64-NEXT: mulh a3, a0, a2 ; RV64-NEXT: mulh a3, a0, a2
; RV64-NEXT: mul a2, a0, a2 ; RV64-NEXT: mul a2, a0, a2
; RV64-NEXT: srai a0, a2, 63 ; RV64-NEXT: srai a0, a2, 63
; RV64-NEXT: xor a0, a3, a0 ; RV64-NEXT: xor a0, a3, a0
; RV64-NEXT: snez a0, a0 ; RV64-NEXT: snez a0, a0
; RV64-NEXT: sd a2, 0(a1) ; RV64-NEXT: sd a2, 0(a1)
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZBA-LABEL: smulo2.i64: ; RV32ZBA-LABEL: smulo2.i64:
; RV32ZBA: # %bb.0: # %entry ; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: li a7, 13 ; RV32ZBA-NEXT: li a3, 13
; RV32ZBA-NEXT: mulhu a4, a0, a7 ; RV32ZBA-NEXT: mulhu a4, a0, a3
; RV32ZBA-NEXT: mul a5, a1, a7 ; RV32ZBA-NEXT: mul a5, a1, a3
; RV32ZBA-NEXT: add t0, a5, a4 ; RV32ZBA-NEXT: add a4, a5, a4
; RV32ZBA-NEXT: sltu a6, t0, a5 ; RV32ZBA-NEXT: sltu a5, a4, a5
; RV32ZBA-NEXT: mulhu a5, a1, a7 ; RV32ZBA-NEXT: mulhu a6, a1, a3
; RV32ZBA-NEXT: add a5, a5, a6 ; RV32ZBA-NEXT: add a5, a6, a5
; RV32ZBA-NEXT: srai a1, a1, 31 ; RV32ZBA-NEXT: srai a1, a1, 31
; RV32ZBA-NEXT: mul a3, a1, a7 ; RV32ZBA-NEXT: mul a6, a1, a3
; RV32ZBA-NEXT: add a3, a5, a3 ; RV32ZBA-NEXT: add a6, a5, a6
; RV32ZBA-NEXT: srai a4, t0, 31 ; RV32ZBA-NEXT: srai a7, a4, 31
; RV32ZBA-NEXT: xor a6, a3, a4 ; RV32ZBA-NEXT: xor t0, a6, a7
; RV32ZBA-NEXT: sltu a3, a3, a5 ; RV32ZBA-NEXT: sltu a5, a6, a5
; RV32ZBA-NEXT: mulh a1, a1, a7 ; RV32ZBA-NEXT: mulh a1, a1, a3
; RV32ZBA-NEXT: add a1, a1, a3 ; RV32ZBA-NEXT: add a1, a1, a5
; RV32ZBA-NEXT: xor a1, a1, a4 ; RV32ZBA-NEXT: xor a1, a1, a7
; RV32ZBA-NEXT: or a1, a6, a1 ; RV32ZBA-NEXT: or a1, t0, a1
; RV32ZBA-NEXT: snez a1, a1 ; RV32ZBA-NEXT: snez a1, a1
; RV32ZBA-NEXT: mul a0, a0, a7 ; RV32ZBA-NEXT: mul a0, a0, a3
; RV32ZBA-NEXT: sw a0, 0(a2) ; RV32ZBA-NEXT: sw a0, 0(a2)
; RV32ZBA-NEXT: sw t0, 4(a2) ; RV32ZBA-NEXT: sw a4, 4(a2)
; RV32ZBA-NEXT: mv a0, a1 ; RV32ZBA-NEXT: mv a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
; ;
; RV64ZBA-LABEL: smulo2.i64: ; RV64ZBA-LABEL: smulo2.i64:
; RV64ZBA: # %bb.0: # %entry ; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: li a2, 13 ; RV64ZBA-NEXT: li a2, 13
; RV64ZBA-NEXT: mulh a3, a0, a2 ; RV64ZBA-NEXT: mulh a3, a0, a2
; RV64ZBA-NEXT: mul a2, a0, a2 ; RV64ZBA-NEXT: mul a2, a0, a2
▲ Show 20 Lines • Show All 152 Lines • ▼ Show 20 Lines; RV64ZBA-NEXT: ret
%7 = zext i1 %5 to i32 %7 = zext i1 %5 to i32
store i32 %7, i32* %2, align 4 store i32 %7, i32* %2, align 4
ret i32 %6 ret i32 %6
} }
define zeroext i1 @umulo.i64(i64 %v1, i64 %v2, i64* %res) { define zeroext i1 @umulo.i64(i64 %v1, i64 %v2, i64* %res) {
; RV32-LABEL: umulo.i64: ; RV32-LABEL: umulo.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: mul a6, a3, a0 ; RV32-NEXT: mul a5, a3, a0
; RV32-NEXT: mul a5, a1, a2 ; RV32-NEXT: mul a6, a1, a2
; RV32-NEXT: add a6, a5, a6 ; RV32-NEXT: add a5, a6, a5
; RV32-NEXT: mulhu a5, a0, a2 ; RV32-NEXT: mulhu a6, a0, a2
; RV32-NEXT: add a6, a5, a6 ; RV32-NEXT: add a5, a6, a5
; RV32-NEXT: sltu a7, a6, a5 ; RV32-NEXT: sltu a6, a5, a6
; RV32-NEXT: snez t0, a3 ; RV32-NEXT: snez a7, a3
; RV32-NEXT: snez a5, a1 ; RV32-NEXT: snez t0, a1
; RV32-NEXT: and a5, a5, t0 ; RV32-NEXT: and a7, t0, a7
; RV32-NEXT: mulhu a1, a1, a2 ; RV32-NEXT: mulhu a1, a1, a2
; RV32-NEXT: snez a1, a1 ; RV32-NEXT: snez a1, a1
; RV32-NEXT: or a1, a5, a1 ; RV32-NEXT: or a1, a7, a1
; RV32-NEXT: mulhu a3, a3, a0 ; RV32-NEXT: mulhu a3, a3, a0
; RV32-NEXT: snez a3, a3 ; RV32-NEXT: snez a3, a3
; RV32-NEXT: or a1, a1, a3 ; RV32-NEXT: or a1, a1, a3
; RV32-NEXT: or a1, a1, a7 ; RV32-NEXT: or a1, a1, a6
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: sw a0, 0(a4) ; RV32-NEXT: sw a0, 0(a4)
; RV32-NEXT: sw a6, 4(a4) ; RV32-NEXT: sw a5, 4(a4)
; RV32-NEXT: mv a0, a1 ; RV32-NEXT: mv a0, a1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: umulo.i64: ; RV64-LABEL: umulo.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: mulhu a3, a0, a1 ; RV64-NEXT: mulhu a3, a0, a1
; RV64-NEXT: snez a3, a3 ; RV64-NEXT: snez a3, a3
; RV64-NEXT: mul a0, a0, a1 ; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: sd a0, 0(a2)
; RV64-NEXT: mv a0, a3 ; RV64-NEXT: mv a0, a3
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZBA-LABEL: umulo.i64: ; RV32ZBA-LABEL: umulo.i64:
; RV32ZBA: # %bb.0: # %entry ; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: mul a6, a3, a0 ; RV32ZBA-NEXT: mul a5, a3, a0
; RV32ZBA-NEXT: mul a5, a1, a2 ; RV32ZBA-NEXT: mul a6, a1, a2
; RV32ZBA-NEXT: add a6, a5, a6 ; RV32ZBA-NEXT: add a5, a6, a5
; RV32ZBA-NEXT: mulhu a5, a0, a2 ; RV32ZBA-NEXT: mulhu a6, a0, a2
; RV32ZBA-NEXT: add a6, a5, a6 ; RV32ZBA-NEXT: add a5, a6, a5
; RV32ZBA-NEXT: sltu a7, a6, a5 ; RV32ZBA-NEXT: sltu a6, a5, a6
; RV32ZBA-NEXT: snez t0, a3 ; RV32ZBA-NEXT: snez a7, a3
; RV32ZBA-NEXT: snez a5, a1 ; RV32ZBA-NEXT: snez t0, a1
; RV32ZBA-NEXT: and a5, a5, t0 ; RV32ZBA-NEXT: and a7, t0, a7
; RV32ZBA-NEXT: mulhu a1, a1, a2 ; RV32ZBA-NEXT: mulhu a1, a1, a2
; RV32ZBA-NEXT: snez a1, a1 ; RV32ZBA-NEXT: snez a1, a1
; RV32ZBA-NEXT: or a1, a5, a1 ; RV32ZBA-NEXT: or a1, a7, a1
; RV32ZBA-NEXT: mulhu a3, a3, a0 ; RV32ZBA-NEXT: mulhu a3, a3, a0
; RV32ZBA-NEXT: snez a3, a3 ; RV32ZBA-NEXT: snez a3, a3
; RV32ZBA-NEXT: or a1, a1, a3 ; RV32ZBA-NEXT: or a1, a1, a3
; RV32ZBA-NEXT: or a1, a1, a7 ; RV32ZBA-NEXT: or a1, a1, a6
; RV32ZBA-NEXT: mul a0, a0, a2 ; RV32ZBA-NEXT: mul a0, a0, a2
; RV32ZBA-NEXT: sw a0, 0(a4) ; RV32ZBA-NEXT: sw a0, 0(a4)
; RV32ZBA-NEXT: sw a6, 4(a4) ; RV32ZBA-NEXT: sw a5, 4(a4)
; RV32ZBA-NEXT: mv a0, a1 ; RV32ZBA-NEXT: mv a0, a1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
; ;
; RV64ZBA-LABEL: umulo.i64: ; RV64ZBA-LABEL: umulo.i64:
; RV64ZBA: # %bb.0: # %entry ; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: mulhu a3, a0, a1 ; RV64ZBA-NEXT: mulhu a3, a0, a1
; RV64ZBA-NEXT: snez a3, a3 ; RV64ZBA-NEXT: snez a3, a3
; RV64ZBA-NEXT: mul a0, a0, a1 ; RV64ZBA-NEXT: mul a0, a0, a1
▲ Show 20 Lines • Show All 983 Lines • ▼ Show 20 Lines
} }
define i64 @smulo.select.i64(i64 %v1, i64 %v2) { define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: smulo.select.i64: ; RV32-LABEL: smulo.select.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s2, 4(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset s0, -4 ; RV32-NEXT: .cfi_offset s0, -4
; RV32-NEXT: .cfi_offset s1, -8
; RV32-NEXT: .cfi_offset s2, -12
; RV32-NEXT: mulhu a4, a0, a2 ; RV32-NEXT: mulhu a4, a0, a2
; RV32-NEXT: mul a5, a1, a2 ; RV32-NEXT: mul a5, a1, a2
; RV32-NEXT: add a4, a5, a4 ; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: sltu a6, a4, a5 ; RV32-NEXT: sltu a5, a4, a5
; RV32-NEXT: mulhu a5, a1, a2 ; RV32-NEXT: mulhu a6, a1, a2
; RV32-NEXT: add a5, a6, a5
; RV32-NEXT: mul a6, a0, a3
; RV32-NEXT: add a4, a6, a4
; RV32-NEXT: sltu a6, a4, a6
; RV32-NEXT: mulhu a7, a0, a3
; RV32-NEXT: add a6, a7, a6
; RV32-NEXT: add a6, a5, a6 ; RV32-NEXT: add a6, a5, a6
; RV32-NEXT: mul a5, a0, a3 ; RV32-NEXT: mul a7, a1, a3
; RV32-NEXT: add a7, a5, a4 ; RV32-NEXT: add t0, a7, a6
; RV32-NEXT: sltu a5, a7, a5 ; RV32-NEXT: srai t1, a1, 31
; RV32-NEXT: mulhu a4, a0, a3 ; RV32-NEXT: mul t2, a2, t1
; RV32-NEXT: add a4, a4, a5
; RV32-NEXT: add t0, a6, a4
; RV32-NEXT: mul t1, a1, a3
; RV32-NEXT: add a4, t1, t0
; RV32-NEXT: srai a5, a1, 31
; RV32-NEXT: mul t2, a2, a5
; RV32-NEXT: srai t3, a3, 31 ; RV32-NEXT: srai t3, a3, 31
; RV32-NEXT: mul t4, t3, a0 ; RV32-NEXT: mul t4, t3, a0
; RV32-NEXT: add t5, t4, t2 ; RV32-NEXT: add t5, t4, t2
; RV32-NEXT: add t6, a4, t5 ; RV32-NEXT: add t6, t0, t5
; RV32-NEXT: sltu s2, t6, a4 ; RV32-NEXT: sltu s0, t6, t0
; RV32-NEXT: sltu a4, a4, t1 ; RV32-NEXT: sltu a7, t0, a7
; RV32-NEXT: sltu s0, t0, a6 ; RV32-NEXT: sltu a5, a6, a5
; RV32-NEXT: mulhu s1, a1, a3 ; RV32-NEXT: mulhu a6, a1, a3
; RV32-NEXT: add s1, s1, s0 ; RV32-NEXT: add a5, a6, a5
; RV32-NEXT: add a4, s1, a4 ; RV32-NEXT: add a5, a5, a7
; RV32-NEXT: mulhu s1, a2, a5 ; RV32-NEXT: mulhu a6, a2, t1
; RV32-NEXT: add s1, s1, t2 ; RV32-NEXT: add a6, a6, t2
; RV32-NEXT: mul a5, a3, a5 ; RV32-NEXT: mul a7, a3, t1
; RV32-NEXT: add a5, s1, a5 ; RV32-NEXT: add a6, a6, a7
; RV32-NEXT: mul s1, t3, a1 ; RV32-NEXT: mul a7, t3, a1
; RV32-NEXT: mulhu s0, t3, a0 ; RV32-NEXT: mulhu t0, t3, a0
; RV32-NEXT: add s1, s0, s1 ; RV32-NEXT: add a7, t0, a7
; RV32-NEXT: add s1, s1, t4 ; RV32-NEXT: add a7, a7, t4
; RV32-NEXT: add a5, s1, a5 ; RV32-NEXT: add a6, a7, a6
; RV32-NEXT: sltu s1, t5, t4 ; RV32-NEXT: sltu a7, t5, t4
; RV32-NEXT: add a5, a5, s1 ; RV32-NEXT: add a6, a6, a7
; RV32-NEXT: add a4, a4, a5 ; RV32-NEXT: add a5, a5, a6
; RV32-NEXT: add a4, a4, s2 ; RV32-NEXT: add a5, a5, s0
; RV32-NEXT: srai a5, a7, 31 ; RV32-NEXT: srai a4, a4, 31
; RV32-NEXT: xor a4, a4, a5 ; RV32-NEXT: xor a5, a5, a4
; RV32-NEXT: xor a5, t6, a5 ; RV32-NEXT: xor a4, t6, a4
; RV32-NEXT: or a4, a5, a4 ; RV32-NEXT: or a4, a4, a5
; RV32-NEXT: bnez a4, .LBB44_2 ; RV32-NEXT: bnez a4, .LBB44_2
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: mv a0, a2 ; RV32-NEXT: mv a0, a2
; RV32-NEXT: mv a1, a3 ; RV32-NEXT: mv a1, a3
; RV32-NEXT: .LBB44_2: # %entry ; RV32-NEXT: .LBB44_2: # %entry
; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: smulo.select.i64: ; RV64-LABEL: smulo.select.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: mulh a2, a0, a1 ; RV64-NEXT: mulh a2, a0, a1
; RV64-NEXT: mul a3, a0, a1 ; RV64-NEXT: mul a3, a0, a1
; RV64-NEXT: srai a3, a3, 63 ; RV64-NEXT: srai a3, a3, 63
; RV64-NEXT: bne a2, a3, .LBB44_2 ; RV64-NEXT: bne a2, a3, .LBB44_2
; RV64-NEXT: # %bb.1: # %entry ; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1 ; RV64-NEXT: mv a0, a1
; RV64-NEXT: .LBB44_2: # %entry ; RV64-NEXT: .LBB44_2: # %entry
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZBA-LABEL: smulo.select.i64: ; RV32ZBA-LABEL: smulo.select.i64:
; RV32ZBA: # %bb.0: # %entry ; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: addi sp, sp, -16 ; RV32ZBA-NEXT: addi sp, sp, -16
; RV32ZBA-NEXT: .cfi_def_cfa_offset 16 ; RV32ZBA-NEXT: .cfi_def_cfa_offset 16
; RV32ZBA-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32ZBA-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32ZBA-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32ZBA-NEXT: sw s2, 4(sp) # 4-byte Folded Spill
; RV32ZBA-NEXT: .cfi_offset s0, -4 ; RV32ZBA-NEXT: .cfi_offset s0, -4
; RV32ZBA-NEXT: .cfi_offset s1, -8
; RV32ZBA-NEXT: .cfi_offset s2, -12
; RV32ZBA-NEXT: mulhu a4, a0, a2 ; RV32ZBA-NEXT: mulhu a4, a0, a2
; RV32ZBA-NEXT: mul a5, a1, a2 ; RV32ZBA-NEXT: mul a5, a1, a2
; RV32ZBA-NEXT: add a4, a5, a4 ; RV32ZBA-NEXT: add a4, a5, a4
; RV32ZBA-NEXT: sltu a6, a4, a5 ; RV32ZBA-NEXT: sltu a5, a4, a5
; RV32ZBA-NEXT: mulhu a5, a1, a2 ; RV32ZBA-NEXT: mulhu a6, a1, a2
; RV32ZBA-NEXT: add a5, a6, a5
; RV32ZBA-NEXT: mul a6, a0, a3
; RV32ZBA-NEXT: add a4, a6, a4
; RV32ZBA-NEXT: sltu a6, a4, a6
; RV32ZBA-NEXT: mulhu a7, a0, a3
; RV32ZBA-NEXT: add a6, a7, a6
; RV32ZBA-NEXT: add a6, a5, a6 ; RV32ZBA-NEXT: add a6, a5, a6
; RV32ZBA-NEXT: mul a5, a0, a3 ; RV32ZBA-NEXT: mul a7, a1, a3
; RV32ZBA-NEXT: add a7, a5, a4 ; RV32ZBA-NEXT: add t0, a7, a6
; RV32ZBA-NEXT: sltu a5, a7, a5 ; RV32ZBA-NEXT: srai t1, a1, 31
; RV32ZBA-NEXT: mulhu a4, a0, a3 ; RV32ZBA-NEXT: mul t2, a2, t1
; RV32ZBA-NEXT: add a4, a4, a5
; RV32ZBA-NEXT: add t0, a6, a4
; RV32ZBA-NEXT: mul t1, a1, a3
; RV32ZBA-NEXT: add a4, t1, t0
; RV32ZBA-NEXT: srai a5, a1, 31
; RV32ZBA-NEXT: mul t2, a2, a5
; RV32ZBA-NEXT: srai t3, a3, 31 ; RV32ZBA-NEXT: srai t3, a3, 31
; RV32ZBA-NEXT: mul t4, t3, a0 ; RV32ZBA-NEXT: mul t4, t3, a0
; RV32ZBA-NEXT: add t5, t4, t2 ; RV32ZBA-NEXT: add t5, t4, t2
; RV32ZBA-NEXT: add t6, a4, t5 ; RV32ZBA-NEXT: add t6, t0, t5
; RV32ZBA-NEXT: sltu s2, t6, a4 ; RV32ZBA-NEXT: sltu s0, t6, t0
; RV32ZBA-NEXT: sltu a4, a4, t1 ; RV32ZBA-NEXT: sltu a7, t0, a7
; RV32ZBA-NEXT: sltu s0, t0, a6 ; RV32ZBA-NEXT: sltu a5, a6, a5
; RV32ZBA-NEXT: mulhu s1, a1, a3 ; RV32ZBA-NEXT: mulhu a6, a1, a3
; RV32ZBA-NEXT: add s1, s1, s0 ; RV32ZBA-NEXT: add a5, a6, a5
; RV32ZBA-NEXT: add a4, s1, a4 ; RV32ZBA-NEXT: add a5, a5, a7
; RV32ZBA-NEXT: mulhu s1, a2, a5 ; RV32ZBA-NEXT: mulhu a6, a2, t1
; RV32ZBA-NEXT: add s1, s1, t2 ; RV32ZBA-NEXT: add a6, a6, t2
; RV32ZBA-NEXT: mul a5, a3, a5 ; RV32ZBA-NEXT: mul a7, a3, t1
; RV32ZBA-NEXT: add a5, s1, a5 ; RV32ZBA-NEXT: add a6, a6, a7
; RV32ZBA-NEXT: mul s1, t3, a1 ; RV32ZBA-NEXT: mul a7, t3, a1
; RV32ZBA-NEXT: mulhu s0, t3, a0 ; RV32ZBA-NEXT: mulhu t0, t3, a0
; RV32ZBA-NEXT: add s1, s0, s1 ; RV32ZBA-NEXT: add a7, t0, a7
; RV32ZBA-NEXT: add s1, s1, t4 ; RV32ZBA-NEXT: add a7, a7, t4
; RV32ZBA-NEXT: add a5, s1, a5 ; RV32ZBA-NEXT: add a6, a7, a6
; RV32ZBA-NEXT: sltu s1, t5, t4 ; RV32ZBA-NEXT: sltu a7, t5, t4
; RV32ZBA-NEXT: add a5, a5, s1 ; RV32ZBA-NEXT: add a6, a6, a7
; RV32ZBA-NEXT: add a4, a4, a5 ; RV32ZBA-NEXT: add a5, a5, a6
; RV32ZBA-NEXT: add a4, a4, s2 ; RV32ZBA-NEXT: add a5, a5, s0
; RV32ZBA-NEXT: srai a5, a7, 31 ; RV32ZBA-NEXT: srai a4, a4, 31
; RV32ZBA-NEXT: xor a4, a4, a5 ; RV32ZBA-NEXT: xor a5, a5, a4
; RV32ZBA-NEXT: xor a5, t6, a5 ; RV32ZBA-NEXT: xor a4, t6, a4
; RV32ZBA-NEXT: or a4, a5, a4 ; RV32ZBA-NEXT: or a4, a4, a5
; RV32ZBA-NEXT: bnez a4, .LBB44_2 ; RV32ZBA-NEXT: bnez a4, .LBB44_2
; RV32ZBA-NEXT: # %bb.1: # %entry ; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: mv a0, a2 ; RV32ZBA-NEXT: mv a0, a2
; RV32ZBA-NEXT: mv a1, a3 ; RV32ZBA-NEXT: mv a1, a3
; RV32ZBA-NEXT: .LBB44_2: # %entry ; RV32ZBA-NEXT: .LBB44_2: # %entry
; RV32ZBA-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32ZBA-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32ZBA-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32ZBA-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
; RV32ZBA-NEXT: addi sp, sp, 16 ; RV32ZBA-NEXT: addi sp, sp, 16
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
; ;
; RV64ZBA-LABEL: smulo.select.i64: ; RV64ZBA-LABEL: smulo.select.i64:
; RV64ZBA: # %bb.0: # %entry ; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: mulh a2, a0, a1 ; RV64ZBA-NEXT: mulh a2, a0, a1
; RV64ZBA-NEXT: mul a3, a0, a1 ; RV64ZBA-NEXT: mul a3, a0, a1
; RV64ZBA-NEXT: srai a3, a3, 63 ; RV64ZBA-NEXT: srai a3, a3, 63
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} }
define i1 @smulo.not.i64(i64 %v1, i64 %v2) { define i1 @smulo.not.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: smulo.not.i64: ; RV32-LABEL: smulo.not.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s2, 4(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset s0, -4 ; RV32-NEXT: .cfi_offset s0, -4
; RV32-NEXT: .cfi_offset s1, -8
; RV32-NEXT: .cfi_offset s2, -12
; RV32-NEXT: mulhu a4, a0, a2 ; RV32-NEXT: mulhu a4, a0, a2
; RV32-NEXT: mul a5, a1, a2 ; RV32-NEXT: mul a5, a1, a2
; RV32-NEXT: add a4, a5, a4 ; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: sltu a6, a4, a5 ; RV32-NEXT: sltu a5, a4, a5
; RV32-NEXT: mulhu a5, a1, a2 ; RV32-NEXT: mulhu a6, a1, a2
; RV32-NEXT: add a5, a6, a5
; RV32-NEXT: mul a6, a0, a3
; RV32-NEXT: add a4, a6, a4
; RV32-NEXT: sltu a6, a4, a6
; RV32-NEXT: mulhu a7, a0, a3
; RV32-NEXT: add a6, a7, a6
; RV32-NEXT: add a6, a5, a6 ; RV32-NEXT: add a6, a5, a6
; RV32-NEXT: mul a5, a0, a3 ; RV32-NEXT: mul a7, a1, a3
; RV32-NEXT: add a7, a5, a4 ; RV32-NEXT: add t0, a7, a6
; RV32-NEXT: sltu a5, a7, a5 ; RV32-NEXT: srai t1, a1, 31
; RV32-NEXT: mulhu a4, a0, a3 ; RV32-NEXT: mul t2, a2, t1
; RV32-NEXT: add a4, a4, a5
; RV32-NEXT: add t0, a6, a4
; RV32-NEXT: mul t1, a1, a3
; RV32-NEXT: add a4, t1, t0
; RV32-NEXT: srai a5, a1, 31
; RV32-NEXT: mul t2, a2, a5
; RV32-NEXT: srai t3, a3, 31 ; RV32-NEXT: srai t3, a3, 31
; RV32-NEXT: mul t4, t3, a0 ; RV32-NEXT: mul t4, t3, a0
; RV32-NEXT: add t5, t4, t2 ; RV32-NEXT: add t5, t4, t2
; RV32-NEXT: add t6, a4, t5 ; RV32-NEXT: add t6, t0, t5
; RV32-NEXT: sltu s2, t6, a4 ; RV32-NEXT: sltu s0, t6, t0
; RV32-NEXT: sltu a4, a4, t1 ; RV32-NEXT: sltu a7, t0, a7
; RV32-NEXT: sltu s0, t0, a6 ; RV32-NEXT: sltu a5, a6, a5
; RV32-NEXT: mulhu s1, a1, a3 ; RV32-NEXT: mulhu a6, a1, a3
; RV32-NEXT: add s1, s1, s0 ; RV32-NEXT: add a5, a6, a5
; RV32-NEXT: add a4, s1, a4 ; RV32-NEXT: add a5, a5, a7
; RV32-NEXT: mulhu a2, a2, a5 ; RV32-NEXT: mulhu a2, a2, t1
; RV32-NEXT: add a2, a2, t2 ; RV32-NEXT: add a2, a2, t2
; RV32-NEXT: mul a3, a3, a5 ; RV32-NEXT: mul a3, a3, t1
; RV32-NEXT: add a2, a2, a3 ; RV32-NEXT: add a2, a2, a3
; RV32-NEXT: mul a1, t3, a1 ; RV32-NEXT: mul a1, t3, a1
; RV32-NEXT: mulhu a0, t3, a0 ; RV32-NEXT: mulhu a0, t3, a0
; RV32-NEXT: add a0, a0, a1 ; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: add a0, a0, t4 ; RV32-NEXT: add a0, a0, t4
; RV32-NEXT: add a0, a0, a2 ; RV32-NEXT: add a0, a0, a2
; RV32-NEXT: sltu a1, t5, t4 ; RV32-NEXT: sltu a1, t5, t4
; RV32-NEXT: add a0, a0, a1 ; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: add a0, a4, a0 ; RV32-NEXT: add a0, a5, a0
; RV32-NEXT: add a0, a0, s2 ; RV32-NEXT: add a0, a0, s0
; RV32-NEXT: srai a1, a7, 31 ; RV32-NEXT: srai a1, a4, 31
; RV32-NEXT: xor a0, a0, a1 ; RV32-NEXT: xor a0, a0, a1
; RV32-NEXT: xor a1, t6, a1 ; RV32-NEXT: xor a1, t6, a1
; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: seqz a0, a0 ; RV32-NEXT: seqz a0, a0
; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: smulo.not.i64: ; RV64-LABEL: smulo.not.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: mulh a2, a0, a1 ; RV64-NEXT: mulh a2, a0, a1
; RV64-NEXT: mul a0, a0, a1 ; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: srai a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63
; RV64-NEXT: xor a0, a2, a0 ; RV64-NEXT: xor a0, a2, a0
; RV64-NEXT: seqz a0, a0 ; RV64-NEXT: seqz a0, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZBA-LABEL: smulo.not.i64: ; RV32ZBA-LABEL: smulo.not.i64:
; RV32ZBA: # %bb.0: # %entry ; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: addi sp, sp, -16 ; RV32ZBA-NEXT: addi sp, sp, -16
; RV32ZBA-NEXT: .cfi_def_cfa_offset 16 ; RV32ZBA-NEXT: .cfi_def_cfa_offset 16
; RV32ZBA-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32ZBA-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32ZBA-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32ZBA-NEXT: sw s2, 4(sp) # 4-byte Folded Spill
; RV32ZBA-NEXT: .cfi_offset s0, -4 ; RV32ZBA-NEXT: .cfi_offset s0, -4
; RV32ZBA-NEXT: .cfi_offset s1, -8
; RV32ZBA-NEXT: .cfi_offset s2, -12
; RV32ZBA-NEXT: mulhu a4, a0, a2 ; RV32ZBA-NEXT: mulhu a4, a0, a2
; RV32ZBA-NEXT: mul a5, a1, a2 ; RV32ZBA-NEXT: mul a5, a1, a2
; RV32ZBA-NEXT: add a4, a5, a4 ; RV32ZBA-NEXT: add a4, a5, a4
; RV32ZBA-NEXT: sltu a6, a4, a5 ; RV32ZBA-NEXT: sltu a5, a4, a5
; RV32ZBA-NEXT: mulhu a5, a1, a2 ; RV32ZBA-NEXT: mulhu a6, a1, a2
; RV32ZBA-NEXT: add a5, a6, a5
; RV32ZBA-NEXT: mul a6, a0, a3
; RV32ZBA-NEXT: add a4, a6, a4
; RV32ZBA-NEXT: sltu a6, a4, a6
; RV32ZBA-NEXT: mulhu a7, a0, a3
; RV32ZBA-NEXT: add a6, a7, a6
; RV32ZBA-NEXT: add a6, a5, a6 ; RV32ZBA-NEXT: add a6, a5, a6
; RV32ZBA-NEXT: mul a5, a0, a3 ; RV32ZBA-NEXT: mul a7, a1, a3
; RV32ZBA-NEXT: add a7, a5, a4 ; RV32ZBA-NEXT: add t0, a7, a6
; RV32ZBA-NEXT: sltu a5, a7, a5 ; RV32ZBA-NEXT: srai t1, a1, 31
; RV32ZBA-NEXT: mulhu a4, a0, a3 ; RV32ZBA-NEXT: mul t2, a2, t1
; RV32ZBA-NEXT: add a4, a4, a5
; RV32ZBA-NEXT: add t0, a6, a4
; RV32ZBA-NEXT: mul t1, a1, a3
; RV32ZBA-NEXT: add a4, t1, t0
; RV32ZBA-NEXT: srai a5, a1, 31
; RV32ZBA-NEXT: mul t2, a2, a5
; RV32ZBA-NEXT: srai t3, a3, 31 ; RV32ZBA-NEXT: srai t3, a3, 31
; RV32ZBA-NEXT: mul t4, t3, a0 ; RV32ZBA-NEXT: mul t4, t3, a0
; RV32ZBA-NEXT: add t5, t4, t2 ; RV32ZBA-NEXT: add t5, t4, t2
; RV32ZBA-NEXT: add t6, a4, t5 ; RV32ZBA-NEXT: add t6, t0, t5
; RV32ZBA-NEXT: sltu s2, t6, a4 ; RV32ZBA-NEXT: sltu s0, t6, t0
; RV32ZBA-NEXT: sltu a4, a4, t1 ; RV32ZBA-NEXT: sltu a7, t0, a7
; RV32ZBA-NEXT: sltu s0, t0, a6 ; RV32ZBA-NEXT: sltu a5, a6, a5
; RV32ZBA-NEXT: mulhu s1, a1, a3 ; RV32ZBA-NEXT: mulhu a6, a1, a3
; RV32ZBA-NEXT: add s1, s1, s0 ; RV32ZBA-NEXT: add a5, a6, a5
; RV32ZBA-NEXT: add a4, s1, a4 ; RV32ZBA-NEXT: add a5, a5, a7
; RV32ZBA-NEXT: mulhu a2, a2, a5 ; RV32ZBA-NEXT: mulhu a2, a2, t1
; RV32ZBA-NEXT: add a2, a2, t2 ; RV32ZBA-NEXT: add a2, a2, t2
; RV32ZBA-NEXT: mul a3, a3, a5 ; RV32ZBA-NEXT: mul a3, a3, t1
; RV32ZBA-NEXT: add a2, a2, a3 ; RV32ZBA-NEXT: add a2, a2, a3
; RV32ZBA-NEXT: mul a1, t3, a1 ; RV32ZBA-NEXT: mul a1, t3, a1
; RV32ZBA-NEXT: mulhu a0, t3, a0 ; RV32ZBA-NEXT: mulhu a0, t3, a0
; RV32ZBA-NEXT: add a0, a0, a1 ; RV32ZBA-NEXT: add a0, a0, a1
; RV32ZBA-NEXT: add a0, a0, t4 ; RV32ZBA-NEXT: add a0, a0, t4
; RV32ZBA-NEXT: add a0, a0, a2 ; RV32ZBA-NEXT: add a0, a0, a2
; RV32ZBA-NEXT: sltu a1, t5, t4 ; RV32ZBA-NEXT: sltu a1, t5, t4
; RV32ZBA-NEXT: add a0, a0, a1 ; RV32ZBA-NEXT: add a0, a0, a1
; RV32ZBA-NEXT: add a0, a4, a0 ; RV32ZBA-NEXT: add a0, a5, a0
; RV32ZBA-NEXT: add a0, a0, s2 ; RV32ZBA-NEXT: add a0, a0, s0
; RV32ZBA-NEXT: srai a1, a7, 31 ; RV32ZBA-NEXT: srai a1, a4, 31
; RV32ZBA-NEXT: xor a0, a0, a1 ; RV32ZBA-NEXT: xor a0, a0, a1
; RV32ZBA-NEXT: xor a1, t6, a1 ; RV32ZBA-NEXT: xor a1, t6, a1
; RV32ZBA-NEXT: or a0, a1, a0 ; RV32ZBA-NEXT: or a0, a1, a0
; RV32ZBA-NEXT: seqz a0, a0 ; RV32ZBA-NEXT: seqz a0, a0
; RV32ZBA-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32ZBA-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32ZBA-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32ZBA-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
; RV32ZBA-NEXT: addi sp, sp, 16 ; RV32ZBA-NEXT: addi sp, sp, 16
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
; ;
; RV64ZBA-LABEL: smulo.not.i64: ; RV64ZBA-LABEL: smulo.not.i64:
; RV64ZBA: # %bb.0: # %entry ; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: mulh a2, a0, a1 ; RV64ZBA-NEXT: mulh a2, a0, a1
; RV64ZBA-NEXT: mul a0, a0, a1 ; RV64ZBA-NEXT: mul a0, a0, a1
; RV64ZBA-NEXT: srai a0, a0, 63 ; RV64ZBA-NEXT: srai a0, a0, 63
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
define i64 @umulo.select.i64(i64 %v1, i64 %v2) { define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: umulo.select.i64: ; RV32-LABEL: umulo.select.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: mul a4, a3, a0 ; RV32-NEXT: mul a4, a3, a0
; RV32-NEXT: mul a5, a1, a2 ; RV32-NEXT: mul a5, a1, a2
; RV32-NEXT: add a4, a5, a4 ; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: mulhu a5, a0, a2 ; RV32-NEXT: mulhu a5, a0, a2
; RV32-NEXT: add a4, a5, a4 ; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: sltu a6, a4, a5 ; RV32-NEXT: sltu a4, a4, a5
; RV32-NEXT: snez a5, a3 ; RV32-NEXT: snez a5, a3
; RV32-NEXT: snez a4, a1 ; RV32-NEXT: snez a6, a1
; RV32-NEXT: and a4, a4, a5 ; RV32-NEXT: and a5, a6, a5
; RV32-NEXT: mulhu a5, a1, a2 ; RV32-NEXT: mulhu a6, a1, a2
; RV32-NEXT: snez a5, a5 ; RV32-NEXT: snez a6, a6
; RV32-NEXT: or a4, a4, a5 ; RV32-NEXT: or a5, a5, a6
; RV32-NEXT: mulhu a5, a3, a0 ; RV32-NEXT: mulhu a6, a3, a0
; RV32-NEXT: snez a5, a5 ; RV32-NEXT: snez a6, a6
; RV32-NEXT: or a4, a4, a5 ; RV32-NEXT: or a5, a5, a6
; RV32-NEXT: or a4, a4, a6 ; RV32-NEXT: or a4, a5, a4
; RV32-NEXT: bnez a4, .LBB48_2 ; RV32-NEXT: bnez a4, .LBB48_2
; RV32-NEXT: # %bb.1: # %entry ; RV32-NEXT: # %bb.1: # %entry
; RV32-NEXT: mv a0, a2 ; RV32-NEXT: mv a0, a2
; RV32-NEXT: mv a1, a3 ; RV32-NEXT: mv a1, a3
; RV32-NEXT: .LBB48_2: # %entry ; RV32-NEXT: .LBB48_2: # %entry
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: umulo.select.i64: ; RV64-LABEL: umulo.select.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: mulhu a2, a0, a1 ; RV64-NEXT: mulhu a2, a0, a1
; RV64-NEXT: bnez a2, .LBB48_2 ; RV64-NEXT: bnez a2, .LBB48_2
; RV64-NEXT: # %bb.1: # %entry ; RV64-NEXT: # %bb.1: # %entry
; RV64-NEXT: mv a0, a1 ; RV64-NEXT: mv a0, a1
; RV64-NEXT: .LBB48_2: # %entry ; RV64-NEXT: .LBB48_2: # %entry
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZBA-LABEL: umulo.select.i64: ; RV32ZBA-LABEL: umulo.select.i64:
; RV32ZBA: # %bb.0: # %entry ; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: mul a4, a3, a0 ; RV32ZBA-NEXT: mul a4, a3, a0
; RV32ZBA-NEXT: mul a5, a1, a2 ; RV32ZBA-NEXT: mul a5, a1, a2
; RV32ZBA-NEXT: add a4, a5, a4 ; RV32ZBA-NEXT: add a4, a5, a4
; RV32ZBA-NEXT: mulhu a5, a0, a2 ; RV32ZBA-NEXT: mulhu a5, a0, a2
; RV32ZBA-NEXT: add a4, a5, a4 ; RV32ZBA-NEXT: add a4, a5, a4
; RV32ZBA-NEXT: sltu a6, a4, a5 ; RV32ZBA-NEXT: sltu a4, a4, a5
; RV32ZBA-NEXT: snez a5, a3 ; RV32ZBA-NEXT: snez a5, a3
; RV32ZBA-NEXT: snez a4, a1 ; RV32ZBA-NEXT: snez a6, a1
; RV32ZBA-NEXT: and a4, a4, a5 ; RV32ZBA-NEXT: and a5, a6, a5
; RV32ZBA-NEXT: mulhu a5, a1, a2 ; RV32ZBA-NEXT: mulhu a6, a1, a2
; RV32ZBA-NEXT: snez a5, a5 ; RV32ZBA-NEXT: snez a6, a6
; RV32ZBA-NEXT: or a4, a4, a5 ; RV32ZBA-NEXT: or a5, a5, a6
; RV32ZBA-NEXT: mulhu a5, a3, a0 ; RV32ZBA-NEXT: mulhu a6, a3, a0
; RV32ZBA-NEXT: snez a5, a5 ; RV32ZBA-NEXT: snez a6, a6
; RV32ZBA-NEXT: or a4, a4, a5 ; RV32ZBA-NEXT: or a5, a5, a6
; RV32ZBA-NEXT: or a4, a4, a6 ; RV32ZBA-NEXT: or a4, a5, a4
; RV32ZBA-NEXT: bnez a4, .LBB48_2 ; RV32ZBA-NEXT: bnez a4, .LBB48_2
; RV32ZBA-NEXT: # %bb.1: # %entry ; RV32ZBA-NEXT: # %bb.1: # %entry
; RV32ZBA-NEXT: mv a0, a2 ; RV32ZBA-NEXT: mv a0, a2
; RV32ZBA-NEXT: mv a1, a3 ; RV32ZBA-NEXT: mv a1, a3
; RV32ZBA-NEXT: .LBB48_2: # %entry ; RV32ZBA-NEXT: .LBB48_2: # %entry
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
; ;
; RV64ZBA-LABEL: umulo.select.i64: ; RV64ZBA-LABEL: umulo.select.i64:
Show All 14 Lines
define i1 @umulo.not.i64(i64 %v1, i64 %v2) { define i1 @umulo.not.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: umulo.not.i64: ; RV32-LABEL: umulo.not.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: mul a4, a3, a0 ; RV32-NEXT: mul a4, a3, a0
; RV32-NEXT: mul a5, a1, a2 ; RV32-NEXT: mul a5, a1, a2
; RV32-NEXT: add a4, a5, a4 ; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: mulhu a5, a0, a2 ; RV32-NEXT: mulhu a5, a0, a2
; RV32-NEXT: add a4, a5, a4 ; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: sltu a6, a4, a5 ; RV32-NEXT: sltu a4, a4, a5
; RV32-NEXT: snez a5, a3 ; RV32-NEXT: snez a5, a3
; RV32-NEXT: snez a4, a1 ; RV32-NEXT: snez a6, a1
; RV32-NEXT: and a4, a4, a5 ; RV32-NEXT: and a5, a6, a5
; RV32-NEXT: mulhu a1, a1, a2 ; RV32-NEXT: mulhu a1, a1, a2
; RV32-NEXT: snez a1, a1 ; RV32-NEXT: snez a1, a1
; RV32-NEXT: or a1, a4, a1 ; RV32-NEXT: or a1, a5, a1
; RV32-NEXT: mulhu a0, a3, a0 ; RV32-NEXT: mulhu a0, a3, a0
; RV32-NEXT: snez a0, a0 ; RV32-NEXT: snez a0, a0
; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: or a0, a0, a6 ; RV32-NEXT: or a0, a0, a4
; RV32-NEXT: xori a0, a0, 1 ; RV32-NEXT: xori a0, a0, 1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: umulo.not.i64: ; RV64-LABEL: umulo.not.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: mulhu a0, a0, a1 ; RV64-NEXT: mulhu a0, a0, a1
; RV64-NEXT: seqz a0, a0 ; RV64-NEXT: seqz a0, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZBA-LABEL: umulo.not.i64: ; RV32ZBA-LABEL: umulo.not.i64:
; RV32ZBA: # %bb.0: # %entry ; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: mul a4, a3, a0 ; RV32ZBA-NEXT: mul a4, a3, a0
; RV32ZBA-NEXT: mul a5, a1, a2 ; RV32ZBA-NEXT: mul a5, a1, a2
; RV32ZBA-NEXT: add a4, a5, a4 ; RV32ZBA-NEXT: add a4, a5, a4
; RV32ZBA-NEXT: mulhu a5, a0, a2 ; RV32ZBA-NEXT: mulhu a5, a0, a2
; RV32ZBA-NEXT: add a4, a5, a4 ; RV32ZBA-NEXT: add a4, a5, a4
; RV32ZBA-NEXT: sltu a6, a4, a5 ; RV32ZBA-NEXT: sltu a4, a4, a5
; RV32ZBA-NEXT: snez a5, a3 ; RV32ZBA-NEXT: snez a5, a3
; RV32ZBA-NEXT: snez a4, a1 ; RV32ZBA-NEXT: snez a6, a1
; RV32ZBA-NEXT: and a4, a4, a5 ; RV32ZBA-NEXT: and a5, a6, a5
; RV32ZBA-NEXT: mulhu a1, a1, a2 ; RV32ZBA-NEXT: mulhu a1, a1, a2
; RV32ZBA-NEXT: snez a1, a1 ; RV32ZBA-NEXT: snez a1, a1
; RV32ZBA-NEXT: or a1, a4, a1 ; RV32ZBA-NEXT: or a1, a5, a1
; RV32ZBA-NEXT: mulhu a0, a3, a0 ; RV32ZBA-NEXT: mulhu a0, a3, a0
; RV32ZBA-NEXT: snez a0, a0 ; RV32ZBA-NEXT: snez a0, a0
; RV32ZBA-NEXT: or a0, a1, a0 ; RV32ZBA-NEXT: or a0, a1, a0
; RV32ZBA-NEXT: or a0, a0, a6 ; RV32ZBA-NEXT: or a0, a0, a4
; RV32ZBA-NEXT: xori a0, a0, 1 ; RV32ZBA-NEXT: xori a0, a0, 1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
; ;
; RV64ZBA-LABEL: umulo.not.i64: ; RV64ZBA-LABEL: umulo.not.i64:
; RV64ZBA: # %bb.0: # %entry ; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: mulhu a0, a0, a1 ; RV64ZBA-NEXT: mulhu a0, a0, a1
; RV64ZBA-NEXT: seqz a0, a0 ; RV64ZBA-NEXT: seqz a0, a0
; RV64ZBA-NEXT: ret ; RV64ZBA-NEXT: ret
▲ Show 20 Lines • Show All 620 Lines • ▼ Show 20 Lines
} }
define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) { define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: smulo.br.i64: ; RV32-LABEL: smulo.br.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s2, 4(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset s0, -4 ; RV32-NEXT: .cfi_offset s0, -4
; RV32-NEXT: .cfi_offset s1, -8
; RV32-NEXT: .cfi_offset s2, -12
; RV32-NEXT: mulhu a4, a0, a2 ; RV32-NEXT: mulhu a4, a0, a2
; RV32-NEXT: mul a5, a1, a2 ; RV32-NEXT: mul a5, a1, a2
; RV32-NEXT: add a4, a5, a4 ; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: sltu a6, a4, a5 ; RV32-NEXT: sltu a5, a4, a5
; RV32-NEXT: mulhu a5, a1, a2 ; RV32-NEXT: mulhu a6, a1, a2
; RV32-NEXT: add a5, a6, a5
; RV32-NEXT: mul a6, a0, a3
; RV32-NEXT: add a4, a6, a4
; RV32-NEXT: sltu a6, a4, a6
; RV32-NEXT: mulhu a7, a0, a3
; RV32-NEXT: add a6, a7, a6
; RV32-NEXT: add a6, a5, a6 ; RV32-NEXT: add a6, a5, a6
; RV32-NEXT: mul a5, a0, a3 ; RV32-NEXT: mul a7, a1, a3
; RV32-NEXT: add a7, a5, a4 ; RV32-NEXT: add t0, a7, a6
; RV32-NEXT: sltu a5, a7, a5 ; RV32-NEXT: srai t1, a1, 31
; RV32-NEXT: mulhu a4, a0, a3 ; RV32-NEXT: mul t2, a2, t1
; RV32-NEXT: add a4, a4, a5
; RV32-NEXT: add t0, a6, a4
; RV32-NEXT: mul t1, a1, a3
; RV32-NEXT: add a4, t1, t0
; RV32-NEXT: srai a5, a1, 31
; RV32-NEXT: mul t2, a2, a5
; RV32-NEXT: srai t3, a3, 31 ; RV32-NEXT: srai t3, a3, 31
; RV32-NEXT: mul t4, t3, a0 ; RV32-NEXT: mul t4, t3, a0
; RV32-NEXT: add t5, t4, t2 ; RV32-NEXT: add t5, t4, t2
; RV32-NEXT: add t6, a4, t5 ; RV32-NEXT: add t6, t0, t5
; RV32-NEXT: sltu s2, t6, a4 ; RV32-NEXT: sltu s0, t6, t0
; RV32-NEXT: sltu a4, a4, t1 ; RV32-NEXT: sltu a7, t0, a7
; RV32-NEXT: sltu s0, t0, a6 ; RV32-NEXT: sltu a5, a6, a5
; RV32-NEXT: mulhu s1, a1, a3 ; RV32-NEXT: mulhu a6, a1, a3
; RV32-NEXT: add s1, s1, s0 ; RV32-NEXT: add a5, a6, a5
; RV32-NEXT: add a4, s1, a4 ; RV32-NEXT: add a5, a5, a7
; RV32-NEXT: mulhu a2, a2, a5 ; RV32-NEXT: mulhu a2, a2, t1
; RV32-NEXT: add a2, a2, t2 ; RV32-NEXT: add a2, a2, t2
; RV32-NEXT: mul a3, a3, a5 ; RV32-NEXT: mul a3, a3, t1
; RV32-NEXT: add a2, a2, a3 ; RV32-NEXT: add a2, a2, a3
; RV32-NEXT: mul a1, t3, a1 ; RV32-NEXT: mul a1, t3, a1
; RV32-NEXT: mulhu a0, t3, a0 ; RV32-NEXT: mulhu a0, t3, a0
; RV32-NEXT: add a0, a0, a1 ; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: add a0, a0, t4 ; RV32-NEXT: add a0, a0, t4
; RV32-NEXT: add a0, a0, a2 ; RV32-NEXT: add a0, a0, a2
; RV32-NEXT: sltu a1, t5, t4 ; RV32-NEXT: sltu a1, t5, t4
; RV32-NEXT: add a0, a0, a1 ; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: add a0, a4, a0 ; RV32-NEXT: add a0, a5, a0
; RV32-NEXT: add a0, a0, s2 ; RV32-NEXT: add a0, a0, s0
; RV32-NEXT: srai a1, a7, 31 ; RV32-NEXT: srai a1, a4, 31
; RV32-NEXT: xor a0, a0, a1 ; RV32-NEXT: xor a0, a0, a1
; RV32-NEXT: xor a1, t6, a1 ; RV32-NEXT: xor a1, t6, a1
; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: beqz a0, .LBB59_2 ; RV32-NEXT: beqz a0, .LBB59_2
; RV32-NEXT: # %bb.1: # %overflow ; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: li a0, 0 ; RV32-NEXT: li a0, 0
; RV32-NEXT: j .LBB59_3 ; RV32-NEXT: j .LBB59_3
; RV32-NEXT: .LBB59_2: # %continue ; RV32-NEXT: .LBB59_2: # %continue
; RV32-NEXT: li a0, 1 ; RV32-NEXT: li a0, 1
; RV32-NEXT: .LBB59_3: # %overflow ; RV32-NEXT: .LBB59_3: # %overflow
; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: smulo.br.i64: ; RV64-LABEL: smulo.br.i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: mulh a2, a0, a1 ; RV64-NEXT: mulh a2, a0, a1
; RV64-NEXT: mul a0, a0, a1 ; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: srai a0, a0, 63 ; RV64-NEXT: srai a0, a0, 63
; RV64-NEXT: beq a2, a0, .LBB59_2 ; RV64-NEXT: beq a2, a0, .LBB59_2
; RV64-NEXT: # %bb.1: # %overflow ; RV64-NEXT: # %bb.1: # %overflow
; RV64-NEXT: li a0, 0 ; RV64-NEXT: li a0, 0
; RV64-NEXT: ret ; RV64-NEXT: ret
; RV64-NEXT: .LBB59_2: # %continue ; RV64-NEXT: .LBB59_2: # %continue
; RV64-NEXT: li a0, 1 ; RV64-NEXT: li a0, 1
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZBA-LABEL: smulo.br.i64: ; RV32ZBA-LABEL: smulo.br.i64:
; RV32ZBA: # %bb.0: # %entry ; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: addi sp, sp, -16 ; RV32ZBA-NEXT: addi sp, sp, -16
; RV32ZBA-NEXT: .cfi_def_cfa_offset 16 ; RV32ZBA-NEXT: .cfi_def_cfa_offset 16
; RV32ZBA-NEXT: sw s0, 12(sp) # 4-byte Folded Spill ; RV32ZBA-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32ZBA-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32ZBA-NEXT: sw s2, 4(sp) # 4-byte Folded Spill
; RV32ZBA-NEXT: .cfi_offset s0, -4 ; RV32ZBA-NEXT: .cfi_offset s0, -4
; RV32ZBA-NEXT: .cfi_offset s1, -8
; RV32ZBA-NEXT: .cfi_offset s2, -12
; RV32ZBA-NEXT: mulhu a4, a0, a2 ; RV32ZBA-NEXT: mulhu a4, a0, a2
; RV32ZBA-NEXT: mul a5, a1, a2 ; RV32ZBA-NEXT: mul a5, a1, a2
; RV32ZBA-NEXT: add a4, a5, a4 ; RV32ZBA-NEXT: add a4, a5, a4
; RV32ZBA-NEXT: sltu a6, a4, a5 ; RV32ZBA-NEXT: sltu a5, a4, a5
; RV32ZBA-NEXT: mulhu a5, a1, a2 ; RV32ZBA-NEXT: mulhu a6, a1, a2
; RV32ZBA-NEXT: add a5, a6, a5
; RV32ZBA-NEXT: mul a6, a0, a3
; RV32ZBA-NEXT: add a4, a6, a4
; RV32ZBA-NEXT: sltu a6, a4, a6
; RV32ZBA-NEXT: mulhu a7, a0, a3
; RV32ZBA-NEXT: add a6, a7, a6
; RV32ZBA-NEXT: add a6, a5, a6 ; RV32ZBA-NEXT: add a6, a5, a6
; RV32ZBA-NEXT: mul a5, a0, a3 ; RV32ZBA-NEXT: mul a7, a1, a3
; RV32ZBA-NEXT: add a7, a5, a4 ; RV32ZBA-NEXT: add t0, a7, a6
; RV32ZBA-NEXT: sltu a5, a7, a5 ; RV32ZBA-NEXT: srai t1, a1, 31
; RV32ZBA-NEXT: mulhu a4, a0, a3 ; RV32ZBA-NEXT: mul t2, a2, t1
; RV32ZBA-NEXT: add a4, a4, a5
; RV32ZBA-NEXT: add t0, a6, a4
; RV32ZBA-NEXT: mul t1, a1, a3
; RV32ZBA-NEXT: add a4, t1, t0
; RV32ZBA-NEXT: srai a5, a1, 31
; RV32ZBA-NEXT: mul t2, a2, a5
; RV32ZBA-NEXT: srai t3, a3, 31 ; RV32ZBA-NEXT: srai t3, a3, 31
; RV32ZBA-NEXT: mul t4, t3, a0 ; RV32ZBA-NEXT: mul t4, t3, a0
; RV32ZBA-NEXT: add t5, t4, t2 ; RV32ZBA-NEXT: add t5, t4, t2
; RV32ZBA-NEXT: add t6, a4, t5 ; RV32ZBA-NEXT: add t6, t0, t5
; RV32ZBA-NEXT: sltu s2, t6, a4 ; RV32ZBA-NEXT: sltu s0, t6, t0
; RV32ZBA-NEXT: sltu a4, a4, t1 ; RV32ZBA-NEXT: sltu a7, t0, a7
; RV32ZBA-NEXT: sltu s0, t0, a6 ; RV32ZBA-NEXT: sltu a5, a6, a5
; RV32ZBA-NEXT: mulhu s1, a1, a3 ; RV32ZBA-NEXT: mulhu a6, a1, a3
; RV32ZBA-NEXT: add s1, s1, s0 ; RV32ZBA-NEXT: add a5, a6, a5
; RV32ZBA-NEXT: add a4, s1, a4 ; RV32ZBA-NEXT: add a5, a5, a7
; RV32ZBA-NEXT: mulhu a2, a2, a5 ; RV32ZBA-NEXT: mulhu a2, a2, t1
; RV32ZBA-NEXT: add a2, a2, t2 ; RV32ZBA-NEXT: add a2, a2, t2
; RV32ZBA-NEXT: mul a3, a3, a5 ; RV32ZBA-NEXT: mul a3, a3, t1
; RV32ZBA-NEXT: add a2, a2, a3 ; RV32ZBA-NEXT: add a2, a2, a3
; RV32ZBA-NEXT: mul a1, t3, a1 ; RV32ZBA-NEXT: mul a1, t3, a1
; RV32ZBA-NEXT: mulhu a0, t3, a0 ; RV32ZBA-NEXT: mulhu a0, t3, a0
; RV32ZBA-NEXT: add a0, a0, a1 ; RV32ZBA-NEXT: add a0, a0, a1
; RV32ZBA-NEXT: add a0, a0, t4 ; RV32ZBA-NEXT: add a0, a0, t4
; RV32ZBA-NEXT: add a0, a0, a2 ; RV32ZBA-NEXT: add a0, a0, a2
; RV32ZBA-NEXT: sltu a1, t5, t4 ; RV32ZBA-NEXT: sltu a1, t5, t4
; RV32ZBA-NEXT: add a0, a0, a1 ; RV32ZBA-NEXT: add a0, a0, a1
; RV32ZBA-NEXT: add a0, a4, a0 ; RV32ZBA-NEXT: add a0, a5, a0
; RV32ZBA-NEXT: add a0, a0, s2 ; RV32ZBA-NEXT: add a0, a0, s0
; RV32ZBA-NEXT: srai a1, a7, 31 ; RV32ZBA-NEXT: srai a1, a4, 31
; RV32ZBA-NEXT: xor a0, a0, a1 ; RV32ZBA-NEXT: xor a0, a0, a1
; RV32ZBA-NEXT: xor a1, t6, a1 ; RV32ZBA-NEXT: xor a1, t6, a1
; RV32ZBA-NEXT: or a0, a1, a0 ; RV32ZBA-NEXT: or a0, a1, a0
; RV32ZBA-NEXT: beqz a0, .LBB59_2 ; RV32ZBA-NEXT: beqz a0, .LBB59_2
; RV32ZBA-NEXT: # %bb.1: # %overflow ; RV32ZBA-NEXT: # %bb.1: # %overflow
; RV32ZBA-NEXT: li a0, 0 ; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: j .LBB59_3 ; RV32ZBA-NEXT: j .LBB59_3
; RV32ZBA-NEXT: .LBB59_2: # %continue ; RV32ZBA-NEXT: .LBB59_2: # %continue
; RV32ZBA-NEXT: li a0, 1 ; RV32ZBA-NEXT: li a0, 1
; RV32ZBA-NEXT: .LBB59_3: # %overflow ; RV32ZBA-NEXT: .LBB59_3: # %overflow
; RV32ZBA-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32ZBA-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32ZBA-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32ZBA-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
; RV32ZBA-NEXT: addi sp, sp, 16 ; RV32ZBA-NEXT: addi sp, sp, 16
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
; ;
; RV64ZBA-LABEL: smulo.br.i64: ; RV64ZBA-LABEL: smulo.br.i64:
; RV64ZBA: # %bb.0: # %entry ; RV64ZBA: # %bb.0: # %entry
; RV64ZBA-NEXT: mulh a2, a0, a1 ; RV64ZBA-NEXT: mulh a2, a0, a1
; RV64ZBA-NEXT: mul a0, a0, a1 ; RV64ZBA-NEXT: mul a0, a0, a1
; RV64ZBA-NEXT: srai a0, a0, 63 ; RV64ZBA-NEXT: srai a0, a0, 63
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continue: continue:
ret i1 true ret i1 true
} }
define zeroext i1 @smulo2.br.i64(i64 %v1) { define zeroext i1 @smulo2.br.i64(i64 %v1) {
; RV32-LABEL: smulo2.br.i64: ; RV32-LABEL: smulo2.br.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: li a6, -13 ; RV32-NEXT: li a2, -13
; RV32-NEXT: mulhu a3, a0, a6 ; RV32-NEXT: mulhu a3, a0, a2
; RV32-NEXT: mul a4, a1, a6 ; RV32-NEXT: mul a4, a1, a2
; RV32-NEXT: add a3, a4, a3 ; RV32-NEXT: add a3, a4, a3
; RV32-NEXT: sltu a4, a3, a4 ; RV32-NEXT: sltu a4, a3, a4
; RV32-NEXT: mulhu a5, a1, a6 ; RV32-NEXT: mulhu a5, a1, a2
; RV32-NEXT: add t3, a5, a4 ; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: sub t0, a3, a0 ; RV32-NEXT: sub a3, a3, a0
; RV32-NEXT: neg t1, a0 ; RV32-NEXT: neg a5, a0
; RV32-NEXT: sltu a2, t0, t1 ; RV32-NEXT: sltu a6, a3, a5
; RV32-NEXT: li a7, -1 ; RV32-NEXT: li a7, -1
; RV32-NEXT: mulhu t2, a0, a7 ; RV32-NEXT: mulhu t0, a0, a7
; RV32-NEXT: add a2, t2, a2 ; RV32-NEXT: add a6, t0, a6
; RV32-NEXT: add a2, t3, a2 ; RV32-NEXT: add a6, a4, a6
; RV32-NEXT: sub a5, a2, a1 ; RV32-NEXT: sub t1, a6, a1
; RV32-NEXT: srai t6, a1, 31 ; RV32-NEXT: srai t2, a1, 31
; RV32-NEXT: mul a4, t6, a6 ; RV32-NEXT: mul t3, t2, a2
; RV32-NEXT: sub a4, a4, a0 ; RV32-NEXT: sub t3, t3, a0
; RV32-NEXT: add t4, a5, a4 ; RV32-NEXT: add t4, t1, t3
; RV32-NEXT: sltu t5, t4, a5 ; RV32-NEXT: sltu t5, t4, t1
; RV32-NEXT: neg a3, a1 ; RV32-NEXT: neg t6, a1
; RV32-NEXT: sltu a3, a5, a3 ; RV32-NEXT: sltu t1, t1, t6
; RV32-NEXT: sltu a2, a2, t3 ; RV32-NEXT: sltu a4, a6, a4
; RV32-NEXT: mulhu a5, a1, a7 ; RV32-NEXT: mulhu a6, a1, a7
; RV32-NEXT: add a2, a5, a2 ; RV32-NEXT: add a4, a6, a4
; RV32-NEXT: add a2, a2, a3 ; RV32-NEXT: add a4, a4, t1
; RV32-NEXT: sltu a3, a4, t1 ; RV32-NEXT: sltu a5, t3, a5
; RV32-NEXT: mulh a4, t6, a6 ; RV32-NEXT: mulh a2, t2, a2
; RV32-NEXT: sub a0, t2, a0 ; RV32-NEXT: sub a0, t0, a0
; RV32-NEXT: sub a0, a0, a1 ; RV32-NEXT: sub a0, a0, a1
; RV32-NEXT: add a0, a0, a4 ; RV32-NEXT: add a0, a0, a2
; RV32-NEXT: add a0, a0, a3 ; RV32-NEXT: add a0, a0, a5
; RV32-NEXT: add a0, a2, a0 ; RV32-NEXT: add a0, a4, a0
; RV32-NEXT: add a0, a0, t5 ; RV32-NEXT: add a0, a0, t5
; RV32-NEXT: srai a1, t0, 31 ; RV32-NEXT: srai a1, a3, 31
; RV32-NEXT: xor a0, a0, a1 ; RV32-NEXT: xor a0, a0, a1
; RV32-NEXT: xor a1, t4, a1 ; RV32-NEXT: xor a1, t4, a1
; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: beqz a0, .LBB60_2 ; RV32-NEXT: beqz a0, .LBB60_2
; RV32-NEXT: # %bb.1: # %overflow ; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: li a0, 0 ; RV32-NEXT: li a0, 0
; RV32-NEXT: ret ; RV32-NEXT: ret
; RV32-NEXT: .LBB60_2: # %continue ; RV32-NEXT: .LBB60_2: # %continue
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; RV64-NEXT: li a0, 0 ; RV64-NEXT: li a0, 0
; RV64-NEXT: ret ; RV64-NEXT: ret
; RV64-NEXT: .LBB60_2: # %continue ; RV64-NEXT: .LBB60_2: # %continue
; RV64-NEXT: li a0, 1 ; RV64-NEXT: li a0, 1
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ZBA-LABEL: smulo2.br.i64: ; RV32ZBA-LABEL: smulo2.br.i64:
; RV32ZBA: # %bb.0: # %entry ; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: li a6, -13 ; RV32ZBA-NEXT: li a2, -13
; RV32ZBA-NEXT: mulhu a3, a0, a6 ; RV32ZBA-NEXT: mulhu a3, a0, a2
; RV32ZBA-NEXT: mul a4, a1, a6 ; RV32ZBA-NEXT: mul a4, a1, a2
; RV32ZBA-NEXT: add a3, a4, a3 ; RV32ZBA-NEXT: add a3, a4, a3
; RV32ZBA-NEXT: sltu a4, a3, a4 ; RV32ZBA-NEXT: sltu a4, a3, a4
; RV32ZBA-NEXT: mulhu a5, a1, a6 ; RV32ZBA-NEXT: mulhu a5, a1, a2
; RV32ZBA-NEXT: add t3, a5, a4 ; RV32ZBA-NEXT: add a4, a5, a4
; RV32ZBA-NEXT: sub t0, a3, a0 ; RV32ZBA-NEXT: sub a3, a3, a0
; RV32ZBA-NEXT: neg t1, a0 ; RV32ZBA-NEXT: neg a5, a0
; RV32ZBA-NEXT: sltu a2, t0, t1 ; RV32ZBA-NEXT: sltu a6, a3, a5
; RV32ZBA-NEXT: li a7, -1 ; RV32ZBA-NEXT: li a7, -1
; RV32ZBA-NEXT: mulhu t2, a0, a7 ; RV32ZBA-NEXT: mulhu t0, a0, a7
; RV32ZBA-NEXT: add a2, t2, a2 ; RV32ZBA-NEXT: add a6, t0, a6
; RV32ZBA-NEXT: add a2, t3, a2 ; RV32ZBA-NEXT: add a6, a4, a6
; RV32ZBA-NEXT: sub a5, a2, a1 ; RV32ZBA-NEXT: sub t1, a6, a1
; RV32ZBA-NEXT: srai t6, a1, 31 ; RV32ZBA-NEXT: srai t2, a1, 31
; RV32ZBA-NEXT: mul a4, t6, a6 ; RV32ZBA-NEXT: mul t3, t2, a2
; RV32ZBA-NEXT: sub a4, a4, a0 ; RV32ZBA-NEXT: sub t3, t3, a0
; RV32ZBA-NEXT: add t4, a5, a4 ; RV32ZBA-NEXT: add t4, t1, t3
; RV32ZBA-NEXT: sltu t5, t4, a5 ; RV32ZBA-NEXT: sltu t5, t4, t1
; RV32ZBA-NEXT: neg a3, a1 ; RV32ZBA-NEXT: neg t6, a1
; RV32ZBA-NEXT: sltu a3, a5, a3 ; RV32ZBA-NEXT: sltu t1, t1, t6
; RV32ZBA-NEXT: sltu a2, a2, t3 ; RV32ZBA-NEXT: sltu a4, a6, a4
; RV32ZBA-NEXT: mulhu a5, a1, a7 ; RV32ZBA-NEXT: mulhu a6, a1, a7
; RV32ZBA-NEXT: add a2, a5, a2 ; RV32ZBA-NEXT: add a4, a6, a4
; RV32ZBA-NEXT: add a2, a2, a3 ; RV32ZBA-NEXT: add a4, a4, t1
; RV32ZBA-NEXT: sltu a3, a4, t1 ; RV32ZBA-NEXT: sltu a5, t3, a5
; RV32ZBA-NEXT: mulh a4, t6, a6 ; RV32ZBA-NEXT: mulh a2, t2, a2
; RV32ZBA-NEXT: sub a0, t2, a0 ; RV32ZBA-NEXT: sub a0, t0, a0
; RV32ZBA-NEXT: sub a0, a0, a1 ; RV32ZBA-NEXT: sub a0, a0, a1
; RV32ZBA-NEXT: add a0, a0, a4 ; RV32ZBA-NEXT: add a0, a0, a2
; RV32ZBA-NEXT: add a0, a0, a3 ; RV32ZBA-NEXT: add a0, a0, a5
; RV32ZBA-NEXT: add a0, a2, a0 ; RV32ZBA-NEXT: add a0, a4, a0
; RV32ZBA-NEXT: add a0, a0, t5 ; RV32ZBA-NEXT: add a0, a0, t5
; RV32ZBA-NEXT: srai a1, t0, 31 ; RV32ZBA-NEXT: srai a1, a3, 31
; RV32ZBA-NEXT: xor a0, a0, a1 ; RV32ZBA-NEXT: xor a0, a0, a1
; RV32ZBA-NEXT: xor a1, t4, a1 ; RV32ZBA-NEXT: xor a1, t4, a1
; RV32ZBA-NEXT: or a0, a1, a0 ; RV32ZBA-NEXT: or a0, a1, a0
; RV32ZBA-NEXT: beqz a0, .LBB60_2 ; RV32ZBA-NEXT: beqz a0, .LBB60_2
; RV32ZBA-NEXT: # %bb.1: # %overflow ; RV32ZBA-NEXT: # %bb.1: # %overflow
; RV32ZBA-NEXT: li a0, 0 ; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
; RV32ZBA-NEXT: .LBB60_2: # %continue ; RV32ZBA-NEXT: .LBB60_2: # %continue
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define zeroext i1 @umulo.br.i64(i64 %v1, i64 %v2) { define zeroext i1 @umulo.br.i64(i64 %v1, i64 %v2) {
; RV32-LABEL: umulo.br.i64: ; RV32-LABEL: umulo.br.i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: mul a4, a3, a0 ; RV32-NEXT: mul a4, a3, a0
; RV32-NEXT: mul a5, a1, a2 ; RV32-NEXT: mul a5, a1, a2
; RV32-NEXT: add a4, a5, a4 ; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: mulhu a5, a0, a2 ; RV32-NEXT: mulhu a5, a0, a2
; RV32-NEXT: add a4, a5, a4 ; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: sltu a6, a4, a5 ; RV32-NEXT: sltu a4, a4, a5
; RV32-NEXT: snez a5, a3 ; RV32-NEXT: snez a5, a3
; RV32-NEXT: snez a4, a1 ; RV32-NEXT: snez a6, a1
; RV32-NEXT: and a4, a4, a5 ; RV32-NEXT: and a5, a6, a5
; RV32-NEXT: mulhu a1, a1, a2 ; RV32-NEXT: mulhu a1, a1, a2
; RV32-NEXT: snez a1, a1 ; RV32-NEXT: snez a1, a1
; RV32-NEXT: or a1, a4, a1 ; RV32-NEXT: or a1, a5, a1
; RV32-NEXT: mulhu a0, a3, a0 ; RV32-NEXT: mulhu a0, a3, a0
; RV32-NEXT: snez a0, a0 ; RV32-NEXT: snez a0, a0
; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: or a0, a0, a6 ; RV32-NEXT: or a0, a0, a4
; RV32-NEXT: beqz a0, .LBB62_2 ; RV32-NEXT: beqz a0, .LBB62_2
; RV32-NEXT: # %bb.1: # %overflow ; RV32-NEXT: # %bb.1: # %overflow
; RV32-NEXT: li a0, 0 ; RV32-NEXT: li a0, 0
; RV32-NEXT: ret ; RV32-NEXT: ret
; RV32-NEXT: .LBB62_2: # %continue ; RV32-NEXT: .LBB62_2: # %continue
; RV32-NEXT: li a0, 1 ; RV32-NEXT: li a0, 1
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
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; ;
; RV32ZBA-LABEL: umulo.br.i64: ; RV32ZBA-LABEL: umulo.br.i64:
; RV32ZBA: # %bb.0: # %entry ; RV32ZBA: # %bb.0: # %entry
; RV32ZBA-NEXT: mul a4, a3, a0 ; RV32ZBA-NEXT: mul a4, a3, a0
; RV32ZBA-NEXT: mul a5, a1, a2 ; RV32ZBA-NEXT: mul a5, a1, a2
; RV32ZBA-NEXT: add a4, a5, a4 ; RV32ZBA-NEXT: add a4, a5, a4
; RV32ZBA-NEXT: mulhu a5, a0, a2 ; RV32ZBA-NEXT: mulhu a5, a0, a2
; RV32ZBA-NEXT: add a4, a5, a4 ; RV32ZBA-NEXT: add a4, a5, a4
; RV32ZBA-NEXT: sltu a6, a4, a5 ; RV32ZBA-NEXT: sltu a4, a4, a5
; RV32ZBA-NEXT: snez a5, a3 ; RV32ZBA-NEXT: snez a5, a3
; RV32ZBA-NEXT: snez a4, a1 ; RV32ZBA-NEXT: snez a6, a1
; RV32ZBA-NEXT: and a4, a4, a5 ; RV32ZBA-NEXT: and a5, a6, a5
; RV32ZBA-NEXT: mulhu a1, a1, a2 ; RV32ZBA-NEXT: mulhu a1, a1, a2
; RV32ZBA-NEXT: snez a1, a1 ; RV32ZBA-NEXT: snez a1, a1
; RV32ZBA-NEXT: or a1, a4, a1 ; RV32ZBA-NEXT: or a1, a5, a1
; RV32ZBA-NEXT: mulhu a0, a3, a0 ; RV32ZBA-NEXT: mulhu a0, a3, a0
; RV32ZBA-NEXT: snez a0, a0 ; RV32ZBA-NEXT: snez a0, a0
; RV32ZBA-NEXT: or a0, a1, a0 ; RV32ZBA-NEXT: or a0, a1, a0
; RV32ZBA-NEXT: or a0, a0, a6 ; RV32ZBA-NEXT: or a0, a0, a4
; RV32ZBA-NEXT: beqz a0, .LBB62_2 ; RV32ZBA-NEXT: beqz a0, .LBB62_2
; RV32ZBA-NEXT: # %bb.1: # %overflow ; RV32ZBA-NEXT: # %bb.1: # %overflow
; RV32ZBA-NEXT: li a0, 0 ; RV32ZBA-NEXT: li a0, 0
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
; RV32ZBA-NEXT: .LBB62_2: # %continue ; RV32ZBA-NEXT: .LBB62_2: # %continue
; RV32ZBA-NEXT: li a0, 1 ; RV32ZBA-NEXT: li a0, 1
; RV32ZBA-NEXT: ret ; RV32ZBA-NEXT: ret
; ;
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