[AArch64] Define subtarget feature "reserve-x18"

[ahatanak]

Summary

This patch defines a subtarget feature "reserve-x18" and uses it to decide whether X18 should be reserved.

The clang-side patch which makes changes to pass a subtarget feature instead of a backend option is here: http://reviews.llvm.org/D11462

[echristo]

So you're defining it to true here and only have an option to set it to
true from the front end.

How would you turn it off? :)

-eric

[ahatanak]

Currently, there is no option to turn off reserve-x18 for Darwin (x18 is always reserved for Darwin), but I'm assuming it isn't there because no one needs it?

[echristo]

Then why the subtarget option and the command line option? Theoretically
it's off for someone?

-eric

[ahatanak]

According to the original email, the option was added because they wanted to reserve x18 for free bsd kernel but not didn't want to do so for userland programs. They wanted an option to reserve register x18, which is normally not reserved.

http://lists.cs.uiuc.edu/pipermail/cfe-commits/Week-of-Mon-20150119/121916.html

[echristo]

Right, but from looking at the two patches basically it's on all the time
right? You initialize it to true and the only way to pass anything is to
turn it on.

[ahatanak]

I noticed ReserveX18 wasn't being initialized in AArch64Subtarget. ReserveX18 is now initialized to false and becomes true only when subtarget feature "+reserve-x18" is passed. Sorry for the confusion.

[echristo]

Inline comment/question. Can be done as a followup if you'd like.

Thanks!

-eric

lib/Target/AArch64/AArch64RegisterInfo.cpp

402–403 ↗

(On Diff #30528)

I wonder if the isOSDarwin parts here necessarily need to be here - should be able to fold them into either a) the subtarget feature existing, or b) the query in TFI?

[ahatanak]

lib/Target/AArch64/AArch64RegisterInfo.cpp

402–403 ↗

(On Diff #30528)

Yes, either the front-end should pass reserve-x18 if the target is darwin or we should have a function in subtarget or TFI that returns (isOSDDarwin() || isX18Reserved()).

llvm/trunk/lib/Target/AArch64/AArch64.td

 /// Cyclone has register move instructions which are "free".
 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
                                         "Has zero-cycle register moves">;
 
 /// Cyclone has instructions which zero registers for "free".
 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
                                         "Has zero-cycle zeroing instructions">;
 
+def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
+                                         "Reserve X18, making it unavailable "
+                                         "as a GPR">;
+
 //===----------------------------------------------------------------------===//
 // Architectures.
 //
 
 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
   "Support ARM v8.1a instructions", [FeatureCRC]>;
 
 //===----------------------------------------------------------------------===//

llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp

 #include "llvm/Target/TargetFrameLowering.h"
 #include "llvm/Target/TargetOptions.h"
 
 using namespace llvm;
 
 #define GET_REGINFO_TARGET_DESC
 #include "AArch64GenRegisterInfo.inc"
 
-static cl::opt<bool>
-ReserveX18("aarch64-reserve-x18", cl::Hidden,
-          cl::desc("Reserve X18, making it unavailable as GPR"));
-
 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
     : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {}
 
 const MCPhysReg *
 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   assert(MF && "Invalid MachineFunction pointer.");
   if (MF->getFunction()->getCallingConv() == CallingConv::GHC)
     // GHC set of callee saved regs is empty as all those regs are
AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   Reserved.set(AArch64::WSP);
   Reserved.set(AArch64::WZR);
 
   if (TFI->hasFP(MF) || TT.isOSDarwin()) {
     Reserved.set(AArch64::FP);
     Reserved.set(AArch64::W29);
   }
 
-  if (TT.isOSDarwin() || ReserveX18) {
+  if (TT.isOSDarwin() || MF.getSubtarget<AArch64Subtarget>().isX18Reserved()) {
     Reserved.set(AArch64::X18); // Platform register
     Reserved.set(AArch64::W18);
   }
 
   if (hasBasePointer(MF)) {
     Reserved.set(AArch64::X19);
     Reserved.set(AArch64::W19);
   }
default:
     break;
   case AArch64::SP:
   case AArch64::XZR:
   case AArch64::WSP:
   case AArch64::WZR:
     return true;
   case AArch64::X18:
   case AArch64::W18:
-    return TT.isOSDarwin() || ReserveX18;
+    return TT.isOSDarwin() ||
+           MF.getSubtarget<AArch64Subtarget>().isX18Reserved();
   case AArch64::FP:
   case AArch64::W29:
     return TFI->hasFP(MF) || TT.isOSDarwin();
   case AArch64::W19:
   case AArch64::X19:
     return hasBasePointer(MF);
   }
 
unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
   case AArch64::GPR32spRegClassID:
   case AArch64::GPR32allRegClassID:
   case AArch64::GPR64spRegClassID:
   case AArch64::GPR64allRegClassID:
   case AArch64::GPR64RegClassID:
   case AArch64::GPR32commonRegClassID:
   case AArch64::GPR64commonRegClassID:
     return 32 - 1                                // XZR/SP
-           - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP
-           - (TT.isOSDarwin() || ReserveX18) // X18 reserved as platform register
-           - hasBasePointer(MF);           // X19
+      - (TT.isOSDarwin() ||
+         MF.getSubtarget<AArch64Subtarget>()
+             .isX18Reserved()) // X18 reserved as platform register
+      - hasBasePointer(MF);    // X19
   case AArch64::FPR8RegClassID:
   case AArch64::FPR16RegClassID:
   case AArch64::FPR32RegClassID:
   case AArch64::FPR64RegClassID:
   case AArch64::FPR128RegClassID:
     return 32;
 
   case AArch64::DDRegClassID:

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h

protected:
   bool HasCRC;
 
   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
   bool HasZeroCycleRegMove;
 
   // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
   bool HasZeroCycleZeroing;
 
+  // ReserveX18 - X18 is not available as a general purpose register.
+  bool ReserveX18;
+
   bool IsLittle;
 
   /// CPUString - String name of used CPU.
   std::string CPUString;
 
   /// TargetTriple - What processor and OS we're targeting.
   Triple TargetTriple;
 
public:
   }
 
   bool hasV8_1aOps() const { return HasV8_1aOps; }
 
   bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
 
   bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
 
+  bool isX18Reserved() const { return ReserveX18; }
   bool hasFPARMv8() const { return HasFPARMv8; }
   bool hasNEON() const { return HasNEON; }
   bool hasCrypto() const { return HasCrypto; }
   bool hasCRC() const { return HasCRC; }
 
   bool isLittleEndian() const { return IsLittle; }
 
   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }

llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp

 }
 
 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
                                    const std::string &FS,
                                    const TargetMachine &TM, bool LittleEndian)
     : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
       HasV8_1aOps(false), HasFPARMv8(false), HasNEON(false), HasCrypto(false),
       HasCRC(false), HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
-      IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(),
+      ReserveX18(false), IsLittle(LittleEndian), CPUString(CPU),
+      TargetTriple(TT), FrameLowering(),
       InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
       TLInfo(TM, *this) {}
 
 /// ClassifyGlobalReference - Find the target operand flags that describe
 /// how a global value should be referenced for the current subtarget.
 unsigned char
 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
                                         const TargetMachine &TM) const {

llvm/trunk/test/CodeGen/AArch64/arm64-platform-reg.ll

 ; RUN: llc -mtriple=arm64-apple-ios -o - %s | FileCheck %s --check-prefix=CHECK-RESERVE-X18
-; RUN: llc -mtriple=arm64-freebsd-gnu -aarch64-reserve-x18 -o - %s | FileCheck %s --check-prefix=CHECK-RESERVE-X18
+; RUN: llc -mtriple=arm64-freebsd-gnu -mattr=+reserve-x18 -o - %s | FileCheck %s --check-prefix=CHECK-RESERVE-X18
 ; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s
 
 ; x18 is reserved as a platform register on Darwin but not on other
 ; systems. Create loads of register pressure and make sure this is respected.
 
 ; Also, fp must always refer to a valid frame record, even if it's not the one
 ; of the current function, so it shouldn't be used either.