[RegisterCoalescer] Avoid coalescing erased Copy

[guopeilin]

Sometimes the CurrList may have two identical instructions that will be coalesced later. Once the first one coalesced, it will be removed from its parent, this will make the second identical instruction become illegal at the same time which getParent will be a nullptr. In this case, we should avoid coalescing erased instruction.<br>
The test case will trigger an Assertion like the following:

llvm-project/llvm/include/llvm/CodeGen/MachineOperand.h:359: llvm::Register llvm::MachineOperand::getReg() const: Assertion `isReg() && "This is not a register operand!"' failed.

Also recorded in Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=50919

[qcolombet]

llvm/lib/CodeGen/RegisterCoalescer.cpp

3869

Sometimes the CurrList may have two identical instructions that will be coalesced later. Once the first one coalesced, it will be removed from its parent, this will make the second identical instruction become illegal at the same time which getParent will be a nullptr.

When that happens the instruction should be part of ErasedInst and we would skip it in the next conditional block.

Why is it not happening?

BTW

Once the first one coalesced, it will be removed from its parent,

It is removed or erased? If the latter, accessing the pointer is UB, so testing getParent is invalid.

llvm/lib/CodeGen/RegisterCoalescer.cpp

void RegisterCoalescer::lateLiveIntervalUpdate() {
   }
   ToBeUpdated.clear();
 }
 
 bool RegisterCoalescer::
 copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList) {
   bool Progress = false;
   for (unsigned i = 0, e = CurrList.size(); i != e; ++i) {
-    if (!CurrList[i])
+    if (!CurrList[i] || !CurrList[i]->getParent())
       continue;
     // Skip instruction pointers that have already been erased, for example by
     // dead code elimination.
     if (ErasedInstrs.count(CurrList[i])) {
       CurrList[i] = nullptr;
       continue;
     }
     bool Again = false;

llvm/test/CodeGen/AArch64/avoid-coalescing-erased-instructions.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-arm-none-eabi -o - %s \
+# RUN: -run-pass simple-register-coalescing | FileCheck %s
+--- |
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64-arm-none-eabi"
+
+  @u = common dso_local local_unnamed_addr global i32 0, align 4
+  @r = common dso_local local_unnamed_addr global i32 0, align 4
+  @q = common dso_local local_unnamed_addr global i32 0, align 4
+
+  define dso_local i32 @s() local_unnamed_addr {
+    ret i32 0
+  }
+...
+---
+name:            s
+alignment:       4
+body:             |
+  ; CHECK-LABEL: name: s
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
+  ; CHECK:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 841054
+  ; CHECK:   dead $wzr = SUBSWri undef %2:gpr32sp, 2, 0, implicit-def $nzcv
+  ; CHECK:   Bcc 13, %bb.2, implicit killed $nzcv
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.7(0x80000000)
+  ; CHECK:   [[COPY:%[0-9]+]]:gpr32 = COPY $wzr
+  ; CHECK:   [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
+  ; CHECK:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 841054
+  ; CHECK:   B %bb.7
+  ; CHECK: bb.2:
+  ; CHECK:   successors: %bb.4(0x40000000), %bb.3(0x40000000)
+  ; CHECK:   [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @u
+  ; CHECK:   [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @u
+  ; CHECK:   [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @r
+  ; CHECK:   [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[ADRP1]], target-flags(aarch64-pageoff, aarch64-nc) @r
+  ; CHECK:   dead $wzr = SUBSWri [[LDRWui]], 0, 0, implicit-def $nzcv
+  ; CHECK:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY]], [[LDRWui1]], 0, implicit killed $nzcv
+  ; CHECK:   [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
+  ; CHECK:   CBNZW $wzr, %bb.4
+  ; CHECK:   B %bb.3
+  ; CHECK: bb.3:
+  ; CHECK:   successors: %bb.15(0x80000000)
+  ; CHECK:   [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY2]], [[COPY]]
+  ; CHECK:   [[MSUBWrrr:%[0-9]+]]:gpr32 = MSUBWrrr [[SDIVWr]], [[COPY]], [[COPY2]]
+  ; CHECK:   [[ADDWrr:%[0-9]+]]:gpr32 = nsw ADDWrr [[MSUBWrrr]], [[CSELWr]]
+  ; CHECK:   [[ADRP2:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @q
+  ; CHECK:   STRWui [[ADDWrr]], [[ADRP2]], target-flags(aarch64-pageoff, aarch64-nc) @q :: (store 4 into @q)
+  ; CHECK:   B %bb.15
+  ; CHECK: bb.4:
+  ; CHECK:   successors: %bb.6(0x40000000), %bb.5(0x40000000)
+  ; CHECK:   CBNZW $wzr, %bb.6
+  ; CHECK:   B %bb.5
+  ; CHECK: bb.5:
+  ; CHECK:   successors: %bb.6(0x80000000)
+  ; CHECK:   B %bb.6
+  ; CHECK: bb.6:
+  ; CHECK:   successors: %bb.7(0x80000000)
+  ; CHECK: bb.7:
+  ; CHECK:   successors: %bb.8(0x80000000)
+  ; CHECK: bb.8:
+  ; CHECK:   successors: %bb.9(0x40000000), %bb.8(0x40000000)
+  ; CHECK:   CBNZW $wzr, %bb.8
+  ; CHECK:   B %bb.9
+  ; CHECK: bb.9:
+  ; CHECK:   successors: %bb.14(0x40000000), %bb.10(0x40000000)
+  ; CHECK:   CBNZW $wzr, %bb.14
+  ; CHECK:   B %bb.10
+  ; CHECK: bb.10:
+  ; CHECK:   successors: %bb.15(0x40000000), %bb.11(0x40000000)
+  ; CHECK:   CBNZW $wzr, %bb.15
+  ; CHECK:   B %bb.11
+  ; CHECK: bb.11:
+  ; CHECK:   successors: %bb.14(0x40000000), %bb.12(0x40000000)
+  ; CHECK:   CBNZW $wzr, %bb.14
+  ; CHECK:   B %bb.12
+  ; CHECK: bb.12:
+  ; CHECK:   successors: %bb.14(0x40000000), %bb.13(0x40000000)
+  ; CHECK:   CBZW $wzr, %bb.14
+  ; CHECK: bb.13:
+  ; CHECK:   successors: %bb.3(0x80000000)
+  ; CHECK:   [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
+  ; CHECK:   B %bb.3
+  ; CHECK: bb.14:
+  ; CHECK:   successors: %bb.3(0x80000000)
+  ; CHECK:   ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+  ; CHECK:   ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+  ; CHECK:   B %bb.3
+  ; CHECK: bb.15:
+  ; CHECK:   $w0 = COPY $wzr
+  ; CHECK:   RET_ReallyLR implicit killed $w0
+  bb.0:
+    successors: %bb.2, %bb.1
+
+    %13:gpr32 = MOVi32imm 841054
+    %0:gpr32 = COPY %13
+    dead $wzr = SUBSWri undef %16:gpr32sp, 2, 0, implicit-def $nzcv
+    Bcc 13, %bb.2, implicit killed $nzcv
+
+  bb.1:
+    successors: %bb.7
+
+    %14:gpr32all = COPY $wzr
+    %1:gpr32all = COPY killed %14
+    %48:gpr32all = COPY %1
+    %49:gpr32all = COPY killed %1
+    %50:gpr32all = COPY killed %0
+    B %bb.7
+
+  bb.2:
+    successors: %bb.4, %bb.3
+
+    %18:gpr64common = ADRP target-flags(aarch64-page) @u
+    %19:gpr32common = LDRWui killed %18, target-flags(aarch64-pageoff, aarch64-nc) @u
+    %20:gpr64common = ADRP target-flags(aarch64-page) @r
+    %21:gpr32 = LDRWui killed %20, target-flags(aarch64-pageoff, aarch64-nc) @r
+    dead $wzr = SUBSWri killed %19, 0, 0, implicit-def $nzcv
+    %23:gpr32 = CSELWr killed %13, killed %21, 0, implicit killed $nzcv
+    %24:gpr32 = COPY $wzr
+    %17:gpr32all = COPY %24
+    %2:gpr32all = COPY killed %23
+    %42:gpr32 = COPY %0
+    %43:gpr32 = COPY %17
+    %44:gpr32 = COPY %2
+    %45:gpr32all = COPY killed %0
+    %46:gpr32all = COPY killed %17
+    %47:gpr32all = COPY killed %2
+    CBNZW killed %24, %bb.4
+    B %bb.3
+
+  bb.3:
+    successors: %bb.14
+
+    %5:gpr32 = COPY killed %44
+    %4:gpr32 = COPY killed %43
+    %3:gpr32 = COPY killed %42
+    %37:gpr32 = SDIVWr %4, %3
+    %39:gpr32 = MSUBWrrr killed %37, %3, %4
+    %40:gpr32 = nsw ADDWrr killed %39, %5
+    %41:gpr64common = ADRP target-flags(aarch64-page) @q
+    STRWui killed %40, killed %41, target-flags(aarch64-pageoff, aarch64-nc) @q :: (store 4 into @q)
+    %45:gpr32all = COPY killed %3
+    %46:gpr32all = COPY killed %4
+    %47:gpr32all = COPY killed %5
+    B %bb.14
+
+  bb.4:
+    successors: %bb.6, %bb.5
+
+    %8:gpr32all = COPY killed %47
+    %7:gpr32all = COPY killed %46
+    %6:gpr32all = COPY killed %45
+    %25:gpr32 = COPY $wzr
+    CBNZW killed %25, %bb.6
+    B %bb.5
+
+  bb.5:
+    successors: %bb.6
+
+    B %bb.6
+
+  bb.6:
+    successors: %bb.7
+
+    %48:gpr32all = COPY killed %6
+    %49:gpr32all = COPY killed %7
+    %50:gpr32all = COPY killed %8
+
+  bb.7:
+    successors: %bb.8
+
+    %11:gpr32all = COPY killed %50
+    %10:gpr32all = COPY killed %49
+    %9:gpr32all = COPY killed %48
+
+  bb.8:
+    successors: %bb.9, %bb.8
+
+    %27:gpr32 = COPY $wzr
+    CBNZW killed %27, %bb.8
+    B %bb.9
+
+  bb.9:
+    successors: %bb.13, %bb.10
+
+    %28:gpr32 = COPY $wzr
+    CBNZW killed %28, %bb.13
+    B %bb.10
+
+  bb.10:
+    successors: %bb.14, %bb.11
+
+    %29:gpr32 = COPY $wzr
+    CBNZW killed %29, %bb.14
+    B %bb.11
+
+  bb.11:
+    successors: %bb.13, %bb.12
+
+    %32:gpr32 = COPY $wzr
+    CBNZW killed %32, %bb.13
+    B %bb.12
+
+  bb.12:
+    successors: %bb.13, %bb.15
+
+    %33:gpr32 = COPY $wzr
+    CBZW killed %33, %bb.13
+
+  bb.15:
+    successors: %bb.3
+
+    %42:gpr32 = COPY killed %9
+    %43:gpr32 = IMPLICIT_DEF
+    %44:gpr32 = COPY killed %11
+    B %bb.3
+
+  bb.13:
+    successors: %bb.3
+
+    ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+    ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+    %42:gpr32 = COPY killed %9
+    %43:gpr32 = COPY killed %10
+    %44:gpr32 = COPY killed %11
+    B %bb.3
+
+  bb.14:
+    %30:gpr32all = COPY $wzr
+    $w0 = COPY killed %30
+    RET_ReallyLR implicit killed $w0
+
+...