[X86] Store DAGCombine should not assume arbitrary vector types are simple

[mkuper]

Summary

This fixes PR23476.
The basic issue is that we have a store being fed by an extract from v16i64. The combine tries to bitcast it into a v16f64, which is not a simple type, even though v16i64 is.
More generally, this may fire before legalization, so the origin type doesn't have to be simple either.

[spatel]

Thanks, Michael. The code change LGTM, but can you minimize the test case and add it to the file with the related tests?

I think something like this patch would do:

Index: test/CodeGen/X86/i64-mem-copy.ll
===================================================================
--- test/CodeGen/X86/i64-mem-copy.ll	(revision 236961)
+++ test/CodeGen/X86/i64-mem-copy.ll	(working copy)
@@ -63,3 +63,15 @@
   ret void
 }
 
+; https://llvm.org/bugs/show_bug.cgi?id=23476
+; Handle extraction from a non-simple / pre-legalization type.
+
+define void @PR23476(<5 x i64> %in, i64* %out, i32 %index) {
+; X32-LABEL: PR23476:
+; X32:         movsd {{.*#+}} xmm0 = mem[0],zero
+; X32-NEXT:    movsd %xmm0, (%eax)
+  %ext = extractelement <5 x i64> %in, i32 %index
+  store i64 %ext, i64* %out, align 8
+  ret void
+}
+

[mkuper]

Sure, I just copied the test-case from the PR. Will use the minimized one.
Thanks!

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
   // to get past legalization. The execution dependencies fixup pass will
   // choose the optimal machine instruction for the store if this really is
   // an integer or v2f32 rather than an f64.
   if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
       St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
     SDValue OldExtract = St->getOperand(1);
     SDValue ExtOp0 = OldExtract.getOperand(0);
     unsigned VecSize = ExtOp0.getValueSizeInBits();
-    MVT VecVT = MVT::getVectorVT(MVT::f64, VecSize / 64);
+    EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
     SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtOp0);
     SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
                                      BitCast, OldExtract.getOperand(1));
     return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
                         St->getPointerInfo(), St->isVolatile(),
                         St->isNonTemporal(), St->getAlignment());
   }
 

llvm/trunk/test/CodeGen/X86/i64-mem-copy.ll

 ; X32AVX-NEXT:    retl
   %z = add <16 x i16> %x, %y                          ; force execution domain
   %bc = bitcast <16 x i16> %z to <4 x i64>
   %vecext = extractelement <4 x i64> %bc, i32 2
   store i64 %vecext, i64* %i, align 8
   ret void
 }
 
+; PR23476
+; Handle extraction from a non-simple / pre-legalization type.
+
+define void @PR23476(<5 x i64> %in, i64* %out, i32 %index) {
+; X32-LABEL: PR23476:
+; X32:         movsd {{.*#+}} xmm0 = mem[0],zero
+; X32-NEXT:    movsd %xmm0, (%eax)
+  %ext = extractelement <5 x i64> %in, i32 %index
+  store i64 %ext, i64* %out, align 8
+  ret void
+}