[X86] Store DAGCombine should not assume arbitrary vector types are simple

[mkuper]

Summary

This fixes PR23476.
The basic issue is that we have a store being fed by an extract from v16i64. The combine tries to bitcast it into a v16f64, which is not a simple type, even though v16i64 is.
More generally, this may fire before legalization, so the origin type doesn't have to be simple either.

[spatel]

Thanks, Michael. The code change LGTM, but can you minimize the test case and add it to the file with the related tests?

I think something like this patch would do:

Index: test/CodeGen/X86/i64-mem-copy.ll
===================================================================
--- test/CodeGen/X86/i64-mem-copy.ll	(revision 236961)
+++ test/CodeGen/X86/i64-mem-copy.ll	(working copy)
@@ -63,3 +63,15 @@
   ret void
 }
 
+; https://llvm.org/bugs/show_bug.cgi?id=23476
+; Handle extraction from a non-simple / pre-legalization type.
+
+define void @PR23476(<5 x i64> %in, i64* %out, i32 %index) {
+; X32-LABEL: PR23476:
+; X32:         movsd {{.*#+}} xmm0 = mem[0],zero
+; X32-NEXT:    movsd %xmm0, (%eax)
+  %ext = extractelement <5 x i64> %in, i32 %index
+  store i64 %ext, i64* %out, align 8
+  ret void
+}
+

[mkuper]

Sure, I just copied the test-case from the PR. Will use the minimized one.
Thanks!

lib/Target/X86/X86ISelLowering.cpp

static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
   // to get past legalization. The execution dependencies fixup pass will
   // choose the optimal machine instruction for the store if this really is
   // an integer or v2f32 rather than an f64.
   if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
       St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
     SDValue OldExtract = St->getOperand(1);
     SDValue ExtOp0 = OldExtract.getOperand(0);
     unsigned VecSize = ExtOp0.getValueSizeInBits();
-    MVT VecVT = MVT::getVectorVT(MVT::f64, VecSize / 64);
+    EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
     SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtOp0);
     SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
                                      BitCast, OldExtract.getOperand(1));
     return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
                         St->getPointerInfo(), St->isVolatile(),
                         St->isNonTemporal(), St->getAlignment());
   }
 

test/CodeGen/X86/pr23476.ll

+; RUN: llc < %s -mattr=+avx | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
+target triple = "i386-unknown-linux-gnu"
+
+; Function Attrs: nounwind readnone
+declare double @log(double) #0
+
+; Function Attrs: nounwind readnone
+;declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) #0
+
+; Function Attrs: nounwind
+;declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x float>, <8 x float>) #1
+
+; Function Attrs: nounwind readnone
+;declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>) #0
+
+; Function Attrs: nounwind readnone
+;declare i64 @llvm.cttz.i64(i64, i1) #0
+
+; CHECK-LABEL: f_v
+; CHECK: vmovsd  {{.*#+}} xmm0 = mem[0],zero
+; CHECK: vmovsd  %xmm0, (%esp)
+; Function Attrs: nounwind
+define void @f_v(float* noalias nocapture %RET) #1 {
+allocas:
+  br label %foreach_active_find_next.i
+
+foreach_active_find_next.i:                       ; preds = %foreach_active_find_next.i, %allocas
+  ;%extract.i.i.i = extractelement <16 x i64> <i64 4668012349850910720, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i32 undef
+  %extract.i.i.i = extractelement <14 x i64> <i64 4668012349850910720, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i32 undef
+  %int_to_double_bitcast.i.i.i41.i = bitcast i64 %extract.i.i.i to double
+  %r.i.i = tail call double @log(double %int_to_double_bitcast.i.i.i41.i) #1
+  br i1 undef, label %log___vyd.exit, label %foreach_active_find_next.i
+
+log___vyd.exit:                                   ; preds = %foreach_active_find_next.i
+  ret void
+}
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 236935)"}