[mips] [IAS] Enforce .set nomacro.

[tomatabacu]

Summary

When used, ".set nomacro" causes warning messages to be reported when we expand pseudo-instructions to multiple machine instructions.

[tomatabacu]

Fix typo in CHECK-NOT.

[dsanders]

LGTM

I'd prefer there to be some CHECK's in test/MC/Mips/set-nomacro-micromips.s rather than just CHECK-NOT's because of the chance of incorrectly passing due to future changes to the message but there currently aren't any microMIPS instructions that can CHECK the message.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

if (0 <= ImmValue && ImmValue <= 65535) {
     // For negative signed 16-bit values (-32768 <= j < 0):
     // li d,j => addiu d,$zero,j
     tmpInst.setOpcode(Mips::ADDiu);
     tmpInst.addOperand(MCOperand::CreateReg(Reg));
     tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
     tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
     Instructions.push_back(tmpInst);
   } else if ((ImmValue & 0xffffffff) == ImmValue) {
+    if (!AssemblerOptions.back()->isMacro())
+      Warning(IDLoc, "macro instruction expanded into multiple instructions");
+
     // For all other values which are representable as a 32-bit integer:
     // li d,j => lui d,hi16(j)
     //           ori d,d,lo16(j)
     uint16_t Bits31To16 = (ImmValue >> 16) & 0xffff;
     uint16_t Bits15To0 = ImmValue & 0xffff;
 
     tmpInst.setOpcode(Mips::LUi);
     tmpInst.addOperand(MCOperand::CreateReg(Reg));
     tmpInst.addOperand(MCOperand::CreateImm(Bits31To16));
     Instructions.push_back(tmpInst);
     createLShiftOri<0>(Bits15To0, Reg, IDLoc, Instructions);
   } else if ((ImmValue & (0xffffLL << 48)) == 0) {
     if (Is32BitImm) {
       Error(IDLoc, "instruction requires a 32-bit immediate");
       return true;
     }
+    if (!AssemblerOptions.back()->isMacro())
+      Warning(IDLoc, "macro instruction expanded into multiple instructions");
 
     //            <-------  lo32 ------>
     // <-------  hi32 ------>
     // <- hi16 ->             <- lo16 ->
     //  _________________________________
     // |          |          |          |
     // | 16-bits  | 16-bits  | 16-bits  |
     // |__________|__________|__________|
if (0 <= ImmValue && ImmValue <= 65535) {
     Instructions.push_back(tmpInst);
     createLShiftOri<0>(Bits31To16, Reg, IDLoc, Instructions);
     createLShiftOri<16>(Bits15To0, Reg, IDLoc, Instructions);
   } else {
     if (Is32BitImm) {
       Error(IDLoc, "instruction requires a 32-bit immediate");
       return true;
     }
+    if (!AssemblerOptions.back()->isMacro())
+      Warning(IDLoc, "macro instruction expanded into multiple instructions");
 
     // <-------  hi32 ------> <-------  lo32 ------>
     // <- hi16 ->                        <- lo16 ->
     //  ___________________________________________
     // |          |          |          |          |
     // | 16-bits  | 16-bits  | 16-bits  | 16-bits  |
     // |__________|__________|__________|__________|
     //
if (-32768 <= ImmValue && ImmValue <= 65535) {
     // For -32768 <= j <= 65535.
     // la d,j(s) => addiu d,s,j
     tmpInst.setOpcode(Mips::ADDiu);
     tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
     tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
     tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
     Instructions.push_back(tmpInst);
   } else {
+    if (!AssemblerOptions.back()->isMacro())
+      Warning(IDLoc, "macro instruction expanded into multiple instructions");
+
     // For any other value of j that is representable as a 32-bit integer.
     // la d,j(s) => lui d,hi16(j)
     //              ori d,d,lo16(j)
     //              addu d,d,s
     tmpInst.setOpcode(Mips::LUi);
     tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
     tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
     Instructions.push_back(tmpInst);
if (-32768 <= ImmValue && ImmValue <= 65535) {
     // For -32768 <= j <= 65535.
     // la d,j => addiu d,$zero,j
     tmpInst.setOpcode(Mips::ADDiu);
     tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
     tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
     tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
     Instructions.push_back(tmpInst);
   } else {
+    if (!AssemblerOptions.back()->isMacro())
+      Warning(IDLoc, "macro instruction expanded into multiple instructions");
+
     // For any other value of j that is representable as a 32-bit integer.
     // la d,j => lui d,hi16(j)
     //           ori d,d,lo16(j)
     tmpInst.setOpcode(Mips::LUi);
     tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
     tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
     Instructions.push_back(tmpInst);
     tmpInst.clear();
     tmpInst.setOpcode(Mips::ORi);
     tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
     tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
     tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
     Instructions.push_back(tmpInst);
   }
   return false;
 }
 
 void
 MipsAsmParser::expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc,
                                     SmallVectorImpl<MCInst> &Instructions) {
+  if (!AssemblerOptions.back()->isMacro())
+    Warning(IDLoc, "macro instruction expanded into multiple instructions");
+
   // FIXME: If we do have a valid at register to use, we should generate a
   // slightly shorter sequence here.
   MCInst tmpInst;
   int ExprOperandNo = 1;
   // Sometimes the assembly parser will get the immediate expression as
   // a $zero + an immediate.
   if (Inst.getNumOperands() == 3) {
     assert(Inst.getOperand(1).getReg() ==

test/MC/Mips/set-nomacro-micromips.s

+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=micromips 2>&1 | FileCheck %s
+
+  .text
+  .type main, @function
+  .set micromips
+main:
+# CHECK-NOT: warning: macro instruction expanded into multiple instructions
+  .set macro
+  b 132
+  b 1332
+  b bar
+
+  lwm $16, $17, 8($sp)
+  swm $16, $17, 8($sp)
+
+  add $4, $5, $6
+
+  .set noreorder
+  .set nomacro
+  b 132
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  b 1332
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  b bar
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  lwm $16, $17, 8($sp)
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  swm $16, $17, 8($sp)
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  add $4, $5, $6
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions

test/MC/Mips/set-nomacro.s

+# RUN: llvm-mc %s -arch=mips -mcpu=mips32 2>&1 | FileCheck %s
+
+# CHECK-NOT: warning: macro instruction expanded into multiple instructions
+  .set macro
+  li  $8, -16
+  li  $8, 16
+  li  $8, 161616
+
+  la  $8, 16
+  la  $8, 161616
+  la  $8, 16($9)
+  la  $8, 161616($9)
+  la  $8, symbol
+
+  jal $25
+  jal $4, $25
+
+  add $4, $5, $6
+
+  .set noreorder
+  .set nomacro
+  li  $8, -16
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  li  $8, 16
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  li  $8, 161616
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  la  $8, 16
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  la  $8, 161616
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  la  $8, 16($9)
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  la  $8, 161616($9)
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  la  $8, symbol
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  jal $25
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  jal $4, $25
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
+  add $4, $5, $6
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions