[mips][msa] Test basic operations for the N32 ABI too.

[dsanders]

Summary

This required adding instruction aliases for dneg.

N64 will be enabled shortly but requires additional bugfixes.

Depends on D9340

[vkalintiris]

LGTM, with the typo fix and with the aliases marked appropriately.

lib/Target/Mips/Mips64InstrInfo.td

570–575

• I believe that we should mark these aliases as ISA_MIPS3.
• I can't find the second form of the dneg alias anywhere in binutils.
• dnegu isn't used in this patch.

Also, we should add some tests in test/MC for these aliases in a future patch.

test/CodeGen/Mips/msa/basic_operations.ll

5–6

Small typo: R1N -> RUN

[dsanders]

Thanks.

lib/Target/Mips/Mips64InstrInfo.td

570–575

I believe that we should mark these aliases as ISA_MIPS3.

Makes sense to me.

I can't find the second form of the dneg alias anywhere in binutils.

I mostly included this because the 1-operand form of neg is accepted by IAS. GAS accepts it as well with 'dneg $1' being equivalent to 'dneg $1, $1'.

dnegu isn't used in this patch.

I'll add some assembler/disassembler tests for it (and the others).

test/CodeGen/Mips/msa/basic_operations.ll

5–6

This isn't actually a typo. It's a placeholder that keeps the currently broken N64 disabled until the next patch. It shouldn't have been left in the patch though so I'll drop these two lines and merge them with the s/R!N/RUN/ from D9342 instead.

[dsanders]

dneg/dnegu are now available to MIPS-III and later 64-bit ISA's. They also
have assembly/disassembly tests.

Dropped 'R!N' lines.

Made basic_operations_float.ll test N32 too.

lib/Target/Mips/Mips64InstrInfo.td

def : MipsInstAlias<"daddu $rs, $imm",
                     (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
                     0>, ISA_MIPS3;
 def : MipsInstAlias<"dadd $rs, $imm",
                     (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
                     0>, ISA_MIPS3_NOT_32R6_64R6;
 def : MipsInstAlias<"dsll $rd, $rt, $rs",
                     (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
                     ISA_MIPS3;
+def : MipsInstAlias<"dneg $rt, $rs",
+                    (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
+                    ISA_MIPS3;
+def : MipsInstAlias<"dneg $rt",
+                    (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
+                    ISA_MIPS3;
+def : MipsInstAlias<"dnegu $rt, $rs",
+                    (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
+                    ISA_MIPS3;
 def : MipsInstAlias<"dsubu $rt, $rs, $imm",
                     (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
                             InvertedImOperand64:$imm), 0>, ISA_MIPS3;
 def : MipsInstAlias<"dsubi $rs, $rt, $imm",
                     (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
                            InvertedImOperand64:$imm),
                     0>, ISA_MIPS3_NOT_32R6_64R6;
 def : MipsInstAlias<"dsubi $rs, $imm",

lib/Target/Mips/MipsSEISelLowering.cpp

MipsSETargetLowering::emitINSERT_DF_VIDX(MachineInstr *MI,
   DebugLoc DL = MI->getDebugLoc();
   unsigned Wd = MI->getOperand(0).getReg();
   unsigned SrcVecReg = MI->getOperand(1).getReg();
   unsigned LaneReg = MI->getOperand(2).getReg();
   unsigned SrcValReg = MI->getOperand(3).getReg();
 
   const TargetRegisterClass *VecRC = nullptr;
   const TargetRegisterClass *GPRRC =
-      Subtarget.isGP64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
+      Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
   unsigned EltLog2Size;
   unsigned InsertOp = 0;
   unsigned InsveOp = 0;
   switch (EltSizeInBytes) {
   default:
     llvm_unreachable("Unexpected size");
   case 1:
     EltLog2Size = 0;
BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
         .addReg(SrcValReg)
         .addImm(0);
   }
 
   // Rotate elements the rest of the way for a full rotation.
   // sld.df inteprets $rt modulo the number of columns so we only need to negate
   // the lane index to do this.
   unsigned LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
-  BuildMI(*BB, MI, DL, TII->get(Mips::SUB), LaneTmp2)
-      .addReg(Mips::ZERO)
+  BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
+          LaneTmp2)
+      .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
       .addReg(LaneReg);
   BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
       .addReg(WdTmp2)
       .addReg(WdTmp2)
       .addReg(LaneTmp2);
 
   MI->eraseFromParent(); // The pseudo instruction is gone now.
   return BB;

test/CodeGen/Mips/msa/basic_operations.ll

-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-BE %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-LE %s
+; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 -check-prefix=MIPS32 -check-prefix=ALL-BE %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 -check-prefix=MIPS32 -check-prefix=ALL-LE %s
+; RUN: llc -march=mips64 -target-abi n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 -check-prefix=MIPS64 -check-prefix=ALL-BE %s
+; RUN: llc -march=mips64el -target-abi n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 -check-prefix=MIPS64 -check-prefix=ALL-LE %s
 
 @v4i8 = global <4 x i8> <i8 0, i8 0, i8 0, i8 0>
 @v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
 @v8i16 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
 @v4i32 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>
 @v2i64 = global <2 x i64> <i64 0, i64 0>
 @i32 = global i32 0
 @i64 = global i64 0
 
 define void @const_v16i8() nounwind {
   ; ALL-LABEL: const_v16i8:
 
   store volatile <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8>*@v16i8
   ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
 
   store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <16 x i8>*@v16i8
   ; ALL: ldi.b [[R1:\$w[0-9]+]], 1
 
   store volatile <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 31>, <16 x i8>*@v16i8
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.b  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6>, <16 x i8>*@v16i8
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.b  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <16 x i8> <i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0, i8 1, i8 0>, <16 x i8>*@v16i8
-  ; MIPS32-BE: ldi.h [[R1:\$w[0-9]+]], 256
-  ; MIPS32-LE: ldi.h [[R1:\$w[0-9]+]], 1
+  ; ALL-BE: ldi.h [[R1:\$w[0-9]+]], 256
+  ; ALL-LE: ldi.h [[R1:\$w[0-9]+]], 1
 
   store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4, i8 1, i8 2, i8 3, i8 4>, <16 x i8>*@v16i8
-  ; MIPS32-BE-DAG: lui [[R2:\$[0-9]+]], 258
-  ; MIPS32-LE-DAG: lui [[R2:\$[0-9]+]], 1027
-  ; MIPS32-BE-DAG: ori [[R2]], [[R2]], 772
-  ; MIPS32-LE-DAG: ori [[R2]], [[R2]], 513
+  ; ALL-BE-DAG: lui [[R2:\$[0-9]+]], 258
+  ; ALL-LE-DAG: lui [[R2:\$[0-9]+]], 1027
+  ; ALL-BE-DAG: ori [[R2]], [[R2]], 772
+  ; ALL-LE-DAG: ori [[R2]], [[R2]], 513
   ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
 
   store volatile <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <16 x i8>*@v16i8
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.b  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   ret void
 }
 
 define void @const_v8i16() nounwind {
   ; ALL-LABEL: const_v8i16:
 
   store volatile <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i16>*@v8i16
   ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
 
   store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, <8 x i16>*@v8i16
   ; ALL: ldi.h [[R1:\$w[0-9]+]], 1
 
   store volatile <8 x i16> <i16 1, i16 1, i16 1, i16 2, i16 1, i16 1, i16 1, i16 31>, <8 x i16>*@v8i16
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.h  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <8 x i16> <i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028>, <8 x i16>*@v8i16
   ; ALL: ldi.b [[R1:\$w[0-9]+]], 4
 
   store volatile <8 x i16> <i16 1, i16 2, i16 1, i16 2, i16 1, i16 2, i16 1, i16 2>, <8 x i16>*@v8i16
-  ; MIPS32-BE-DAG: lui [[R2:\$[0-9]+]], 1
-  ; MIPS32-LE-DAG: lui [[R2:\$[0-9]+]], 2
-  ; MIPS32-BE-DAG: ori [[R2]], [[R2]], 2
-  ; MIPS32-LE-DAG: ori [[R2]], [[R2]], 1
+  ; ALL-BE-DAG: lui [[R2:\$[0-9]+]], 1
+  ; ALL-LE-DAG: lui [[R2:\$[0-9]+]], 2
+  ; ALL-BE-DAG: ori [[R2]], [[R2]], 2
+  ; ALL-LE-DAG: ori [[R2]], [[R2]], 1
   ; ALL-DAG: fill.w [[R1:\$w[0-9]+]], [[R2]]
 
   store volatile <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 1, i16 2, i16 3, i16 4>, <8 x i16>*@v8i16
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.h  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   ret void
 }
 
 define void @const_v4i32() nounwind {
   ; ALL-LABEL: const_v4i32:
 
   store volatile <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32>*@v4i32
   ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
 
   store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32>*@v4i32
   ; ALL: ldi.w [[R1:\$w[0-9]+]], 1
 
   store volatile <4 x i32> <i32 1, i32 1, i32 1, i32 31>, <4 x i32>*@v4i32
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <4 x i32> <i32 16843009, i32 16843009, i32 16843009, i32 16843009>, <4 x i32>*@v4i32
   ; ALL: ldi.b [[R1:\$w[0-9]+]], 1
 
   store volatile <4 x i32> <i32 65537, i32 65537, i32 65537, i32 65537>, <4 x i32>*@v4i32
   ; ALL: ldi.h [[R1:\$w[0-9]+]], 1
 
   store volatile <4 x i32> <i32 1, i32 2, i32 1, i32 2>, <4 x i32>*@v4i32
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <4 x i32> <i32 3, i32 4, i32 5, i32 6>, <4 x i32>*@v4i32
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   ret void
 }
 
 define void @const_v2i64() nounwind {
   ; ALL-LABEL: const_v2i64:
 
   store volatile <2 x i64> <i64 0, i64 0>, <2 x i64>*@v2i64
   ; ALL: ldi.b [[R1:\$w[0-9]+]], 0
 
   store volatile <2 x i64> <i64 72340172838076673, i64 72340172838076673>, <2 x i64>*@v2i64
   ; ALL: ldi.b [[R1:\$w[0-9]+]], 1
 
   store volatile <2 x i64> <i64 281479271743489, i64 281479271743489>, <2 x i64>*@v2i64
   ; ALL: ldi.h [[R1:\$w[0-9]+]], 1
 
   store volatile <2 x i64> <i64 4294967297, i64 4294967297>, <2 x i64>*@v2i64
   ; ALL: ldi.w [[R1:\$w[0-9]+]], 1
 
   store volatile <2 x i64> <i64 1, i64 1>, <2 x i64>*@v2i64
   ; ALL: ldi.d [[R1:\$w[0-9]+]], 1
 
   store volatile <2 x i64> <i64 1, i64 31>, <2 x i64>*@v2i64
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; ALL: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; MIPS64: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <2 x i64> <i64 3, i64 4>, <2 x i64>*@v2i64
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
-  ; ALL: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; MIPS32: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
+  ; MIPS64: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   ret void
 }
 
 define void @nonconst_v16i8(i8 signext %a, i8 signext %b, i8 signext %c, i8 signext %d, i8 signext %e, i8 signext %f, i8 signext %g, i8 signext %h) nounwind {
   ; ALL-LABEL: nonconst_v16i8:
 
   %1 = insertelement <16 x i8> undef, i8 %a, i32 0
define void @nonconst_v16i8(i8 signext %a, i8 signext %b, i8 signext %c, i8 signext %d, i8 signext %e, i8 signext %f, i8 signext %g, i8 signext %h) nounwind {
   %13 = insertelement <16 x i8> %12, i8 %h, i32 12
   %14 = insertelement <16 x i8> %13, i8 %h, i32 13
   %15 = insertelement <16 x i8> %14, i8 %h, i32 14
   %16 = insertelement <16 x i8> %15, i8 %h, i32 15
   ; ALL-DAG: insert.b [[R1:\$w[0-9]+]][0], $4
   ; ALL-DAG: insert.b [[R1]][1], $5
   ; ALL-DAG: insert.b [[R1]][2], $6
   ; ALL-DAG: insert.b [[R1]][3], $7
-  ; ALL-DAG: lw [[R2:\$[0-9]+]], 16($sp)
-  ; ALL-DAG: insert.b [[R1]][4], [[R2]]
-  ; ALL-DAG: lw [[R3:\$[0-9]+]], 20($sp)
-  ; ALL-DAG: insert.b [[R1]][5], [[R3]]
-  ; ALL-DAG: lw [[R4:\$[0-9]+]], 24($sp)
-  ; ALL-DAG: insert.b [[R1]][6], [[R4]]
-  ; ALL-DAG: lw [[R5:\$[0-9]+]], 28($sp)
-  ; ALL-DAG: insert.b [[R1]][7], [[R5]]
+  ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 16($sp)
+  ; MIPS32-DAG: insert.b [[R1]][4], [[R2]]
+  ; MIPS64-DAG: insert.b [[R1]][4], $8
+  ; MIPS32-DAG: lw [[R3:\$[0-9]+]], 20($sp)
+  ; MIPS32-DAG: insert.b [[R1]][5], [[R3]]
+  ; MIPS64-DAG: insert.b [[R1]][5], $9
+  ; MIPS32-DAG: lw [[R4:\$[0-9]+]], 24($sp)
+  ; MIPS32-DAG: insert.b [[R1]][6], [[R4]]
+  ; MIPS64-DAG: insert.b [[R1]][6], $10
+  ; MIPS32-DAG: lw [[R5:\$[0-9]+]], 28($sp)
+  ; MIPS32-DAG: insert.b [[R1]][7], [[R5]]
+  ; MIPS64-DAG: insert.b [[R1]][7], [[R5:\$11]]
   ; ALL-DAG: insert.b [[R1]][8], [[R5]]
   ; ALL-DAG: insert.b [[R1]][9], [[R5]]
   ; ALL-DAG: insert.b [[R1]][10], [[R5]]
   ; ALL-DAG: insert.b [[R1]][11], [[R5]]
   ; ALL-DAG: insert.b [[R1]][12], [[R5]]
   ; ALL-DAG: insert.b [[R1]][13], [[R5]]
   ; ALL-DAG: insert.b [[R1]][14], [[R5]]
   ; ALL-DAG: insert.b [[R1]][15], [[R5]]
define void @nonconst_v8i16(i16 signext %a, i16 signext %b, i16 signext %c, i16 signext %d, i16 signext %e, i16 signext %f, i16 signext %g, i16 signext %h) nounwind {
   %5 = insertelement <8 x i16> %4, i16 %e, i32 4
   %6 = insertelement <8 x i16> %5, i16 %f, i32 5
   %7 = insertelement <8 x i16> %6, i16 %g, i32 6
   %8 = insertelement <8 x i16> %7, i16 %h, i32 7
   ; ALL-DAG: insert.h [[R1:\$w[0-9]+]][0], $4
   ; ALL-DAG: insert.h [[R1]][1], $5
   ; ALL-DAG: insert.h [[R1]][2], $6
   ; ALL-DAG: insert.h [[R1]][3], $7
-  ; ALL-DAG: lw [[R2:\$[0-9]+]], 16($sp)
-  ; ALL-DAG: insert.h [[R1]][4], [[R2]]
-  ; ALL-DAG: lw [[R2:\$[0-9]+]], 20($sp)
-  ; ALL-DAG: insert.h [[R1]][5], [[R2]]
-  ; ALL-DAG: lw [[R2:\$[0-9]+]], 24($sp)
-  ; ALL-DAG: insert.h [[R1]][6], [[R2]]
-  ; ALL-DAG: lw [[R2:\$[0-9]+]], 28($sp)
-  ; ALL-DAG: insert.h [[R1]][7], [[R2]]
+  ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 16($sp)
+  ; MIPS32-DAG: insert.h [[R1]][4], [[R2]]
+  ; MIPS64-DAG: insert.h [[R1]][4], $8
+  ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 20($sp)
+  ; MIPS32-DAG: insert.h [[R1]][5], [[R2]]
+  ; MIPS64-DAG: insert.h [[R1]][5], $9
+  ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 24($sp)
+  ; MIPS32-DAG: insert.h [[R1]][6], [[R2]]
+  ; MIPS64-DAG: insert.h [[R1]][6], $10
+  ; MIPS32-DAG: lw [[R2:\$[0-9]+]], 28($sp)
+  ; MIPS32-DAG: insert.h [[R1]][7], [[R2]]
+  ; MIPS64-DAG: insert.h [[R1]][7], $11
 
   store volatile <8 x i16> %8, <8 x i16>*@v8i16
 
   ret void
 }
 
 define void @nonconst_v4i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
   ; ALL-LABEL: nonconst_v4i32:
define void @nonconst_v4i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
   ret void
 }
 
 define void @nonconst_v2i64(i64 signext %a, i64 signext %b) nounwind {
   ; ALL-LABEL: nonconst_v2i64:
 
   %1 = insertelement <2 x i64> undef, i64 %a, i32 0
   %2 = insertelement <2 x i64> %1, i64 %b, i32 1
-  ; ALL: insert.w [[R1:\$w[0-9]+]][0], $4
-  ; ALL: insert.w [[R1]][1], $5
-  ; ALL: insert.w [[R1]][2], $6
-  ; ALL: insert.w [[R1]][3], $7
+  ; MIPS32: insert.w [[R1:\$w[0-9]+]][0], $4
+  ; MIPS32: insert.w [[R1]][1], $5
+  ; MIPS32: insert.w [[R1]][2], $6
+  ; MIPS32: insert.w [[R1]][3], $7
+  ; MIPS64: insert.d [[R1:\$w[0-9]+]][0], $4
+  ; MIPS64: insert.d [[R1]][1], $5
 
   store volatile <2 x i64> %2, <2 x i64>*@v2i64
 
   ret void
 }
 
 define i32 @extract_sext_v16i8() nounwind {
   ; ALL-LABEL: extract_sext_v16i8:
define i64 @extract_sext_v2i64() nounwind {
 
   %1 = load <2 x i64>, <2 x i64>* @v2i64
   ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],
 
   %2 = add <2 x i64> %1, %1
   ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <2 x i64> %2, i32 1
-  ; ALL-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][2]
-  ; ALL-DAG: copy_s.w [[R4:\$[0-9]+]], [[R1]][3]
+  ; MIPS32-DAG: copy_s.w [[R3:\$[0-9]+]], [[R1]][2]
+  ; MIPS32-DAG: copy_s.w [[R4:\$[0-9]+]], [[R1]][3]
+  ; MIPS64-DAG: copy_s.d [[R3:\$[0-9]+]], [[R1]][1]
   ; ALL-NOT: sll
   ; ALL-NOT: sra
 
   ret i64 %3
 }
 
 define i32 @extract_zext_v16i8() nounwind {
   ; ALL-LABEL: extract_zext_v16i8:
define i64 @extract_zext_v2i64() nounwind {
 
   %1 = load <2 x i64>, <2 x i64>* @v2i64
   ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],
 
   %2 = add <2 x i64> %1, %1
   ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = extractelement <2 x i64> %2, i32 1
-  ; ALL-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][2]
-  ; ALL-DAG: copy_{{[su]}}.w [[R4:\$[0-9]+]], [[R1]][3]
+  ; MIPS32-DAG: copy_{{[su]}}.w [[R3:\$[0-9]+]], [[R1]][2]
+  ; MIPS32-DAG: copy_{{[su]}}.w [[R4:\$[0-9]+]], [[R1]][3]
+  ; MIPS64-DAG: copy_{{[su]}}.d [[R3:\$[0-9]+]], [[R1]][1]
   ; ALL-NOT: andi
 
   ret i64 %3
 }
 
 define i32 @extract_sext_v16i8_vidx() nounwind {
   ; ALL-LABEL: extract_sext_v16i8_vidx:
 
   %1 = load <16 x i8>, <16 x i8>* @v16i8
-  ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v16i8)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v16i8)(
   ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <16 x i8> %1, %1
   ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <16 x i8> %2, i32 %3
   %5 = sext i8 %4 to i32
   ; ALL-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
   ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
   ; ALL-DAG: sra [[R6:\$[0-9]+]], [[R5]], 24
 
   ret i32 %5
 }
 
 define i32 @extract_sext_v8i16_vidx() nounwind {
   ; ALL-LABEL: extract_sext_v8i16_vidx:
 
   %1 = load <8 x i16>, <8 x i16>* @v8i16
-  ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v8i16)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v8i16)(
   ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <8 x i16> %1, %1
   ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <8 x i16> %2, i32 %3
   %5 = sext i16 %4 to i32
   ; ALL-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
   ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
   ; ALL-DAG: sra [[R6:\$[0-9]+]], [[R5]], 16
 
   ret i32 %5
 }
 
 define i32 @extract_sext_v4i32_vidx() nounwind {
   ; ALL-LABEL: extract_sext_v4i32_vidx:
 
   %1 = load <4 x i32>, <4 x i32>* @v4i32
-  ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4i32)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4i32)(
   ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <4 x i32> %1, %1
   ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <4 x i32> %2, i32 %3
   ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
   ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
   ; ALL-NOT: sra
 
   ret i32 %4
 }
 
 define i64 @extract_sext_v2i64_vidx() nounwind {
   ; ALL-LABEL: extract_sext_v2i64_vidx:
 
   %1 = load <2 x i64>, <2 x i64>* @v2i64
-  ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2i64)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2i64)(
   ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <2 x i64> %1, %1
   ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <2 x i64> %2, i32 %3
-  ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
-  ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
-  ; ALL-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
-  ; ALL-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
+  ; MIPS32-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; MIPS32-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
+  ; MIPS64-DAG: splat.d $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS64-DAG: dmfc1 [[R5:\$[0-9]+]], $f[[R3]]
   ; ALL-NOT: sra
 
   ret i64 %4
 }
 
 define i32 @extract_zext_v16i8_vidx() nounwind {
   ; ALL-LABEL: extract_zext_v16i8_vidx:
 
   %1 = load <16 x i8>, <16 x i8>* @v16i8
-  ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v16i8)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v16i8)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v16i8)(
   ; ALL-DAG: ld.b [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <16 x i8> %1, %1
   ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <16 x i8> %2, i32 %3
   %5 = zext i8 %4 to i32
   ; ALL-DAG: splat.b $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
   ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
   ; ALL-DAG: srl [[R6:\$[0-9]+]], [[R5]], 24
 
   ret i32 %5
 }
 
 define i32 @extract_zext_v8i16_vidx() nounwind {
   ; ALL-LABEL: extract_zext_v8i16_vidx:
 
   %1 = load <8 x i16>, <8 x i16>* @v8i16
-  ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v8i16)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v8i16)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v8i16)(
   ; ALL-DAG: ld.h [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <8 x i16> %1, %1
   ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <8 x i16> %2, i32 %3
   %5 = zext i16 %4 to i32
   ; ALL-DAG: splat.h $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
   ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
   ; ALL-DAG: srl [[R6:\$[0-9]+]], [[R5]], 16
 
   ret i32 %5
 }
 
 define i32 @extract_zext_v4i32_vidx() nounwind {
   ; ALL-LABEL: extract_zext_v4i32_vidx:
 
   %1 = load <4 x i32>, <4 x i32>* @v4i32
-  ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4i32)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4i32)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4i32)(
   ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <4 x i32> %1, %1
   ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <4 x i32> %2, i32 %3
   ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
   ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
   ; ALL-NOT: srl
 
   ret i32 %4
 }
 
 define i64 @extract_zext_v2i64_vidx() nounwind {
   ; ALL-LABEL: extract_zext_v2i64_vidx:
 
   %1 = load <2 x i64>, <2 x i64>* @v2i64
-  ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2i64)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2i64)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2i64)(
   ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = add <2 x i64> %1, %1
   ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <2 x i64> %2, i32 %3
-  ; ALL-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
-  ; ALL-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
-  ; ALL-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
-  ; ALL-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
+  ; MIPS32-DAG: splat.w $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-DAG: mfc1 [[R5:\$[0-9]+]], $f[[R3]]
+  ; MIPS32-DAG: splat.w $w[[R4:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS32-DAG: mfc1 [[R6:\$[0-9]+]], $f[[R4]]
+  ; MIPS64-DAG: splat.d $w[[R3:[0-9]+]], [[R1]]{{\[}}[[IDX]]]
+  ; MIPS64-DAG: dmfc1 [[R5:\$[0-9]+]], $f[[R3]]
   ; ALL-NOT: srl
 
   ret i64 %4
 }
 
 define void @insert_v16i8(i32 signext %a) nounwind {
   ; ALL-LABEL: insert_v16i8:
 
define void @insert_v4i32(i32 signext %a) nounwind {
 
   ret void
 }
 
 define void @insert_v2i64(i64 signext %a) nounwind {
   ; ALL-LABEL: insert_v2i64:
 
   %1 = load <2 x i64>, <2 x i64>* @v2i64
-  ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
+  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
+  ; MIPS64-DAG: ld.d [[R1:\$w[0-9]+]],
 
   ; ALL-NOT: andi
   ; ALL-NOT: sra
 
   %2 = insertelement <2 x i64> %1, i64 %a, i32 1
-  ; ALL-DAG: insert.w [[R1]][2], $4
-  ; ALL-DAG: insert.w [[R1]][3], $5
+  ; MIPS32-DAG: insert.w [[R1]][2], $4
+  ; MIPS32-DAG: insert.w [[R1]][3], $5
+  ; MIPS64-DAG: insert.d [[R1]][1], $4
 
   store <2 x i64> %2, <2 x i64>* @v2i64
-  ; ALL-DAG: st.w [[R1]]
+  ; MIPS32-DAG: st.w [[R1]]
+  ; MIPS64-DAG: st.d [[R1]]
 
   ret void
 }
 
 define void @insert_v16i8_vidx(i32 signext %a) nounwind {
   ; ALL-LABEL: insert_v16i8_vidx:
 
   %1 = load <16 x i8>, <16 x i8>* @v16i8
   ; ALL-DAG: ld.b [[R1:\$w[0-9]+]],
 
   %2 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %a2 = trunc i32 %a to i8
   %a3 = sext i8 %a2 to i32
   %a4 = trunc i32 %a3 to i8
   ; ALL-NOT: andi
   ; ALL-NOT: sra
 
   %3 = insertelement <16 x i8> %1, i8 %a4, i32 %2
   ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[IDX]]]
   ; ALL-DAG: insert.b [[R1]][0], $4
-  ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]]
+  ; O32-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]]
+  ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[IDX]]
+  ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[IDX]]
   ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
 
   store <16 x i8> %3, <16 x i8>* @v16i8
   ; ALL-DAG: st.b [[R1]]
 
   ret void
 }
 
-define void @insert_v8i16_vidx(i32 %a) nounwind {
+define void @insert_v8i16_vidx(i32 signext %a) nounwind {
   ; ALL-LABEL: insert_v8i16_vidx:
 
   %1 = load <8 x i16>, <8 x i16>* @v8i16
   ; ALL-DAG: ld.h [[R1:\$w[0-9]+]],
 
   %2 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %a2 = trunc i32 %a to i16
   %a3 = sext i16 %a2 to i32
   %a4 = trunc i32 %a3 to i16
   ; ALL-NOT: andi
   ; ALL-NOT: sra
 
   %3 = insertelement <8 x i16> %1, i16 %a4, i32 %2
   ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 1
   ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
   ; ALL-DAG: insert.h [[R1]][0], $4
-  ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; O32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[BIDX]]
   ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
 
   store <8 x i16> %3, <8 x i16>* @v8i16
   ; ALL-DAG: st.h [[R1]]
 
   ret void
 }
 
 define void @insert_v4i32_vidx(i32 signext %a) nounwind {
   ; ALL-LABEL: insert_v4i32_vidx:
 
   %1 = load <4 x i32>, <4 x i32>* @v4i32
   ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
 
   %2 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   ; ALL-NOT: andi
   ; ALL-NOT: sra
 
   %3 = insertelement <4 x i32> %1, i32 %a, i32 %2
   ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
   ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
   ; ALL-DAG: insert.w [[R1]][0], $4
   ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
   ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
 
   store <4 x i32> %3, <4 x i32>* @v4i32
   ; ALL-DAG: st.w [[R1]]
 
   ret void
 }
 
 define void @insert_v2i64_vidx(i64 signext %a) nounwind {
   ; ALL-LABEL: insert_v2i64_vidx:
 
   %1 = load <2 x i64>, <2 x i64>* @v2i64
-  ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
+  ; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
+  ; MIPS64-DAG: ld.d [[R1:\$w[0-9]+]],
 
   %2 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   ; ALL-NOT: andi
   ; ALL-NOT: sra
 
   %3 = insertelement <2 x i64> %1, i64 %a, i32 %2
   ; TODO: This code could be a lot better but it works. The legalizer splits
   ; 64-bit inserts into two 32-bit inserts because there is no i64 type on
   ; MIPS32. The obvious optimisation is to perform both insert.w's at once while
   ; the vector is rotated.
-  ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
-  ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
-  ; ALL-DAG: insert.w [[R1]][0], $4
-  ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
-  ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
-  ; ALL-DAG: addiu [[IDX2:\$[0-9]+]], [[IDX]], 1
-  ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX2]], 2
-  ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
-  ; ALL-DAG: insert.w [[R1]][0], $5
-  ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
-  ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+  ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
+  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; MIPS32-DAG: insert.w [[R1]][0], $4
+  ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+  ; MIPS32-DAG: addiu [[IDX2:\$[0-9]+]], [[IDX]], 1
+  ; MIPS32-DAG: sll [[BIDX:\$[0-9]+]], [[IDX2]], 2
+  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; MIPS32-DAG: insert.w [[R1]][0], $5
+  ; MIPS32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; MIPS32-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
+
+  ; MIPS64-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3
+  ; MIPS64-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
+  ; MIPS64-DAG: insert.d [[R1]][0], $4
+  ; N32-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; N64-DAG: dneg [[NIDX:\$[0-9]+]], [[BIDX]]
+  ; MIPS64-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
 
   store <2 x i64> %3, <2 x i64>* @v2i64
-  ; ALL-DAG: st.w [[R1]]
+  ; MIPS32-DAG: st.w [[R1]]
+  ; MIPS64-DAG: st.d [[R1]]
 
   ret void
 }
 
 define void @truncstore() nounwind {
   ; ALL-LABEL: truncstore:
 
   store volatile <4 x i8> <i8 -1, i8 -1, i8 -1, i8 -1>, <4 x i8>*@v4i8
   ; TODO: What code should be emitted?
 
   ret void
 }

test/CodeGen/Mips/msa/basic_operations_float.ll

-; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL %s
+; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 %s
+; RUN: llc -march=mips64 -target-abi=n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 %s
+; RUN: llc -march=mips64el -target-abi=n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 %s
 
 @v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
 @v2f64 = global <2 x double> <double 0.0, double 0.0>
 @i32 = global i32 0
 @f32 = global float 0.0
 @f64 = global double 0.0
 
 define void @const_v4f32() nounwind {
   ; ALL-LABEL: const_v4f32:
 
   store volatile <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>*@v4f32
   ; ALL: ldi.b  [[R1:\$w[0-9]+]], 0
 
   store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float>*@v4f32
   ; ALL: lui     [[R1:\$[0-9]+]], 16256
   ; ALL: fill.w  [[R2:\$w[0-9]+]], [[R1]]
 
   store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
   ; ALL: lui     [[R1:\$[0-9]+]], 18304
   ; ALL: ori     [[R2:\$[0-9]+]], [[R1]], 128
   ; ALL: fill.w  [[R3:\$w[0-9]+]], [[R2]]
 
   store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.w  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   ret void
 }
 
 define void @const_v2f64() nounwind {
   ; ALL-LABEL: const_v2f64:
 
   store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64
   ; ALL: ldi.b  [[R1:\$w[0-9]+]], 0
 
   store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
-  ; ALL: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; O32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
+  ; N32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
+  ; N64: daddiu [[G_PTR:\$[0-9]+]], {{.*}}, %got_ofst($
   ; ALL: ld.d  [[R1:\$w[0-9]+]], 0([[G_PTR]])
 
   ret void
 }
 
 define void @nonconst_v4f32() nounwind {
   ; ALL-LABEL: nonconst_v4f32:
 
define float @extract_v4f32_elt2() nounwind {
 
   ret float %3
 }
 
 define float @extract_v4f32_vidx() nounwind {
   ; ALL-LABEL: extract_v4f32_vidx:
 
   %1 = load <4 x float>, <4 x float>* @v4f32
-  ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(
   ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = fadd <4 x float> %1, %1
   ; ALL-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <4 x float> %2, i32 %3
   ; ALL-DAG: splat.w $w0, [[R1]]{{\[}}[[IDX]]]
 
   ret float %4
 }
 
define double @extract_v2f64_elt0() nounwind {
 
   ret double %3
 }
 
 define double @extract_v2f64_vidx() nounwind {
   ; ALL-LABEL: extract_v2f64_vidx:
 
   %1 = load <2 x double>, <2 x double>* @v2f64
-  ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(
   ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = fadd <2 x double> %1, %1
   ; ALL-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
 
   %3 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %4 = extractelement <2 x double> %2, i32 %3
   ; ALL-DAG: splat.d $w0, [[R1]]{{\[}}[[IDX]]]
 
   ret double %4
 }
 
define void @insert_v2f64(double %a) nounwind {
 
   ret void
 }
 
 define void @insert_v4f32_vidx(float %a) nounwind {
   ; ALL-LABEL: insert_v4f32_vidx:
 
   %1 = load <4 x float>, <4 x float>* @v4f32
-  ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v4f32)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v4f32)(
   ; ALL-DAG: ld.w [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %3 = insertelement <4 x float> %1, float %a, i32 %2
   ; float argument passed in $f12
   ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 2
   ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
   ; ALL-DAG: insve.w [[R1]][0], $w12[0]
   ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
   ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
 
   store <4 x float> %3, <4 x float>* @v4f32
   ; ALL-DAG: st.w [[R1]]
 
   ret void
 }
 
 define void @insert_v2f64_vidx(double %a) nounwind {
   ; ALL-LABEL: insert_v2f64_vidx:
 
   %1 = load <2 x double>, <2 x double>* @v2f64
-  ; ALL-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
+  ; O32-DAG: lw [[PTR_V:\$[0-9]+]], %got(v2f64)(
+  ; N32-DAG: lw [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(
+  ; N64-DAG: ld [[PTR_V:\$[0-9]+]], %got_disp(v2f64)(
   ; ALL-DAG: ld.d [[R1:\$w[0-9]+]], 0([[PTR_V]])
 
   %2 = load i32, i32* @i32
-  ; ALL-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; O32-DAG: lw [[PTR_I:\$[0-9]+]], %got(i32)(
+  ; N32-DAG: lw [[PTR_I:\$[0-9]+]], %got_disp(i32)(
+  ; N64-DAG: ld [[PTR_I:\$[0-9]+]], %got_disp(i32)(
   ; ALL-DAG: lw [[IDX:\$[0-9]+]], 0([[PTR_I]])
 
   %3 = insertelement <2 x double> %1, double %a, i32 %2
   ; double argument passed in $f12
   ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[IDX]], 3
   ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[BIDX]]]
   ; ALL-DAG: insve.d [[R1]][0], $w12[0]
   ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
   ; ALL-DAG: sld.b [[R1]], [[R1]]{{\[}}[[NIDX]]]
 
   store <2 x double> %3, <2 x double>* @v2f64
   ; ALL-DAG: st.d [[R1]]
 
   ret void
 }

test/MC/Disassembler/Mips/mips3/valid-mips3.txt

 0x03 0x2b 0x00 0x1a # CHECK: div $zero, $25, $11
 0x46 0x3a 0xa7 0x03 # CHECK: div.d $f28, $f20, $f26
 0x46 0x0f 0x29 0x03 # CHECK: div.s $f4, $f5, $f15
 0x03 0x2f 0x00 0x1b # CHECK: divu $zero, $25, $15
 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
+0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
+0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
 0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
 0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
 0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
 0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10
 0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10

test/MC/Disassembler/Mips/mips4/valid-mips4.txt

 0x03 0x2b 0x00 0x1a # CHECK: div $zero, $25, $11
 0x46 0x3a 0xa7 0x03 # CHECK: div.d $f28, $f20, $f26
 0x46 0x0f 0x29 0x03 # CHECK: div.s $f4, $f5, $f15
 0x03 0x2f 0x00 0x1b # CHECK: divu $zero, $25, $15
 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
+0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
+0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
 0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
 0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
 0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
 0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10
 0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10

test/MC/Disassembler/Mips/mips64/valid-mips64.txt

 0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6
 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
 0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
+0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
+0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
 0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
 0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
 0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
 0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10
 0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10

test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt

 0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6
 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
 0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
+0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
+0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
 0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
 0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
 0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
 0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10
 0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10

test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt

 0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6
 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
 0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
+0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
+0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
 0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
 0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
 0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
 0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10
 0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10

test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt

 0x70 0xd2 0x90 0x25 # CHECK: dclo $18, $6
 0x73 0x30 0x80 0x24 # CHECK: dclz $16, $25
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
 0x02 0x11 0x00 0x1f # CHECK: ddivu $zero, $16, $17
 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x00 0xa6 0x00 0x1d # CHECK: dmultu $5, $6
+0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
+0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x00 0x00 0x04 0xb8 # CHECK: dsll $zero, $zero, 18
 0x00 0x14 0x04 0xb8 # CHECK: dsll $zero, $20, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
 0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
 0x00 0x00 0x04 0xbc # CHECK: dsll32 $zero, $zero, 18
 0x01 0x94 0x00 0x14 # CHECK: dsllv $zero, $20, $12
 0x00 0x1c 0xe2 0xbb # CHECK: dsra $gp, $gp, 10
 0x00 0x12 0xe2 0xbb # CHECK: dsra $gp, $18, 10

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt

 0x00 0x64 0x10 0x9b # CHECK: divu $2, $3, $4
 0x00 0x64 0x10 0xd5 # CHECK: dlsa $2, $3, $4, 3
 0x00 0x64 0x10 0xde # CHECK: dmod $2, $3, $4
 0x00 0x64 0x10 0xdf # CHECK: dmodu $2, $3, $4
 0x00 0x64 0x10 0xdc # CHECK: dmuh $2, $3, $4
 0x00 0x64 0x10 0xdd # CHECK: dmuhu $2, $3, $4
 0x00 0x64 0x10 0x9c # CHECK: dmul $2, $3, $4
 0x00 0x64 0x10 0x9d # CHECK: dmulu $2, $3, $4
+0x00 0x03 0x10 0x2e # CHECK: dneg $2, $3
+0x00 0x03 0x10 0x2f # CHECK: dnegu $2, $3
 0x41 0x60 0x60 0x20 # CHECK: ei
 0x41 0x6e 0x60 0x20 # CHECK: ei $14
 0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
 0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
 0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
 0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
 0x00 0x80 0x04 0x09 # CHECK: jr.hb $4
 0x49 0xc8 0x0d 0x43 # CHECK: ldc2 $8, -701($1)

test/MC/Mips/mips1/invalid-mips3.s

.set noat
         daddu     $s3,$at,$ra       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         daddu     $24,$2,18079      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         daddu     $19,26943         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         ddiv      $zero,$k0,$s3     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         ddivu     $zero,$s0,$s1     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dmfc1     $12,$f13          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dmtc1     $s0,$f14          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dmultu    $a1,$a2           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dneg      $2                # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dneg      $2,$3             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dnegu     $2,$3             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll      $zero,18          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll      $zero,$s4,18      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll      $zero,$s4,$12     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll32    $zero,18          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll32    $zero,$zero,18    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsllv     $zero,$s4,$12     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsra      $gp,10            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsra      $gp,$s2,10        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

test/MC/Mips/mips2/invalid-mips3.s

# RUN: FileCheck %s < %t1
         daddu      $s3,$at,$ra       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         daddu      $24,$2,18079      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         daddu      $19,26943         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         ddiv       $zero,$k0,$s3     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         ddivu      $zero,$s0,$s1     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dmfc1      $t0,$f13          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dmtc1      $s0,$f14          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dmultu     $a1,$a2           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dneg       $2                # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dneg       $2,$3             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dnegu      $2,$3             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll       $zero,18          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll       $zero,$s4,18      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll       $zero,$s4,$t0     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll32     $zero,18          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsll32     $zero,$zero,18    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsllv      $zero,$s4,$t0     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsra       $gp,10            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         dsra       $gp,$s2,10        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

test/MC/Mips/mips3/valid.s

a:
         div       $zero,$25,$11
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
         dmfc1     $12,$f13
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
         dsll      $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
         dsll      $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
         dsll32    $zero,18             # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
         dsll32    $zero,$zero,18       # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
         dsllv     $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
         dsra      $gp,10               # CHECK: dsra $gp, $gp, 10           # encoding: [0x00,0x1c,0xe2,0xbb]
         dsra      $gp,$s2,10           # CHECK: dsra $gp, $18, 10           # encoding: [0x00,0x12,0xe2,0xbb]

test/MC/Mips/mips32/invalid-mips64.s

 # Instructions that are invalid
 #
 # RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips32 \
 # RUN:     2>%t1
 # RUN: FileCheck %s < %t1
 
   .set noat
   dclo  $s2,$a2    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
   dclz  $s0,$t9    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dneg      $2       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dneg      $2,$3    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        dnegu     $2,$3    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

test/MC/Mips/mips4/valid.s

a:
         div       $zero,$25,$11
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
         dmfc1     $12,$f13
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
         dsll      $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
         dsll      $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
         dsll32    $zero,18             # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
         dsll32    $zero,$zero,18       # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
         dsllv     $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
         dsra      $gp,10               # CHECK: dsra $gp, $gp, 10           # encoding: [0x00,0x1c,0xe2,0xbb]
         dsra      $gp,$s2,10           # CHECK: dsra $gp, $18, 10           # encoding: [0x00,0x12,0xe2,0xbb]

test/MC/Mips/mips5/valid.s

a:
         div       $zero,$25,$11
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
         dmfc1     $12,$f13
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
         dsll      $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
         dsll      $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
         dsll32    $zero,18             # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
         dsll32    $zero,$zero,18       # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
         dsllv     $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
         dsra      $gp,10               # CHECK: dsra $gp, $gp, 10           # encoding: [0x00,0x1c,0xe2,0xbb]
         dsra      $gp,$s2,10           # CHECK: dsra $gp, $18, 10           # encoding: [0x00,0x12,0xe2,0xbb]

test/MC/Mips/mips64/valid.s

a:
         div       $zero,$25,$11
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
         dmfc1     $12,$f13
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]
         dsll      $zero,$s4,18         # CHECK: dsll $zero, $20, 18         # encoding: [0x00,0x14,0x04,0xb8]
         dsll      $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
         dsll32    $zero,18             # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
         dsll32    $zero,$zero,18       # CHECK: dsll32 $zero, $zero, 18     # encoding: [0x00,0x00,0x04,0xbc]
         dsllv     $zero,$s4,$12        # CHECK: dsllv $zero, $20, $12       # encoding: [0x01,0x94,0x00,0x14]
         dsra      $gp,10               # CHECK: dsra $gp, $gp, 10           # encoding: [0x00,0x1c,0xe2,0xbb]
         dsra      $gp,$s2,10           # CHECK: dsra $gp, $18, 10           # encoding: [0x00,0x12,0xe2,0xbb]

test/MC/Mips/mips64r2/valid.s

a:
         div       $zero,$25,$11
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
         dmfc1     $12,$f13
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         drotr     $1,15                # CHECK: drotr $1, $1, 15            # encoding: [0x00,0x21,0x0b,0xfa]
         drotr     $1,$14,15            # CHECK: drotr $1, $14, 15           # encoding: [0x00,0x2e,0x0b,0xfa]
         drotr32   $1,15                # CHECK: drotr32 $1, $1, 15          # encoding: [0x00,0x21,0x0b,0xfe]
         drotr32   $1,$14,15            # CHECK: drotr32 $1, $14, 15         # encoding: [0x00,0x2e,0x0b,0xfe]
         drotrv    $1,$14,$15           # CHECK: drotrv $1, $14, $15         # encoding: [0x01,0xee,0x08,0x56]
         dsbh      $v1,$14
         dshd      $v0,$sp
         dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]

test/MC/Mips/mips64r3/valid.s

a:
         div       $zero,$25,$11
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
         dmfc1     $12,$f13
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         drotr     $1,15                # CHECK: drotr $1, $1, 15            # encoding: [0x00,0x21,0x0b,0xfa]
         drotr     $1,$14,15            # CHECK: drotr $1, $14, 15           # encoding: [0x00,0x2e,0x0b,0xfa]
         drotr32   $1,15                # CHECK: drotr32 $1, $1, 15          # encoding: [0x00,0x21,0x0b,0xfe]
         drotr32   $1,$14,15            # CHECK: drotr32 $1, $14, 15         # encoding: [0x00,0x2e,0x0b,0xfe]
         drotrv    $1,$14,$15           # CHECK: drotrv $1, $14, $15         # encoding: [0x01,0xee,0x08,0x56]
         dsbh      $v1,$14
         dshd      $v0,$sp
         dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]

test/MC/Mips/mips64r5/valid.s

a:
         div       $zero,$25,$11
         div.d     $f29,$f20,$f27
         div.s     $f4,$f5,$f15
         divu      $zero,$25,$15
         dmfc1     $12,$f13
         dmtc1     $s0,$f14
         dmult     $s7,$9
         dmultu    $a1,$a2
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         drotr     $1,15                # CHECK: drotr $1, $1, 15            # encoding: [0x00,0x21,0x0b,0xfa]
         drotr     $1,$14,15            # CHECK: drotr $1, $14, 15           # encoding: [0x00,0x2e,0x0b,0xfa]
         drotr32   $1,15                # CHECK: drotr32 $1, $1, 15          # encoding: [0x00,0x21,0x0b,0xfe]
         drotr32   $1,$14,15            # CHECK: drotr32 $1, $14, 15         # encoding: [0x00,0x2e,0x0b,0xfe]
         drotrv    $1,$14,$15           # CHECK: drotrv $1, $14, $15         # encoding: [0x01,0xee,0x08,0x56]
         dsbh      $v1,$14
         dshd      $v0,$sp
         dsll      $zero,18             # CHECK: dsll $zero, $zero, 18       # encoding: [0x00,0x00,0x04,0xb8]

test/MC/Mips/mips64r6/valid.s

a:
         divu    $2,$3,$4         # CHECK: divu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9b]
         dlsa    $2, $3, $4, 3    # CHECK: dlsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xd5]
         dmod    $2,$3,$4         # CHECK: dmod $2, $3, $4  # encoding: [0x00,0x64,0x10,0xde]
         dmodu   $2,$3,$4         # CHECK: dmodu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdf]
         dmuh    $2,$3,$4         # CHECK: dmuh $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdc]
         dmuhu   $2,$3,$4         # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdd]
         dmul    $2,$3,$4         # CHECK: dmul $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9c]
         dmulu   $2,$3,$4         # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9d]
+        dneg      $2                   # CHECK: dneg $2, $2                 # encoding: [0x00,0x02,0x10,0x2e]
+        dneg      $2,$3                # CHECK: dneg $2, $3                 # encoding: [0x00,0x03,0x10,0x2e]
+        dnegu     $2,$3                # CHECK: dnegu $2, $3                # encoding: [0x00,0x03,0x10,0x2f]
         dsubu   $14,-4586        # CHECK: daddiu $14, $14, 4586  # encoding: [0x65,0xce,0x11,0xea]
         dsubu   $15,$11,5025     # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
         ei                       # CHECK: ei               # encoding: [0x41,0x60,0x60,0x20]
         ei      $14              # CHECK: ei  $14          # encoding: [0x41,0x6e,0x60,0x20]
         j       1f               # CHECK: j $tmp0                # encoding: [0b000010AA,A,A,A]
                                  # CHECK:                        #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
         j       a                # CHECK: j a                    # encoding: [0b000010AA,A,A,A]
                                  # CHECK:                        #   fixup A - offset: 0, value: a, kind: fixup_Mips_26