This is an archive of the discontinued LLVM Phabricator instance.

[llvm-tblgen] Fixed 64-bit filters being sliced to 32 bits in FixedLenDecoderEmitter
ClosedPublic

Authored by cameron314 on Dec 1 2020, 1:03 PM.

Details

Summary

When using the FixedLenDecoderEmitter, llvm-tblgen emits tables with (OPC_ExtractField, OPC_ExtractFilterValue) opcode sequences to match the contiguous fixed bits of a given instruction's encoding. This encoding is represented in a 64-bit integer. However, the filter values were represented in a 32-bit integer. As such, instructions with fixed 64-bit encodings (a rare case, but one which occurs in our backend) resulted in a table with an OPC_ExtractField for all 64 bits, followed by an OPC_ExtractFilterValue containing just the low 32 bits of their encoding, causing the filter never to match.

The exact point at which the slicing occurred is line 631.

Diff Detail

Event Timeline

cameron314 created this revision.Dec 1 2020, 1:03 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 1 2020, 1:03 PM
cameron314 requested review of this revision.Dec 1 2020, 1:03 PM

Does it make sense to define a const for the value (uint64_t)-1?

Possibly dumb question: There are places where the opcode (Opc) is declared as unsigned. Is that okay?

I can add a constant.

As far as I understand it, the various unsigned Opc variables actually refer to an opcode ID (in NumberedEncodings) and not the instruction encoding itself, so they should be OK.

cameron314 updated this revision to Diff 308762.Dec 1 2020, 1:54 PM
This revision is now accepted and ready to land.Dec 14 2020, 8:57 AM