[TableGen][SchedModels] Simplify the code. NFC

[evgeny777]

Summary

Patch takes advantage of having only one processor index in PredTransition which is not zero.

[evgeny777]

Also simplify CodeGenSchedTransition

[dmgreen]

From what I can tell, this LGTM. It took a while to figure out all the changes.

llvm/utils/TableGen/CodeGenSchedule.h

 #ifndef NDEBUG
   void dump() const;
 #endif
 };
 
 /// Represent a transition between SchedClasses induced by SchedVariant.
 struct CodeGenSchedTransition {
   unsigned ToClassIdx;
-  IdxVec ProcIndices;
+  unsigned ProcIndex;
   RecVec PredTerm;
 };
 
 /// Scheduling class.
 ///
 /// Each instruction description will be mapped to a scheduling class. There are
 /// four types of classes:
 ///

llvm/utils/TableGen/CodeGenSchedule.cpp

 };
 
 // A Predicate transition is a list of RW sequences guarded by a PredTerm.
 struct PredTransition {
   // A predicate term is a conjunction of PredChecks.
   SmallVector<PredCheck, 4> PredTerm;
   SmallVector<SmallVector<unsigned,4>, 16> WriteSequences;
   SmallVector<SmallVector<unsigned,4>, 16> ReadSequences;
-  SmallVector<unsigned, 4> ProcIndices;
+  unsigned ProcIndex = 0;
 
   PredTransition() = default;
-  PredTransition(ArrayRef<PredCheck> PT) {
+  PredTransition(ArrayRef<PredCheck> PT, unsigned ProcId) {
     PredTerm.assign(PT.begin(), PT.end());
-    ProcIndices.assign(1, 0);
-  }
-  PredTransition(ArrayRef<PredCheck> PT, ArrayRef<unsigned> PIds) {
-    PredTerm.assign(PT.begin(), PT.end());
-    ProcIndices.assign(PIds.begin(), PIds.end());
+    ProcIndex = ProcId;
   }
 };
 
 // Encapsulate a set of partially constructed transitions.
 // The results are built by repeated calls to substituteVariants.
 class PredTransitions {
   CodeGenSchedModels &SchedModels;
 
if (any_of(Variants, [PredDef](const Record *R) {
         continue;
       return true;
     }
   }
   return false;
 }
 
 static std::vector<Record *> getAllPredicates(ArrayRef<TransVariant> Variants,
-                                              ArrayRef<unsigned> ProcIndices) {
+                                              unsigned ProcId) {
   std::vector<Record *> Preds;
   for (auto &Variant : Variants) {
     if (!Variant.VarOrSeqDef->isSubClassOf("SchedVar"))
       continue;
-
-    if (ProcIndices[0] && Variant.ProcIdx)
-      if (!llvm::count(ProcIndices, Variant.ProcIdx))
-        continue;
-
     Preds.push_back(Variant.VarOrSeqDef->getValueAsDef("Predicate"));
   }
   return Preds;
 }
 
 // Populate IntersectingVariants with any variants or aliased sequences of the
 // given SchedRW whose processor indices and predicates are not mutually
 // exclusive with the given transition.
 void PredTransitions::getIntersectingVariants(
   const CodeGenSchedRW &SchedRW, unsigned TransIdx,
   std::vector<TransVariant> &IntersectingVariants) {
 
   bool GenericRW = false;
 
   std::vector<TransVariant> Variants;
   if (SchedRW.HasVariants) {
     unsigned VarProcIdx = 0;
     if (SchedRW.TheDef->getValueInit("SchedModel")->isComplete()) {
       Record *ModelDef = SchedRW.TheDef->getValueAsDef("SchedModel");
       VarProcIdx = SchedModels.getProcModel(ModelDef).Index;
     }
+    if (VarProcIdx == 0 || VarProcIdx == TransVec[TransIdx].ProcIndex) {
       // Push each variant. Assign TransVecIdx later.
       const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");
       for (Record *VarDef : VarDefs)
         Variants.emplace_back(VarDef, SchedRW.Index, VarProcIdx, 0);
       if (VarProcIdx == 0)
         GenericRW = true;
     }
+  }
   for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
        AI != AE; ++AI) {
     // If either the SchedAlias itself or the SchedReadWrite that it aliases
     // to is defined within a processor model, constrain all variants to
     // that processor.
     unsigned AliasProcIdx = 0;
     if ((*AI)->getValueInit("SchedModel")->isComplete()) {
       Record *ModelDef = (*AI)->getValueAsDef("SchedModel");
       AliasProcIdx = SchedModels.getProcModel(ModelDef).Index;
     }
+    if (AliasProcIdx && AliasProcIdx != TransVec[TransIdx].ProcIndex)
+      continue;
+    if (!Variants.empty()) {
+      const CodeGenProcModel &PM =
+          *(SchedModels.procModelBegin() + AliasProcIdx);
+      PrintFatalError((*AI)->getLoc(),
+                      "Multiple variants defined for processor " +
+                          PM.ModelName +
+                          " Ensure only one SchedAlias exists per RW.");
+    }
+
     const CodeGenSchedRW &AliasRW =
       SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
 
     if (AliasRW.HasVariants) {
       const RecVec VarDefs = AliasRW.TheDef->getValueAsListOfDefs("Variants");
       for (Record *VD : VarDefs)
         Variants.emplace_back(VD, AliasRW.Index, AliasProcIdx, 0);
     }
     if (AliasRW.IsSequence)
       Variants.emplace_back(AliasRW.TheDef, SchedRW.Index, AliasProcIdx, 0);
     if (AliasProcIdx == 0)
       GenericRW = true;
   }
   std::vector<Record *> AllPreds =
-      getAllPredicates(Variants, TransVec[TransIdx].ProcIndices);
+      getAllPredicates(Variants, TransVec[TransIdx].ProcIndex);
   for (TransVariant &Variant : Variants) {
     // Don't expand variants if the processor models don't intersect.
     // A zero processor index means any processor.
-    SmallVectorImpl<unsigned> &ProcIndices = TransVec[TransIdx].ProcIndices;
-    if (ProcIndices[0] && Variant.ProcIdx) {
-      unsigned Cnt = std::count(ProcIndices.begin(), ProcIndices.end(),
-                                Variant.ProcIdx);
-      if (!Cnt)
-        continue;
-      if (Cnt > 1) {
-        const CodeGenProcModel &PM =
-          *(SchedModels.procModelBegin() + Variant.ProcIdx);
-        PrintFatalError(Variant.VarOrSeqDef->getLoc(),
-                        "Multiple variants defined for processor " +
-                        PM.ModelName +
-                        " Ensure only one SchedAlias exists per RW.");
-      }
-    }
     if (Variant.VarOrSeqDef->isSubClassOf("SchedVar")) {
       Record *PredDef = Variant.VarOrSeqDef->getValueAsDef("Predicate");
       if (mutuallyExclusive(PredDef, AllPreds, TransVec[TransIdx].PredTerm))
         continue;
     }
 
     if (IntersectingVariants.empty()) {
       // The first variant builds on the existing transition.

 // Push the Reads/Writes selected by this variant onto the PredTransition
 // specified by VInfo.
 void PredTransitions::
 pushVariant(const TransVariant &VInfo, bool IsRead) {
   PredTransition &Trans = TransVec[VInfo.TransVecIdx];
 
   // If this operand transition is reached through a processor-specific alias,
   // then the whole transition is specific to this processor.
-  if (VInfo.ProcIdx != 0)
-    Trans.ProcIndices.assign(1, VInfo.ProcIdx);
-
   IdxVec SelectedRWs;
   if (VInfo.VarOrSeqDef->isSubClassOf("SchedVar")) {
     Record *PredDef = VInfo.VarOrSeqDef->getValueAsDef("Predicate");
     Trans.PredTerm.emplace_back(IsRead, VInfo.RWIdx,PredDef);
     RecVec SelectedDefs = VInfo.VarOrSeqDef->getValueAsListOfDefs("Selected");
     SchedModels.findRWs(SelectedDefs, SelectedRWs, IsRead);
   }
   else {

 // predicates should result in linear growth in the total number variants.
 //
 // This is one step in a breadth-first search of nested variants.
 bool PredTransitions::substituteVariants(const PredTransition &Trans) {
   // Build up a set of partial results starting at the back of
   // PredTransitions. Remember the first new transition.
   unsigned StartIdx = TransVec.size();
   bool Subst = false;
-  TransVec.emplace_back(Trans.PredTerm, Trans.ProcIndices);
+  assert(Trans.ProcIndex != 0);
+  TransVec.emplace_back(Trans.PredTerm, Trans.ProcIndex);
 
-  assert(!llvm::count(Trans.ProcIndices, 0));
   // Visit each original write sequence.
   for (SmallVectorImpl<SmallVector<unsigned,4>>::const_iterator
          WSI = Trans.WriteSequences.begin(), WSE = Trans.WriteSequences.end();
        WSI != WSE; ++WSI) {
     // Push a new (empty) write sequence onto all partial Transitions.
     for (std::vector<PredTransition>::iterator I =
            TransVec.begin() + StartIdx, E = TransVec.end(); I != E; ++I) {
       I->WriteSequences.emplace_back();

 static void dumpTransition(const CodeGenSchedModels &SchedModels,
                            const CodeGenSchedClass &FromSC,
                            const CodeGenSchedTransition &SCTrans,
                            const RecVec &Preds) {
   LLVM_DEBUG(dbgs() << "Adding transition from " << FromSC.Name << "("
                     << FromSC.Index << ") to "
                     << SchedModels.getSchedClass(SCTrans.ToClassIdx).Name << "("
                     << SCTrans.ToClassIdx << ") on pred term: (";
-             dumpRecVec(Preds); dbgs() << ") on processor indices: (";
-             dumpIdxVec(SCTrans.ProcIndices); dbgs() << ")\n");
+             dumpRecVec(Preds);
+             dbgs() << ") on processor (" << SCTrans.ProcIndex << ")\n");
 }
 // Create a new SchedClass for each variant found by inferFromRW. Pass
 static void inferFromTransitions(ArrayRef<PredTransition> LastTransitions,
                                  unsigned FromClassIdx,
                                  CodeGenSchedModels &SchedModels) {
   // For each PredTransition, create a new CodeGenSchedTransition, which usually
   // requires creating a new SchedClass.
   for (ArrayRef<PredTransition>::iterator
          I = LastTransitions.begin(), E = LastTransitions.end(); I != E; ++I) {
     // Variant expansion (substituteVariants) may create unconditional
     // transitions. We don't need to build sched classes for them.
     if (I->PredTerm.empty())
       continue;
     IdxVec OperWritesVariant, OperReadsVariant;
     addSequences(SchedModels, I->WriteSequences, OperWritesVariant, false);
     addSequences(SchedModels, I->ReadSequences, OperReadsVariant, true);
     CodeGenSchedTransition SCTrans;
 
     // Transition should not contain processor indices already assigned to
     // InstRWs in this scheduling class.
     const CodeGenSchedClass &FromSC = SchedModels.getSchedClass(FromClassIdx);
-    llvm::copy_if(I->ProcIndices, std::back_inserter(SCTrans.ProcIndices),
-                  [&FromSC](unsigned PIdx) {
-                    return !FromSC.InstRWProcIndices.count(PIdx);
-                  });
-    if (SCTrans.ProcIndices.empty())
+    if (FromSC.InstRWProcIndices.count(I->ProcIndex))
       continue;
+    SCTrans.ProcIndex = I->ProcIndex;
     SCTrans.ToClassIdx =
         SchedModels.addSchedClass(/*ItinClassDef=*/nullptr, OperWritesVariant,
-                                  OperReadsVariant, I->ProcIndices);
+                                  OperReadsVariant, I->ProcIndex);
 
     // The final PredTerm is unique set of predicates guarding the transition.
     RecVec Preds;
     transform(I->PredTerm, std::back_inserter(Preds),
               [](const PredCheck &P) {
                 return P.Predicate;
               });
     Preds.erase(std::unique(Preds.begin(), Preds.end()), Preds.end());

 
 static std::vector<PredTransition>
 makePerProcessorTransitions(const PredTransition &Trans,
                             ArrayRef<unsigned> ProcIndices) {
   std::vector<PredTransition> PerCpuTransVec;
   for (unsigned ProcId : ProcIndices) {
     assert(ProcId != 0);
     PerCpuTransVec.push_back(Trans);
-    PerCpuTransVec.back().ProcIndices.assign(1, ProcId);
+    PerCpuTransVec.back().ProcIndex = ProcId;
   }
   return PerCpuTransVec;
 }
 
 // Create new SchedClasses for the given ReadWrite list. If any of the
 // ReadWrites refers to a SchedVariant, create a new SchedClass for each variant
 // of the ReadWrite list, following Aliases if necessary.
 void CodeGenSchedModels::inferFromRW(ArrayRef<unsigned> OperWrites,
                                      ArrayRef<unsigned> OperReads,
                                      unsigned FromClassIdx,
                                      ArrayRef<unsigned> ProcIndices) {
   LLVM_DEBUG(dbgs() << "INFER RW proc("; dumpIdxVec(ProcIndices);
              dbgs() << ") ");
   // Create a seed transition with an empty PredTerm and the expanded sequences
   // of SchedWrites for the current SchedClass.
   std::vector<PredTransition> LastTransitions;
   LastTransitions.emplace_back();
-  LastTransitions.back().ProcIndices.append(ProcIndices.begin(),
-                                            ProcIndices.end());
 
   for (unsigned WriteIdx : OperWrites) {
     IdxVec WriteSeq;
     expandRWSequence(WriteIdx, WriteSeq, /*IsRead=*/false);
     LastTransitions[0].WriteSequences.emplace_back();
     SmallVectorImpl<unsigned> &Seq = LastTransitions[0].WriteSequences.back();
     Seq.append(WriteSeq.begin(), WriteSeq.end());
     LLVM_DEBUG(dbgs() << "("; dumpIdxVec(Seq); dbgs() << ") ");
if (i < N-1) {
       dbgs() << '\n';
       dbgs().indent(10);
     }
   }
   dbgs() << "\n  ProcIdx: "; dumpIdxVec(ProcIndices);
   if (!Transitions.empty()) {
     dbgs() << "\n Transitions for Proc ";
     for (const CodeGenSchedTransition &Transition : Transitions) {
-      dumpIdxVec(Transition.ProcIndices);
+      dbgs() << Transition.ProcIndex << ", ";
     }
   }
   dbgs() << '\n';
 }
 
 void PredTransitions::dump() const {
   dbgs() << "Expanded Variants:\n";
   for (std::vector<PredTransition>::const_iterator

llvm/utils/TableGen/SubtargetEmitter.cpp

for (const CodeGenSchedClass &SC : SchedModels.schedClasses()) {
     SCDesc.WriteProcResIdx = 0;
     SCDesc.WriteLatencyIdx = 0;
     SCDesc.ReadAdvanceIdx = 0;
 
     // A Variant SchedClass has no resources of its own.
     bool HasVariants = false;
     for (const CodeGenSchedTransition &CGT :
            make_range(SC.Transitions.begin(), SC.Transitions.end())) {
-      if (CGT.ProcIndices[0] == 0 ||
-          is_contained(CGT.ProcIndices, ProcModel.Index)) {
+      if (CGT.ProcIndex == ProcModel.Index) {
         HasVariants = true;
         break;
       }
     }
     if (HasVariants) {
       SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps;
       continue;
     }

 
 static void collectProcessorIndices(const CodeGenSchedClass &SC,
                                     IdxVec &ProcIndices) {
   // A variant scheduling class may define transitions for multiple
   // processors.  This function identifies wich processors are associated with
   // transition rules specified by variant class `SC`.
   for (const CodeGenSchedTransition &T : SC.Transitions) {
     IdxVec PI;
-    std::set_union(T.ProcIndices.begin(), T.ProcIndices.end(),
-                   ProcIndices.begin(), ProcIndices.end(),
-                   std::back_inserter(PI));
+    std::set_union(&T.ProcIndex, &T.ProcIndex + 1, ProcIndices.begin(),
+                   ProcIndices.end(), std::back_inserter(PI));
     ProcIndices.swap(PI);
   }
 }
 
 static bool isAlwaysTrue(const CodeGenSchedTransition &T) {
   return llvm::all_of(T.PredTerm,
                       [](const Record *R) { return isTruePredicate(R); });
 }
for (unsigned PI : ProcIndices) {
                    : "if (SchedModel->getProcessorID() == ");
         OS << PI << ") ";
         OS << "{ // " << (SchedModels.procModelBegin() + PI)->ModelName << '\n';
       }
 
       // Now emit transitions associated with processor PI.
       const CodeGenSchedTransition *FinalT = nullptr;
       for (const CodeGenSchedTransition &T : SC.Transitions) {
-        if (PI != 0 && !count(T.ProcIndices, PI))
+        if (PI != 0 && T.ProcIndex != PI)
           continue;
 
         // Emit only transitions based on MCSchedPredicate, if it's the case.
         // At least the transition specified by NoSchedPred is emitted,
         // which becomes the default transition for those variants otherwise
         // not based on MCSchedPredicate.
         // FIXME: preferably, llvm-mca should instead assume a reasonable
         // default when a variant transition is not based on MCSchedPredicate