Update cpsr register in BLX instruction emulation

[tberghammer]

Summary

Update cpsr register in BLX instruction emulation

Write the new cpsr value into the cpsr register if the BL or the BLX
instruction change the instruction set on arm.

[clayborg]

Nice catch. Looks good.

source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp

if (ConditionPassed(opcode))
             uint32_t J1 = Bit32(opcode, 13);
             uint32_t J2 = Bit32(opcode, 11);
             uint32_t imm11 = Bits32(opcode, 10, 0);
             uint32_t I1 = !(J1 ^ S);
             uint32_t I2 = !(J2 ^ S);
             uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
             imm32 = llvm::SignExtend32<25>(imm25);
             target = pc + imm32;
+            SelectInstrSet (eModeThumb);
             context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
             if (InITBlock() && !LastInITBlock())
                 return false;
             break;
             }
         case eEncodingT2:
             {
             lr = pc | 1u; // return address
             uint32_t S = Bit32(opcode, 26);
             uint32_t imm10H = Bits32(opcode, 25, 16);
             uint32_t J1 = Bit32(opcode, 13);
             uint32_t J2 = Bit32(opcode, 11);
             uint32_t imm10L = Bits32(opcode, 10, 1);
             uint32_t I1 = !(J1 ^ S);
             uint32_t I2 = !(J2 ^ S);
             uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10H << 12) | (imm10L << 2);
             imm32 = llvm::SignExtend32<25>(imm25);
             target = Align(pc, 4) + imm32;
+            SelectInstrSet (eModeARM);
             context.SetISAAndImmediateSigned (eModeARM, 4 + imm32);
             if (InITBlock() && !LastInITBlock())
                 return false;
             break;
             }
         case eEncodingA1:
             lr = pc - 4; // return address
             imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
             target = Align(pc, 4) + imm32;
+            SelectInstrSet (eModeARM);
             context.SetISAAndImmediateSigned (eModeARM, 8 + imm32);
             break;
         case eEncodingA2:
             lr = pc - 4; // return address
             imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 | Bits32(opcode, 24, 24) << 1);
             target = pc + imm32;
+            SelectInstrSet (eModeThumb);
             context.SetISAAndImmediateSigned (eModeThumb, 8 + imm32);
             break;
         default:
             return false;
         }
         if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
             return false;
         if (!BranchWritePC(context, target))
             return false;
+        if (m_opcode_cpsr != m_new_inst_cpsr)
+            if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr))
+                return false;
     }
     return true;
 }
 
 // Branch with Link and Exchange (register) calls a subroutine at an address and
 // instruction set specified by a register.
 // BLX (register)
 bool