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Differential D7581

[mips] Avoid redundant sign extension of the result of binary bitwise instructions.
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Authored by vkalintiris on Feb 12 2015, 3:07 AM.

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dsanders
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rGc491657a9d2e: Merging r229675: --------------------------------------------------------------…
rG611cb70b83d8: [mips] Avoid redundant sign extension of the result of binary bitwise…
rL229675: [mips] Avoid redundant sign extension of the result of binary bitwise…

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vkalintiris updated this revision to Diff 19815.Feb 12 2015, 3:07 AM
vkalintiris retitled this revision from to [mips] Avoid redundant sign extension of the result of binary bitwise instructions..
vkalintiris updated this object.
vkalintiris edited the test plan for this revision. (Show Details)
vkalintiris added a reviewer: dsanders.
vkalintiris added a subscriber: Unknown Object (MLST).
dsanders accepted this revision.Feb 18 2015, 6:27 AM
dsanders edited edge metadata.

LGTM with a comment nit.

lib/Target/Mips/Mips64InstrInfo.td
489

Nit: Capitalize first letter and add full-stop

This revision is now accepted and ready to land.Feb 18 2015, 6:27 AM
Closed by commit rL229675: [mips] Avoid redundant sign extension of the result of binary bitwise… (authored by vkalintiris). · Explain WhyFeb 18 2015, 6:59 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
8 lines
test/
CodeGen/
Mips/
llvm-ir/
5 lines
6 lines
5 lines

Diff 19815

lib/Target/Mips/Mips64InstrInfo.td

Show First 20 Lines • Show All 480 Lines • ▼ Show 20 Lines
// truncate // truncate
def : MipsPat<(trunc (assertsext GPR64:$src)), def : MipsPat<(trunc (assertsext GPR64:$src)),
(EXTRACT_SUBREG GPR64:$src, sub_32)>; (EXTRACT_SUBREG GPR64:$src, sub_32)>;
def : MipsPat<(trunc (assertzext GPR64:$src)), def : MipsPat<(trunc (assertzext GPR64:$src)),
(EXTRACT_SUBREG GPR64:$src, sub_32)>; (EXTRACT_SUBREG GPR64:$src, sub_32)>;
def : MipsPat<(i32 (trunc GPR64:$src)), def : MipsPat<(i32 (trunc GPR64:$src)),
(SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>; (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
// bypass trunc nodes for bitwise ops
dsandersUnsubmitted
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Nit: Capitalize first letter and add full-stop

dsanders: Nit: Capitalize first letter and add full-stop
def : MipsPat<(i32 (trunc (and GPR64:$lhs, GPR64:$rhs))),
(EXTRACT_SUBREG (AND64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
def : MipsPat<(i32 (trunc (or GPR64:$lhs, GPR64:$rhs))),
(EXTRACT_SUBREG (OR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))),
(EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>;
// 32-to-64-bit extension // 32-to-64-bit extension
def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>; def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>; def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>; def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
// Sign extend in register // Sign extend in register
def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
(SLL64_64 GPR64:$src)>; (SLL64_64 GPR64:$src)>;
▲ Show 20 Lines • Show All 102 Lines • Show Last 20 Lines

test/CodeGen/Mips/llvm-ir/and.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines; ALL-LABEL: and_i16:
%r = and i16 %a, %b %r = and i16 %a, %b
ret i16 %r ret i16 %r
} }
define signext i32 @and_i32(i32 signext %a, i32 signext %b) { define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
entry: entry:
; ALL-LABEL: and_i32: ; ALL-LABEL: and_i32:
; GP32: and $2, $4, $5 ; ALL: and $2, $4, $5
; GP64: and $[[T0:[0-9]+]], $4, $5
; GP64: sll $2, $[[T0]], 0
%r = and i32 %a, %b %r = and i32 %a, %b
ret i32 %r ret i32 %r
} }
define signext i64 @and_i64(i64 signext %a, i64 signext %b) { define signext i64 @and_i64(i64 signext %a, i64 signext %b) {
entry: entry:
; ALL-LABEL: and_i64: ; ALL-LABEL: and_i64:
Show All 29 Lines

test/CodeGen/Mips/llvm-ir/or.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines; ALL-LABEL: or_i16:
%r = or i16 %a, %b %r = or i16 %a, %b
ret i16 %r ret i16 %r
} }
define signext i32 @or_i32(i32 signext %a, i32 signext %b) { define signext i32 @or_i32(i32 signext %a, i32 signext %b) {
entry: entry:
; ALL-LABEL: or_i32: ; ALL-LABEL: or_i32:
; GP32: or $2, $4, $5 ; ALL: or $2, $4, $5
; GP64: or $[[T0:[0-9]+]], $4, $5
; FIXME: The sll instruction below is redundant.
; GP64: sll $2, $[[T0]], 0
%r = or i32 %a, %b %r = or i32 %a, %b
ret i32 %r ret i32 %r
} }
define signext i64 @or_i64(i64 signext %a, i64 signext %b) { define signext i64 @or_i64(i64 signext %a, i64 signext %b) {
entry: entry:
; ALL-LABEL: or_i64: ; ALL-LABEL: or_i64:
Show All 29 Lines

test/CodeGen/Mips/llvm-ir/xor.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines; ALL-LABEL: xor_i16:
%r = xor i16 %a, %b %r = xor i16 %a, %b
ret i16 %r ret i16 %r
} }
define signext i32 @xor_i32(i32 signext %a, i32 signext %b) { define signext i32 @xor_i32(i32 signext %a, i32 signext %b) {
entry: entry:
; ALL-LABEL: xor_i32: ; ALL-LABEL: xor_i32:
; GP32: xor $2, $4, $5 ; ALL: xor $2, $4, $5
; GP64: xor $[[T0:[0-9]+]], $4, $5
; GP64: sll $2, $[[T0]], 0
%r = xor i32 %a, %b %r = xor i32 %a, %b
ret i32 %r ret i32 %r
} }
define signext i64 @xor_i64(i64 signext %a, i64 signext %b) { define signext i64 @xor_i64(i64 signext %a, i64 signext %b) {
entry: entry:
; ALL-LABEL: xor_i64: ; ALL-LABEL: xor_i64:
Show All 29 Lines