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Differential D75124

[AVR] Fix private label prefix
ClosedPublic

Authored by aykevl on Feb 25 2020, 8:34 AM.

Details

Reviewers
dylanmckay
Commits
rG6afc3de42f8f: [AVR] Fix private label prefix
Summary

This is a small pet peeve from me. This change makes sure the AVR backend uses the correct private label prefix (.L) so that private labels are hidden in avr-objdump.

Example code:

define i8 @foo(i1 %cond) {    
  br i1 %cond, label %then, label %else    
then:    
  ret i8 3    
else:    
  ret i8 5    
}

When compiling this:

llc -march=avr -filetype=obj -o test.o test.ll

and then dumping it:

avr-objdump -d test.o

You would previously get an ugly temporary label:

00000000 <foo>:    
   0:        81 70       andi       r24, 0x01    ; 1    
   2:        80 30       cpi        r24, 0x00    ; 0    
   4:        f9 f3       breq       .-2          ; 0x4 <foo+0x4>    
   6:        83 e0       ldi        r24, 0x03    ; 3    
   8:        08 95       ret    

0000000a <LBB0_2>:    
   a:        85 e0       ldi        r24, 0x05    ; 5    
   c:        08 95       ret

This patch fixes that, the output is now:

00000000 <foo>:    
   0:        81 70       andi       r24, 0x01    ; 1    
   2:        80 30       cpi        r24, 0x00    ; 0    
   4:        01 f0       breq       .+0          ; 0x6 <foo+0x6>    
   6:        83 e0       ldi        r24, 0x03    ; 3    
   8:        08 95       ret    
   a:        85 e0       ldi        r24, 0x05    ; 5    
   c:        08 95       ret

Note that as you can see the breq operand is different. However it is still the same after linking:

4:        11 f0       breq       .+4

Diff Detail

Event Timeline

aykevl created this revision.Feb 25 2020, 8:34 AM
Herald added subscribers: Jim, hiraditya. · View Herald TranscriptFeb 25 2020, 8:34 AM
dylanmckay accepted this revision.Feb 25 2020, 9:11 PM

Consistency, nice.

This revision is now accepted and ready to land.Feb 25 2020, 9:11 PM
Closed by commit rG6afc3de42f8f: [AVR] Fix private label prefix (authored by aykevl). · Explain WhyFeb 26 2020, 11:33 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AVR/
MCTargetDesc/
1 line
test/
CodeGen/
AVR/
8 lines
10 lines
4 lines
2 lines
integration/
4 lines
16 lines
2 lines
2 lines

Diff 246802

llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp

Show All 15 Lines
namespace llvm { namespace llvm {
AVRMCAsmInfo::AVRMCAsmInfo(const Triple &TT, const MCTargetOptions &Options) { AVRMCAsmInfo::AVRMCAsmInfo(const Triple &TT, const MCTargetOptions &Options) {
CodePointerSize = 2; CodePointerSize = 2;
CalleeSaveStackSlotSize = 2; CalleeSaveStackSlotSize = 2;
CommentString = ";"; CommentString = ";";
PrivateGlobalPrefix = ".L"; PrivateGlobalPrefix = ".L";
PrivateLabelPrefix = ".L";
UsesELFSectionDirectiveForBSS = true; UsesELFSectionDirectiveForBSS = true;
UseIntegratedAssembler = true; UseIntegratedAssembler = true;
SupportsDebugInformation = true; SupportsDebugInformation = true;
} }
} // end of namespace llvm } // end of namespace llvm

llvm/test/CodeGen/AVR/branch-relaxation-long.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr | FileCheck %s
; CHECK-LABEL: relax_to_jmp: ; CHECK-LABEL: relax_to_jmp:
; CHECK: cpi r{{[0-9]+}}, 0 ; CHECK: cpi r{{[0-9]+}}, 0
; CHECK: brne [[BB1:LBB[0-9]+_[0-9]+]] ; CHECK: brne [[BB1:.LBB[0-9]+_[0-9]+]]
; CHECK: jmp [[BB2:LBB[0-9]+_[0-9]+]] ; CHECK: jmp [[BB2:.LBB[0-9]+_[0-9]+]]
; CHECK: [[BB1]]: ; CHECK: [[BB1]]:
; CHECK: nop ; CHECK: nop
; CHECK: [[BB2]]: ; CHECK: [[BB2]]:
define i8 @relax_to_jmp(i1 %a) { define i8 @relax_to_jmp(i1 %a) {
entry-block: entry-block:
br i1 %a, label %hello, label %finished br i1 %a, label %hello, label %finished
hello: hello:
; with >4 kB of instructions (2050 NOPs), this requires a long jump (jmp), ; with >4 kB of instructions (2050 NOPs), this requires a long jump (jmp),
▲ Show 20 Lines • Show All 2,049 Lines • ▼ Show 20 Lines
call void asm sideeffect "nop", ""() call void asm sideeffect "nop", ""()
call void asm sideeffect "nop", ""() call void asm sideeffect "nop", ""()
br label %finished br label %finished
finished: finished:
ret i8 3 ret i8 3
} }
; CHECK-LABEL: relax_to_jmp_backwards: ; CHECK-LABEL: relax_to_jmp_backwards:
; CHECK: [[BB1:LBB[0-9]+_[0-9]+]] ; CHECK: [[BB1:.LBB[0-9]+_[0-9]+]]
; CHECK: nop ; CHECK: nop
; CHECK: cpi r{{[0-9]+}}, 0 ; CHECK: cpi r{{[0-9]+}}, 0
; CHECK: breq [[BB2:LBB[0-9]+_[0-9]+]] ; CHECK: breq [[BB2:.LBB[0-9]+_[0-9]+]]
; CHECK: jmp [[BB1]] ; CHECK: jmp [[BB1]]
; CHECK: [[BB2]]: ; CHECK: [[BB2]]:
define i8 @relax_to_jmp_backwards(i1 %a) { define i8 @relax_to_jmp_backwards(i1 %a) {
entry-block: entry-block:
br label %hello br label %hello
hello: hello:
; with >4 kB of instructions (2050 NOPs), this requires a long jump (jmp), ; with >4 kB of instructions (2050 NOPs), this requires a long jump (jmp),
; versus a relative one (rjmp). ; versus a relative one (rjmp).
▲ Show 20 Lines • Show All 2,054 Lines • Show Last 20 Lines

llvm/test/CodeGen/AVR/branch-relaxation.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr | FileCheck %s
; CHECK-LABEL: relax_breq ; CHECK-LABEL: relax_breq
; CHECK: cpi r{{[0-9]+}}, 0 ; CHECK: cpi r{{[0-9]+}}, 0
; CHECK: brne LBB0_1 ; CHECK: brne .LBB0_1
; CHECK: rjmp LBB0_2 ; CHECK: rjmp .LBB0_2
; LBB0_1: ; .LBB0_1:
define i8 @relax_breq(i1 %a) { define i8 @relax_breq(i1 %a) {
entry-block: entry-block:
br i1 %a, label %hello, label %finished br i1 %a, label %hello, label %finished
hello: hello:
call void asm sideeffect "nop", ""() call void asm sideeffect "nop", ""()
call void asm sideeffect "nop", ""() call void asm sideeffect "nop", ""()
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lineshello:
call void asm sideeffect "nop", ""() call void asm sideeffect "nop", ""()
br label %finished br label %finished
finished: finished:
ret i8 3 ret i8 3
} }
; CHECK-LABEL: no_relax_breq ; CHECK-LABEL: no_relax_breq
; CHECK: cpi r{{[0-9]+}}, 0 ; CHECK: cpi r{{[0-9]+}}, 0
; CHECK: breq [[END_BB:LBB[0-9]+_[0-9]+]] ; CHECK: breq [[END_BB:.LBB[0-9]+_[0-9]+]]
; CHECK: nop ; CHECK: nop
; ... ; ...
; LBB0_1: ; .LBB0_1:
define i8 @no_relax_breq(i1 %a) { define i8 @no_relax_breq(i1 %a) {
entry-block: entry-block:
br i1 %a, label %hello, label %finished br i1 %a, label %hello, label %finished
hello: hello:
; There are not enough NOPs to require relaxation. ; There are not enough NOPs to require relaxation.
call void asm sideeffect "nop", ""() call void asm sideeffect "nop", ""()
call void asm sideeffect "nop", ""() call void asm sideeffect "nop", ""()
Show All 14 Lines

llvm/test/CodeGen/AVR/ctlz.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr | FileCheck %s
define i8 @count_leading_zeros(i8) unnamed_addr { define i8 @count_leading_zeros(i8) unnamed_addr {
entry-block: entry-block:
%1 = tail call i8 @llvm.ctlz.i8(i8 %0) %1 = tail call i8 @llvm.ctlz.i8(i8 %0)
ret i8 %1 ret i8 %1
} }
declare i8 @llvm.ctlz.i8(i8) declare i8 @llvm.ctlz.i8(i8)
; CHECK-LABEL: count_leading_zeros: ; CHECK-LABEL: count_leading_zeros:
; CHECK: cpi [[RESULT:r[0-9]+]], 0 ; CHECK: cpi [[RESULT:r[0-9]+]], 0
; CHECK: brne LBB0_1 ; CHECK: brne .LBB0_1
; CHECK: rjmp LBB0_2 ; CHECK: rjmp .LBB0_2
; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]] ; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
; CHECK: lsr {{.*}}[[SCRATCH]] ; CHECK: lsr {{.*}}[[SCRATCH]]
; CHECK: or {{.*}}[[SCRATCH]], {{.*}}[[RESULT]] ; CHECK: or {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
; CHECK: mov {{.*}}[[RESULT]], {{.*}}[[SCRATCH]] ; CHECK: mov {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
; CHECK: lsr {{.*}}[[RESULT]] ; CHECK: lsr {{.*}}[[RESULT]]
; CHECK: lsr {{.*}}[[RESULT]] ; CHECK: lsr {{.*}}[[RESULT]]
; CHECK: or {{.*}}[[RESULT]], {{.*}}[[SCRATCH]] ; CHECK: or {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]] ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
Show All 27 Lines

llvm/test/CodeGen/AVR/cttz.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr | FileCheck %s
define i8 @count_trailing_zeros(i8) unnamed_addr { define i8 @count_trailing_zeros(i8) unnamed_addr {
entry-block: entry-block:
%1 = tail call i8 @llvm.cttz.i8(i8 %0) %1 = tail call i8 @llvm.cttz.i8(i8 %0)
ret i8 %1 ret i8 %1
} }
declare i8 @llvm.cttz.i8(i8) declare i8 @llvm.cttz.i8(i8)
; CHECK-LABEL: count_trailing_zeros: ; CHECK-LABEL: count_trailing_zeros:
; CHECK: cpi [[RESULT:r[0-9]+]], 0 ; CHECK: cpi [[RESULT:r[0-9]+]], 0
; CHECK: breq [[END_BB:LBB[0-9]+_[0-9]+]] ; CHECK: breq [[END_BB:.LBB[0-9]+_[0-9]+]]
; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]] ; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
; CHECK: dec {{.*}}[[SCRATCH]] ; CHECK: dec {{.*}}[[SCRATCH]]
; CHECK: com {{.*}}[[RESULT]] ; CHECK: com {{.*}}[[RESULT]]
; CHECK: and {{.*}}[[RESULT]], {{.*}}[[SCRATCH]] ; CHECK: and {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]] ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
; CHECK: lsr {{.*}}[[SCRATCH]] ; CHECK: lsr {{.*}}[[SCRATCH]]
; CHECK: andi {{.*}}[[SCRATCH]], 85 ; CHECK: andi {{.*}}[[SCRATCH]], 85
; CHECK: sub {{.*}}[[RESULT]], {{.*}}[[SCRATCH]] ; CHECK: sub {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
Show All 19 Lines

llvm/test/CodeGen/AVR/integration/blink.ll

Show First 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
define i16 @main() { define i16 @main() {
entry: entry:
; CHECK: call setup_ddr ; CHECK: call setup_ddr
call void @setup_ddr() call void @setup_ddr()
br label %while.body br label %while.body
; CHECK-LABEL: LBB3_1 ; CHECK-LABEL: .LBB3_1
while.body: while.body:
; CHECK: call turn_on ; CHECK: call turn_on
call void @turn_on() call void @turn_on()
; CHECK-NEXT: call turn_off ; CHECK-NEXT: call turn_off
call void @turn_off() call void @turn_off()
; CHECK-NEXT: rjmp LBB3_1 ; CHECK-NEXT: rjmp .LBB3_1
br label %while.body br label %while.body
} }

llvm/test/CodeGen/AVR/rot.ll

; RUN: llc < %s -march=avr | FileCheck %s ; RUN: llc < %s -march=avr | FileCheck %s
; Bit rotation tests. ; Bit rotation tests.
; CHECK-LABEL: rol8: ; CHECK-LABEL: rol8:
define i8 @rol8(i8 %val, i8 %amt) { define i8 @rol8(i8 %val, i8 %amt) {
; CHECK: andi r22, 7 ; CHECK: andi r22, 7
; CHECK-NEXT: cpi r22, 0 ; CHECK-NEXT: cpi r22, 0
; CHECK-NEXT: breq LBB0_2 ; CHECK-NEXT: breq .LBB0_2
; CHECK-NEXT: LBB0_1: ; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: lsl r24 ; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1 ; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: subi r22, 1 ; CHECK-NEXT: subi r22, 1
; CHECK-NEXT: brne LBB0_1 ; CHECK-NEXT: brne .LBB0_1
; CHECK-NEXT:LBB0_2: ; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mod = urem i8 %amt, 8 %mod = urem i8 %amt, 8
%inv = sub i8 8, %mod %inv = sub i8 8, %mod
%parta = shl i8 %val, %mod %parta = shl i8 %val, %mod
%partb = lshr i8 %val, %inv %partb = lshr i8 %val, %inv
%rotl = or i8 %parta, %partb %rotl = or i8 %parta, %partb
ret i8 %rotl ret i8 %rotl
} }
; CHECK-LABEL: ror8: ; CHECK-LABEL: ror8:
define i8 @ror8(i8 %val, i8 %amt) { define i8 @ror8(i8 %val, i8 %amt) {
; CHECK: andi r22, 7 ; CHECK: andi r22, 7
; CHECK-NEXT: cpi r22, 0 ; CHECK-NEXT: cpi r22, 0
; CHECK-NEXT: breq LBB1_2 ; CHECK-NEXT: breq .LBB1_2
; CHECK-NEXT: LBB1_1: ; CHECK-NEXT: .LBB1_1:
; CHECK-NEXT: lsr r24 ; CHECK-NEXT: lsr r24
; CHECK-NEXT: ldi r0, 0 ; CHECK-NEXT: ldi r0, 0
; CHECK-NEXT: ror r0 ; CHECK-NEXT: ror r0
; CHECK-NEXT: or r24, r0 ; CHECK-NEXT: or r24, r0
; CHECK-NEXT: subi r22, 1 ; CHECK-NEXT: subi r22, 1
; CHECK-NEXT: brne LBB1_1 ; CHECK-NEXT: brne .LBB1_1
; CHECK-NEXT:LBB1_2: ; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mod = urem i8 %amt, 8 %mod = urem i8 %amt, 8
%inv = sub i8 8, %mod %inv = sub i8 8, %mod
%parta = lshr i8 %val, %mod %parta = lshr i8 %val, %mod
%partb = shl i8 %val, %inv %partb = shl i8 %val, %inv
%rotr = or i8 %parta, %partb %rotr = or i8 %parta, %partb
ret i8 %rotr ret i8 %rotr
} }

llvm/test/CodeGen/AVR/smul-with-overflow.ll

Show All 16 Lines
; CHECK: asr {{.*}}[[LOW]] ; CHECK: asr {{.*}}[[LOW]]
; CHECK: asr {{.*}}[[LOW]] ; CHECK: asr {{.*}}[[LOW]]
; CHECK: asr {{.*}}[[LOW]] ; CHECK: asr {{.*}}[[LOW]]
; CHECK: asr {{.*}}[[LOW]] ; CHECK: asr {{.*}}[[LOW]]
; CHECK: asr {{.*}}[[LOW]] ; CHECK: asr {{.*}}[[LOW]]
; CHECK: asr {{.*}}[[LOW]] ; CHECK: asr {{.*}}[[LOW]]
; CHECK: ldi [[RET:r[0-9]+]], 1 ; CHECK: ldi [[RET:r[0-9]+]], 1
; CHECK: cp {{.*}}[[HIGH]], {{.*}}[[LOW]] ; CHECK: cp {{.*}}[[HIGH]], {{.*}}[[LOW]]
; CHECK: brne [[LABEL:LBB[_0-9]+]] ; CHECK: brne [[LABEL:.LBB[_0-9]+]]
; CHECK: ldi {{.*}}[[RET]], 0 ; CHECK: ldi {{.*}}[[RET]], 0
; CHECK: {{.*}}[[LABEL]] ; CHECK: {{.*}}[[LABEL]]
; CHECK: ret ; CHECK: ret
} }
declare { i8, i1 } @llvm.smul.with.overflow.i8(i8, i8) declare { i8, i1 } @llvm.smul.with.overflow.i8(i8, i8)

llvm/test/CodeGen/AVR/umul-with-overflow.ll

; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s ; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
define i1 @unsigned_multiplication_did_overflow(i8, i8) unnamed_addr { define i1 @unsigned_multiplication_did_overflow(i8, i8) unnamed_addr {
; CHECK-LABEL: unsigned_multiplication_did_overflow: ; CHECK-LABEL: unsigned_multiplication_did_overflow:
entry-block: entry-block:
%2 = tail call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %0, i8 %1) %2 = tail call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %0, i8 %1)
%3 = extractvalue { i8, i1 } %2, 1 %3 = extractvalue { i8, i1 } %2, 1
ret i1 %3 ret i1 %3
; Multiply, return if the high byte is zero ; Multiply, return if the high byte is zero
; ;
; CHECK: mul r{{[0-9]+}}, r{{[0-9]+}} ; CHECK: mul r{{[0-9]+}}, r{{[0-9]+}}
; CHECK: mov [[HIGH:r[0-9]+]], r1 ; CHECK: mov [[HIGH:r[0-9]+]], r1
; CHECK: ldi [[RET:r[0-9]+]], 1 ; CHECK: ldi [[RET:r[0-9]+]], 1
; CHECK: cpi {{.*}}[[HIGH]], 0 ; CHECK: cpi {{.*}}[[HIGH]], 0
; CHECK: brne [[LABEL:LBB[_0-9]+]] ; CHECK: brne [[LABEL:.LBB[_0-9]+]]
; CHECK: ldi {{.*}}[[RET]], 0 ; CHECK: ldi {{.*}}[[RET]], 0
; CHECK: {{.*}}[[LABEL]] ; CHECK: {{.*}}[[LABEL]]
; CHECK: ret ; CHECK: ret
} }
declare { i8, i1 } @llvm.umul.with.overflow.i8(i8, i8) declare { i8, i1 } @llvm.umul.with.overflow.i8(i8, i8)