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[AVR] Use correct register class for mul instructions
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Authored by aykevl on Feb 8 2020, 9:34 AM.

Details

Summary

A number of multiplication instructions (muls, mulsu, fmul, fmuls, fmulsu) had the wrong register class for an operand. This resulted in the wrong register being used for the instruction.

Example:

target datalayout = "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8"
target triple = "avr-atmel-none"

define i16 @sliceAppend(i16, i16, i16, i16, i16, i16) addrspace(1) {
  %d = mul i16 %0, %5
  ret i16 %d
}

The first instruction would be muls r24, r31 before this patch. The r31 should have been r15 if you look at the intermediate forms during instruction selection / register allocation, but the generated instruction uses r31. After this patch, an extra movw is inserted to get %5 in range for muls.

To make sure this bug is fixed everywhere, I checked all instructions and found that most multiplication instructions suffered from this bug, which I have fixed with this patch. No other instructions appear to be affected.

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Event Timeline

aykevl created this revision.Feb 8 2020, 9:34 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 8 2020, 9:34 AM
Herald added subscribers: Jim, hiraditya. · View Herald Transcript
dylanmckay accepted this revision.Feb 24 2020, 2:30 AM

As always, appreciate the patch @aykevl, I've checked the instruction set manual and you are 100% right.

This revision is now accepted and ready to land.Feb 24 2020, 2:30 AM
This revision was automatically updated to reflect the committed changes.