[ARM] Enable vector extload combine for legal types.

[ab]

Summary

This patch enables forming vector extloads (introduced in D6904) for ARM.
It only does so for legal types, and when we can't fold the extension in a wide/long form of the user instruction.

Enabling it for larger types isn't as good an idea on ARM as it is on X86, because:

1. we pretend that extloads are legal, but end up generating vld+vmov, and
2. we have instructions like vld {dN, dM}, which can't be generated when we "manually expand" extloads to vld+vmov.

For instance, for a 16i16 -> 16i64 sextload, we generate something like:
...
vld1.64 {d16, d17}, [r2:128]
vmovl.s16 q9, d16
vmovl.s16 q8, d17
...

Whereas with the combine enabled for illegal types, we would generate:
...
vld1.32 {d18[0]}, [r1:32]
...
vmovl.s16 q9, d18
...

For legal types, the combine doesn't fire that often: in the integration tests only in a big endian testcase, where it removes a pointless AND.

[jmolloy]

Hi Ahmed,

This looks fine to me. I'd prefer a testcase that shows this optimization triggering, but perhaps that is not possible.

Cheers,

James

[ab]

r231396, thanks for the review!

I tried harder to tickle the combine, but I couldn't write a more
explicit test :/

-Ahmed

llvm/trunk/lib/Target/ARM/ARMISelLowering.h

EVT getOptimalMemOpType(uint64_t Size,
                             unsigned DstAlign, unsigned SrcAlign,
                             bool IsMemset, bool ZeroMemset,
                             bool MemcpyStrSrc,
                             MachineFunction &MF) const override;
 
     using TargetLowering::isZExtFree;
     bool isZExtFree(SDValue Val, EVT VT2) const override;
 
+    bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
+
     bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
 
 
     /// isLegalAddressingMode - Return true if the addressing mode represented
     /// by AM is legal for this target, for a load/store of the specified type.
     bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
     bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
 

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
   case MVT::i16:
     // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
     return true;
   }
 
   return false;
 }
 
+bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
+  EVT VT = ExtVal.getValueType();
+
+  if (!isTypeLegal(VT))
+    return false;
+
+  // Don't create a loadext if we can fold the extension into a wide/long
+  // instruction.
+  // If there's more than one user instruction, the loadext is desirable no
+  // matter what.  There can be two uses by the same instruction.
+  if (ExtVal->use_empty() ||
+      !ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode()))
+    return true;
+
+  SDNode *U = *ExtVal->use_begin();
+  if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
+       U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHL))
+    return false;
+
+  return true;
+}
+
 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
   if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
     return false;
 
   if (!isTypeLegal(EVT::getEVT(Ty1)))
     return false;
 
   assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");

llvm/trunk/test/CodeGen/ARM/big-endian-neon-extend.ll

 ; RUN: llc < %s -mtriple armeb-eabi -mattr v7,neon -o - | FileCheck %s
 
 define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ) {
 ; CHECK-LABEL: vector_ext_2i8_to_2i64:
 ; CHECK:      vld1.16   {[[REG:d[0-9]+]][0]}, [r0:16]
-; CHECK-NEXT: vmov.i64  [[MASK:q[0-9]+]], #0xff
-; CHECK-NEXT: vrev64.32 [[MASK]], [[MASK]]
 ; CHECK-NEXT: vrev16.8  [[REG]], [[REG]]
 ; CHECK-NEXT: vmovl.u8  [[QREG:q[0-9]+]], [[REG]]
 ; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
 ; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
-; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
-; CHECK-NEXT: vand      [[QREG]], [[QREG]], [[MASK]]
-; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
 ; CHECK-NEXT: vst1.64   {[[REG]], {{d[0-9]+}}}, [r1]
 ; CHECK-NEXT: bx        lr
   %1 = load <2 x i8>, <2 x i8>* %loadaddr
   %2 = zext <2 x i8> %1 to <2 x i64>
   store <2 x i64> %2, <2 x i64>* %storeaddr
   ret void
 }
 
 define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeaddr ) {
 ; CHECK-LABEL: vector_ext_2i16_to_2i64:
 ; CHECK:      vld1.32   {[[REG:d[0-9]+]][0]}, [r0:32]
-; CHECK-NEXT: vmov.i64  [[MASK:q[0-9]+]], #0xffff
-; CHECK-NEXT: vrev64.32 [[MASK]], [[MASK]]
 ; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
 ; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
 ; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
-; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
-; CHECK-NEXT: vand      [[QREG]], [[QREG]], [[MASK]]
-; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
 ; CHECK-NEXT: vst1.64   {[[REG]], {{d[0-9]+}}}, [r1]
 ; CHECK-NEXT: bx        lr
   %1 = load <2 x i16>, <2 x i16>* %loadaddr
   %2 = zext <2 x i16> %1 to <2 x i64>
   store <2 x i64> %2, <2 x i64>* %storeaddr
   ret void
 }
 

llvm/trunk/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll

 ; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
 
 ; CHECK-LABEL: f:
 define float @f(<4 x i16>* nocapture %in) {
-  ; CHECK: vldr
+  ; CHECK: vld1
   ; CHECK: vmovl.u16
   ; CHECK-NOT: vand
   %1 = load <4 x i16>, <4 x i16>* %in
   ; CHECK: vcvt.f32.u32
   %2 = uitofp <4 x i16> %1 to <4 x float>
   %3 = extractelement <4 x float> %2, i32 0
   %4 = extractelement <4 x float> %2, i32 1
   %5 = extractelement <4 x float> %2, i32 2

llvm/trunk/test/CodeGen/ARM/vector-extend-narrow.ll

 ; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
 
 ; CHECK-LABEL: f:
 define float @f(<4 x i16>* nocapture %in) {
-  ; CHECK: vldr
+  ; CHECK: vld1
   ; CHECK: vmovl.u16
   %1 = load <4 x i16>, <4 x i16>* %in
   ; CHECK: vcvt.f32.u32
   %2 = uitofp <4 x i16> %1 to <4 x float>
   %3 = extractelement <4 x float> %2, i32 0
   %4 = extractelement <4 x float> %2, i32 1
   %5 = extractelement <4 x float> %2, i32 2