Preserve early clobber flag when using named registers in inline assembly.

[dsanders]

Summary

Named registers with the constraint "=&r" currently lose the early clobber flag
and turn into "=r" when converted to LLVM-IR. This patch correctly passes it on.

[atanasyan]

LGTM

[dsanders]

I found some regressions when I re-tested before committing. It was possible for the early-clobber flag to appear twice.

I'm about to upload a corrected version.

[dsanders]

Fixed crashes caused by the accidental introduction of constraints like '=&&r'.
Correct test/CodeGen/arm-asm-variable.c to expect the early-clobber flag.

[atanasyan]

How did the compiler produce constraints like =&&r in the initial version of this patch? Might the CodeGenFunction::EmitAsmStmt be called twice?

[dsanders]

The argument to SimplifyConstraint() would omit the first character (always '=') and the function preserved the '&', giving '&r' as the result of SimplifyConstraint(). Each of the paths of AddVariableConstraints() that returned Constraint unmodified would also preserve the '&'. Then the code I added would prepend '=&' for the early clobber case giving '=&&r'.

[atanasyan]

Thanks for the clarification.

LGTM

lib/CodeGen/CGStmt.cpp

 }
 
 /// AddVariableConstraints - Look at AsmExpr and if it is a variable declared
 /// as using a particular register add that as a constraint that will be used
 /// in this asm stmt.
 static std::string
 AddVariableConstraints(const std::string &Constraint, const Expr &AsmExpr,
                        const TargetInfo &Target, CodeGenModule &CGM,
-                       const AsmStmt &Stmt) {
+                       const AsmStmt &Stmt, const bool EarlyClobber) {
   const DeclRefExpr *AsmDeclRef = dyn_cast<DeclRefExpr>(&AsmExpr);
   if (!AsmDeclRef)
     return Constraint;
   const ValueDecl &Value = *AsmDeclRef->getDecl();
   const VarDecl *Variable = dyn_cast<VarDecl>(&Value);
   if (!Variable)
     return Constraint;
   if (Variable->getStorageClass() != SC_Register)
     return Constraint;
   AsmLabelAttr *Attr = Variable->getAttr<AsmLabelAttr>();
   if (!Attr)
     return Constraint;
   StringRef Register = Attr->getLabel();
   assert(Target.isValidGCCRegisterName(Register));
   // We're using validateOutputConstraint here because we only care if
   // this is a register constraint.
   TargetInfo::ConstraintInfo Info(Constraint, "");
   if (Target.validateOutputConstraint(Info) &&
       !Info.allowsRegister()) {
     CGM.ErrorUnsupported(&Stmt, "__asm__");
     return Constraint;
   }
   // Canonicalize the register here before returning it.
   Register = Target.getNormalizedGCCRegisterName(Register);
-  return "{" + Register.str() + "}";
+  return (EarlyClobber ? "&{" : "{") + Register.str() + "}";
 }
 
 llvm::Value*
 CodeGenFunction::EmitAsmInputLValue(const TargetInfo::ConstraintInfo &Info,
                                     LValue InputValue, QualType InputType,
                                     std::string &ConstraintStr,
                                     SourceLocation Loc) {
   llvm::Value *Arg;
for (unsigned i = 0, e = S.getNumOutputs(); i != e; i++) {
     std::string OutputConstraint(S.getOutputConstraint(i));
     OutputConstraint = SimplifyConstraint(OutputConstraint.c_str() + 1,
                                           getTarget());
 
     const Expr *OutExpr = S.getOutputExpr(i);
     OutExpr = OutExpr->IgnoreParenNoopCasts(getContext());
 
     OutputConstraint = AddVariableConstraints(OutputConstraint, *OutExpr,
-                                              getTarget(), CGM, S);
+                                              getTarget(), CGM, S,
+                                              Info.earlyClobber());
 
     LValue Dest = EmitLValue(OutExpr);
     if (!Constraints.empty())
       Constraints += ',';
 
     // If this is a register output, then make the inline asm return it
     // by-value.  If this is a memory result, return the value by-reference.
     if (!Info.allowsMemory() && hasScalarEvaluationKind(OutExpr->getType())) {
for (unsigned i = 0, e = S.getNumInputs(); i != e; i++) {
     // Simplify the input constraint.
     std::string InputConstraint(S.getInputConstraint(i));
     InputConstraint = SimplifyConstraint(InputConstraint.c_str(), getTarget(),
                                          &OutputConstraintInfos);
 
     InputConstraint =
       AddVariableConstraints(InputConstraint,
                             *InputExpr->IgnoreParenNoopCasts(getContext()),
-                            getTarget(), CGM, S);
+                            getTarget(), CGM, S, Info.earlyClobber());
 
     llvm::Value *Arg = EmitAsmInput(Info, InputExpr, Constraints);
 
     // If this input argument is tied to a larger output result, extend the
     // input to be the same size as the output.  The LLVM backend wants to see
     // the input and output of a matching constraint be the same size.  Note
     // that GCC does not define what the top bits are here.  We use zext because
     // that is usually cheaper, but LLVM IR should really get an anyext someday.

test/CodeGen/arm-asm-variable.c

int64_t foo(int64_t v, volatile int64_t *p)
   int64_t r;
   uint32_t t;
 
   __asm__ __volatile__(             \
            "ldrexd%[_rl], %[_rh], [%[_p]]"      \
            : [_rl] "=&r" (rl), [_rh] "=&r" (rh)    \
            : [_p] "p" (p) : "memory");
 
-  // CHECK: call { i32, i32 } asm sideeffect "ldrexd$0, $1, [$2]", "={r1},={r2},r,~{memory}"(i64*
+  // CHECK: call { i32, i32 } asm sideeffect "ldrexd$0, $1, [$2]", "=&{r1},=&{r2},r,~{memory}"(i64*
 
   return r;
 }
 
 // Make sure we translate register names properly.
 void bar (void) {
   register unsigned int rn asm("r14");
   register unsigned int d asm("r2");
 
   // CHECK: call i32 asm sideeffect "sub $1, $1, #32", "={r2},{lr}"
   asm volatile ("sub %1, %1, #32" : "=r"(d) : "r"(rn));
 }

test/CodeGen/asm-reg-var-local.c

 // RUN: %clang_cc1 %s -triple x86_64-apple-darwin -emit-llvm -o - | FileCheck %s
 // Exercise various use cases for local asm "register variables".
 
 int foo() {
+// CHECK-LABEL: define i32 @foo()
 // CHECK: [[A:%[a-zA-Z0-9]+]] = alloca i32
 
   register int a asm("rsi")=5;
 // CHECK: store i32 5, i32* [[A]]
 
   asm volatile("; %0 This asm defines rsi" : "=r"(a));
 // CHECK: [[Z:%[a-zA-Z0-9]+]] = call i32 asm sideeffect "; $0 This asm defines rsi", "={rsi},~{dirflag},~{fpsr},~{flags}"()
 // CHECK: store i32 [[Z]], i32* [[A]]
 
   a = 42;
 // CHECK:  store i32 42, i32* [[A]]
 
   asm volatile("; %0 This asm uses rsi" : : "r"(a));
 // CHECK:  [[TMP:%[a-zA-Z0-9]+]] = load i32* [[A]]
 // CHECK:  call void asm sideeffect "; $0 This asm uses rsi", "{rsi},~{dirflag},~{fpsr},~{flags}"(i32 [[TMP]])
 
   return a;
 // CHECK:  [[TMP1:%[a-zA-Z0-9]+]] = load i32* [[A]]
 // CHECK:  ret i32 [[TMP1]]
 }
+
+int earlyclobber() {
+// CHECK-LABEL: define i32 @earlyclobber()
+// CHECK: [[A:%[a-zA-Z0-9]+]] = alloca i32
+
+  register int a asm("rsi")=5;
+// CHECK: store i32 5, i32* [[A]]
+
+  asm volatile("; %0 This asm defines rsi" : "=&r"(a));
+// CHECK: [[Z:%[a-zA-Z0-9]+]] = call i32 asm sideeffect "; $0 This asm defines rsi", "=&{rsi},~{dirflag},~{fpsr},~{flags}"()
+// CHECK: store i32 [[Z]], i32* [[A]]
+
+  a = 42;
+// CHECK:  store i32 42, i32* [[A]]
+
+  asm volatile("; %0 This asm uses rsi" : : "r"(a));
+// CHECK:  [[TMP:%[a-zA-Z0-9]+]] = load i32* [[A]]
+// CHECK:  call void asm sideeffect "; $0 This asm uses rsi", "{rsi},~{dirflag},~{fpsr},~{flags}"(i32 [[TMP]])
+
+  return a;
+// CHECK:  [[TMP1:%[a-zA-Z0-9]+]] = load i32* [[A]]
+// CHECK:  ret i32 [[TMP1]]
+}