[mips] [IAS] Add missing constraints and improve testing for the .module directive.

[tomatabacu]

Summary

None of the .set directives can be used before the .module directives. The .set mips0/pop/push were not triggering this constraint.
Also added testing for all the other implemented directives which are supposed to trigger this constraint.

[tomatabacu]

Moved tests to mips-abi-bad.s.
Added test for .set pop.

[tomatabacu]

Add more comprehensive test.

[tomatabacu]

Ping.

[dsanders]

The code change looks correct to me but I think there's a problem with the test.

test/MC/Mips/module-set-directives-bad.s

1–134 ↗

(On Diff #19469)

I don't think this test covers what you think it does. It looks like it's only testing that '.set mips0' triggers the errors. All the subsequent errors will appear as a consequence of '.set mips0' regardless of whether those directives do the right thing.

I think we need a special directive for testing purposes to reset the flag in between each test (.llvm_internal_reallow_module_directive?). That way we can reset the flag between each subtest. The alternative is to have a separate file (and associated process overhead) for each subtest which seems unreasonable.

[tomatabacu]

Added internal directive for resetting .module, as suggested in the review.
Added missing call to forbidModuleDirective in emitDirectiveSetFp.
Removed CHECKs for .set macro/nomacro because they don't get emitted at the moment.
Changed the name of the test file to a more appropriate one.

[dsanders]

LGTM with the CHECK-NOT's added

test/MC/Mips/module-directive-bad.s

9 ↗

(On Diff #21091)

You ought to have a CHECK-NOT on each of these to ensure the error doesn't trigger.

[tomatabacu]

Added CHECK-NOTs.

lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

 void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
                                    unsigned ReturnReg) {}
 void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
 void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
 }
 void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
   forbidModuleDirective();
 }
-void MipsTargetStreamer::emitDirectiveSetMips0() {}
+void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
-void MipsTargetStreamer::emitDirectiveSetPop() {}
-void MipsTargetStreamer::emitDirectiveSetPush() {}
+void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
+void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
 void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
 void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
                                               const MCSymbol &Sym, bool IsReg) {
 }
 void MipsTargetStreamer::emitDirectiveModuleOddSPReg(bool Enabled,
                                                      bool IsO32ABI) {
OS << "\t.frame\t$"
      << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
 }
 
 void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
   OS << "\t.set arch=" << Arch << "\n";
   MipsTargetStreamer::emitDirectiveSetArch(Arch);
 }
 
-void MipsTargetAsmStreamer::emitDirectiveSetMips0() { OS << "\t.set\tmips0\n"; }
+void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
+  OS << "\t.set\tmips0\n";
+  MipsTargetStreamer::emitDirectiveSetMips0();
+}
 
 void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
   OS << "\t.set\tmips1\n";
   MipsTargetStreamer::emitDirectiveSetMips1();
 }
 
 void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
   OS << "\t.set\tmips2\n";
void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
   MipsTargetStreamer::emitDirectiveSetDsp();
 }
 
 void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
   OS << "\t.set\tnodsp\n";
   MipsTargetStreamer::emitDirectiveSetNoDsp();
 }
 
-void MipsTargetAsmStreamer::emitDirectiveSetPop() { OS << "\t.set\tpop\n"; }
+void MipsTargetAsmStreamer::emitDirectiveSetPop() {
+  OS << "\t.set\tpop\n";
+  MipsTargetStreamer::emitDirectiveSetPop();
+}
 
-void MipsTargetAsmStreamer::emitDirectiveSetPush() { OS << "\t.set\tpush\n"; }
+void MipsTargetAsmStreamer::emitDirectiveSetPush() {
+ OS << "\t.set\tpush\n";
+ MipsTargetStreamer::emitDirectiveSetPush();
+}
 
 // Print a 32 bit hex number with all numbers.
 static void printHex32(unsigned Value, raw_ostream &OS) {
   OS << "0x";
   for (int i = 7; i >= 0; i--)
     OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
 }
 

test/MC/Mips/mips-abi-bad.s

 # CHECK-NEXT: .module 34
 # CHECK-NEXT:         ^
 
     .set mips16
     .module fp=32
 # CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
 # CHECK-NEXT: .module fp=32
 # CHECK-NEXT:         ^
+
+    .set mips0
+    .module fp=32
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set push
+    .module fp=32
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code
+
+    .set pop
+    .module fp=32
+# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code