Add saving and restoring of r30 to the prologue and epilogue, respectively

[jhibbits]

Summary

The PIC additions didn't update the prologue and epilogue code to save and restore r30 (PIC base register). This does that.

[hfinkel]

LGTM.

lib/Target/PowerPC/PPCFrameLowering.cpp

647 ↗

(On Diff #17884)

This line is too long.

1013 ↗

(On Diff #17884)

Same here.

[hfinkel]

test/CodeGen/PowerPC/ppc32-pic.ll

18 ↗

(On Diff #17884)

Also, you should probably make this line

; SMALL-BSS-DAG:         lwz {{[0-9]+}}, 0([[VREG]])
; SMALL-BSS-DAG:         lwz 30, -8(1)

because post-ra scheduling could legally interchange them.

[jhibbits]

Address Hal's comments

[hfinkel]

LGTM.

llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp

void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
 
   if (HasFP)
     // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
     BuildMI(MBB, MBBI, dl, StoreInst)
       .addReg(FPReg)
       .addImm(FPOffset)
       .addReg(SPReg);
 
+  if (isPIC && !isDarwinABI && !isPPC64 &&
+      MF.getInfo<PPCFunctionInfo>()->usesPICBase())
+    // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
+    BuildMI(MBB, MBBI, dl, StoreInst)
+      .addReg(PPC::R30)
+      .addImm(-8U)
+      .addReg(SPReg);
+
   if (HasBP)
     // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
     BuildMI(MBB, MBBI, dl, StoreInst)
       .addReg(BPReg)
       .addImm(BPOffset)
       .addReg(SPReg);
 
   if (MustSaveLR)
BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
       .addImm(8)
       .addReg(SPReg);
 
   if (HasFP)
     BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
       .addImm(FPOffset)
       .addReg(SPReg);
 
+  if (isPIC && !isDarwinABI && !isPPC64 &&
+      MF.getInfo<PPCFunctionInfo>()->usesPICBase())
+    // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
+    BuildMI(MBB, MBBI, dl, LoadInst)
+      .addReg(PPC::R30)
+      .addImm(-8U)
+      .addReg(SPReg);
+
   if (HasBP)
     BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
       .addImm(BPOffset)
       .addReg(SPReg);
 
   if (!MustSaveCRs.empty()) // will only occur for PPC64
     for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
       BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])

llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

if (!GlobalBaseReg) {
     DebugLoc dl;
 
     if (PPCLowering->getPointerTy() == MVT::i32) {
       if (PPCSubTarget->isTargetELF()) {
         GlobalBaseReg = PPC::R30;
         if (M->getPICLevel() == PICLevel::Small) {
           BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));
           BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
+          MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
         } else {
           BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
           BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
           unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
           BuildMI(FirstMBB, MBBI, dl,
                   TII.get(PPC::UpdateGBR)).addReg(GlobalBaseReg)
                   .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
           MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);

llvm/trunk/test/CodeGen/PowerPC/ppc32-pic-large.ll

 ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck -check-prefix=LARGE-BSS %s
 @bar = common global i32 0, align 4
 
 define i32 @foo() {
 entry:
   %0 = load i32* @bar, align 4
   ret i32 %0
 }
 
 !llvm.module.flags = !{!0}
 !0 = !{i32 1, !"PIC Level", i32 2}
 ; LARGE-BSS:       [[POFF:\.L[0-9]+\$poff]]:
 ; LARGE-BSS-NEXT:    .long .LTOC-[[PB:\.L[0-9]+\$pb]]
 ; LARGE-BSS-NEXT:  foo:
+; LARGE-BSS:         stw 30, -8(1)
 ; LARGE-BSS:         bl [[PB]]
 ; LARGE-BSS-NEXT:  [[PB]]:
 ; LARGE-BSS:         mflr 30
 ; LARGE-BSS:         lwz [[REG:[0-9]+]], [[POFF]]-[[PB]](30)
 ; LARGE-BSS-NEXT:    add 30, [[REG]], 30
 ; LARGE-BSS:         lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30)
-; LARGE-BSS:         lwz {{[0-9]+}}, 0([[VREG]])
+; LARGE-BSS-DAG:     lwz {{[0-9]+}}, 0([[VREG]])
+; LARGE-BSS-DAG:     lwz 30, -8(1)
 ; LARGE-BSS:       [[VREF]]:
 ; LARGE-BSS-NEXT:    .long bar

llvm/trunk/test/CodeGen/PowerPC/ppc32-pic.ll

 ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck -check-prefix=SMALL-BSS %s
 @bar = common global i32 0, align 4
 
 define i32 @foo() {
 entry:
   %0 = load i32* @bar, align 4
   ret i32 %0
 }
 
 !llvm.module.flags = !{!0}
 !0 = !{i32 1, !"PIC Level", i32 1}
 ; SMALL-BSS-LABEL:foo:
+; SMALL-BSS:         stw 30, -8(1)
 ; SMALL-BSS:         bl _GLOBAL_OFFSET_TABLE_@local-4
 ; SMALL-BSS:         mflr 30
 ; SMALL-BSS:         lwz [[VREG:[0-9]+]], bar@GOT(30)
-; SMALL-BSS:         lwz {{[0-9]+}}, 0([[VREG]])
+; SMALL-BSS-DAG:     lwz {{[0-9]+}}, 0([[VREG]])
+; SMALL-BSS-DAG:     lwz 30, -8(1)