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[ARM] Fix BXJ is undefined in AArch32.

Authored by rengolin on Jan 5 2015, 7:06 AM.



BXJ was incorrectly said to be unsupported in ARMv8-A. It is not supported in
the A64 instruction set, but it is supported in the T32 and A32 instruction
sets, because it's listed as an instruction in the ARM ARM section F7.1.28.

This was found by MCHammer.

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chatur01 retitled this revision from to [ARM] Fix BXJ is undefined in AArch32..
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olista01 requested changes to this revision.Jan 12 2015, 2:34 AM
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Up to v7[AR], BXJ is unpredictable for r13 and r15, but v8A makes it well-defined for r13. This should be accepted for v8A thumb:

$ llvm-mc -triple thumbv8a--none-eabi -assemble <<< "bxj r13"
<stdin>:1:1: error: instruction requires: arm-mode
bxj r13
This revision now requires changes to proceed.Jan 12 2015, 2:34 AM
chatur01 updated this revision to Diff 23151.EditedApr 2 2015, 8:05 AM
chatur01 edited edge metadata.

Track the change from SP being unpredictable as an operand to BXJ in architecture pre v8-A to now being predictable.

I wasn't sure how best to approach the unpredictability change in v8-A.
The approach here was to change rGPR to GPRnopc, so that BXJ could now match SP as an operand, and then to add a new validate case in ARMAsmParser that check what the target architecture revision is. If it's v8-A, then BXJ SP is fine, otherwise give a diagnostic.
Is there a better way in tblgen to overload the register set an instruction can take based on the target architecture?

rengolin accepted this revision.Apr 15 2015, 5:39 AM
rengolin added a reviewer: rengolin.

LGTM, Thanks!

Thanks Renato! Landed r235024.

rengolin accepted this revision.May 8 2015, 4:38 AM
rengolin commandeered this revision.May 8 2015, 5:04 AM
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rengolin edited reviewers, added: chatur01; removed: rengolin.
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