[Mips][Disassembler][R6] Disassembler crashes on load/store from coprocessor 2 instructions for r6

[vmedic]

Summary

When disassembler meets load/store from coprocessor 2 instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions.

[dsanders]

LGTM

[vmedic]

Committed revision 226652.

lib/Target/Mips/Disassembler/MipsDisassembler.cpp

 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
                                uint64_t Address,
                                const void *Decoder);
-
 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
                                uint64_t Address,
                                const void *Decoder);

                                uint64_t Address,
                                const void *Decoder);
 
+static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
+                               uint64_t Address,
+                               const void *Decoder);
+
 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
                                        unsigned Insn,
                                        uint64_t Address,

   return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
+                               unsigned Insn,
+                               uint64_t Address,
+                               const void *Decoder) {
+  int Offset = SignExtend32<11>(Insn & 0x07ff);
+  unsigned Reg = fieldFromInstruction(Insn, 16, 5);
+  unsigned Base = fieldFromInstruction(Insn, 11, 5);
+
+  Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
+  Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
+
+  Inst.addOperand(MCOperand::CreateReg(Reg));
+  Inst.addOperand(MCOperand::CreateReg(Base));
+  Inst.addOperand(MCOperand::CreateImm(Offset));
+
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
                                        unsigned Insn,
                                        uint64_t Address,

lib/Target/Mips/Mips32r6InstrInfo.td

   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
   list<dag> Pattern = [];
   bit mayLoad = 1;
+  string DecoderMethod = "DecodeFMemCop2R6";
 }
 
 class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>;

   string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
   list<dag> Pattern = [];
   bit mayStore = 1;
+  string DecoderMethod = "DecodeFMemCop2R6";
 }
 
 class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>;

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt

 0x33 0xfe 0x1d 0x02    # CHECK: tltu $16, $sp, 1016
 0x36 0x00 0xd1 0x00    # CHECK: tne $6, $17
 0x76 0xdd 0xe8 0x00    # CHECK: tne $7, $8, 885
+0x43 0x0d 0xc8 0x49    # CHECK: ldc2 $8, -701($1)
+0xb7 0x34 0x52 0x49    # CHECK: lwc2 $18, -841($6)
+0x75 0x92 0xf4 0x49    # CHECK: sdc2 $20, 629($18)
+0x30 0x81 0x79 0x49    # CHECK: swc2 $25, 304($16)

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt

 0x02 0x1d 0xfe 0x33    # CHECK: tltu $16, $sp, 1016
 0x00 0xd1 0x00 0x36    # CHECK: tne $6, $17
 0x00 0xe8 0xdd 0x76    # CHECK: tne $7, $8, 885
+0x49 0xc8 0x0d 0x43    # CHECK: ldc2 $8, -701($1)
+0x49 0x52 0x34 0xb7    # CHECK: lwc2 $18, -841($6)
+0x49 0xf4 0x92 0x75    # CHECK: sdc2 $20, 629($18)
+0x49 0x79 0x81 0x30    # CHECK: swc2 $25, 304($16)

test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt

 0x60 0xc0 0x00 0x40    # CHECK: bnec $6, $zero, 256
 0x60 0xa0 0x00 0x40    # CHECK: bnec $5, $zero, 256
 0x60 0xa6 0x00 0x40    # CHECK: bnec $5, $6, 256
 0xf8 0x05 0x01 0x00    # CHECK: jialc $5, 256
 0xd8 0x05 0x01 0x00    # CHECK: jic $5, 256
-0x49 0xc8 0x0d 0x43    # CHECK: ldc2 $8, -701($1)
-0x49 0x52 0x34 0xb7    # CHECK: lwc2 $18, -841($6)
-0x49 0xf4 0x92 0x75    # CHECK: sdc2 $20, 629($18)
-0x49 0x79 0x81 0x30    # CHECK: swc2 $25, 304($16)

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt

 0x33 0xfe 0x1d 0x02    # CHECK: tltu $16, $sp, 1016
 0x36 0x00 0xd1 0x00    # CHECK: tne $6, $17
 0x76 0xdd 0xe8 0x00    # CHECK: tne $7, $8, 885
+0x43 0x0d 0xc8 0x49    # CHECK: ldc2 $8, -701($1)
+0xb7 0x34 0x52 0x49    # CHECK: lwc2 $18, -841($6)
+0x75 0x92 0xf4 0x49    # CHECK: sdc2 $20, 629($18)
+0x30 0x81 0x79 0x49    # CHECK: swc2 $25, 304($16)

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt

 0x02 0x1d 0xfe 0x33    # CHECK: tltu $16, $sp, 1016
 0x00 0xd1 0x00 0x36    # CHECK: tne $6, $17
 0x00 0xe8 0xdd 0x76    # CHECK: tne $7, $8, 885
+0x49 0xc8 0x0d 0x43    # CHECK: ldc2 $8, -701($1)
+0x49 0x52 0x34 0xb7    # CHECK: lwc2 $18, -841($6)
+0x49 0xf4 0x92 0x75    # CHECK: sdc2 $20, 629($18)
+0x49 0x79 0x81 0x30    # CHECK: swc2 $25, 304($16)

test/MC/Disassembler/Mips/mips64r6/valid-xfail-mips64r6.txt

 0x60 0xc0 0x00 0x40    # CHECK: bnec $6, $zero, 256
 0x60 0xa0 0x00 0x40    # CHECK: bnec $5, $zero, 256
 0x60 0xa6 0x00 0x40    # CHECK: bnec $5, $6, 256
 0xf8 0x05 0x01 0x00    # CHECK: jialc $5, 256
 0xd8 0x05 0x01 0x00    # CHECK: jic $5, 256
-0x49 0xc8 0x0d 0x43    # CHECK: ldc2 $8, -701($1)
-0x49 0x52 0x34 0xb7    # CHECK: lwc2 $18, -841($6)
-0x49 0xf4 0x92 0x75    # CHECK: sdc2 $20, 629($18)
-0x49 0x79 0x81 0x30    # CHECK: swc2 $25, 304($16)
 0x64 0x58 0x46 0x9f    # CHECK: daddiu $24, $2, 18079
 0x66 0x73 0x69 0x3f    # CHECK: daddiu $19, $19, 26943
 0x65 0x6f 0xec 0x5f    # CHECK: daddiu $15, $11, -5025