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[Mips][Disassembler][R6] Disassembler crashes on cache/pref instructions for r6
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Authored by vmedic on Dec 30 2014, 4:55 AM.

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Summary

When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.

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Event Timeline

vmedic updated this revision to Diff 17715.Dec 30 2014, 4:55 AM
vmedic retitled this revision from to [Mips][Disassembler][R6] Disassembler crashes on cache/pref instructions for r6.
vmedic updated this object.
vmedic edited the test plan for this revision. (Show Details)
vmedic added reviewers: dsanders, sstankovic.
vmedic added a subscriber: Unknown Object (MLST).
dsanders accepted this revision.Jan 28 2015, 8:05 AM
dsanders edited edge metadata.

LGTM with a few nits

lib/Target/Mips/Disassembler/MipsDisassembler.cpp
256–258

Nit: Indentation

1120–1122

Nit: Indentation

1123

Nit: Just for consistency, we should probably use 'fieldFromInstruction(Insn, 7, 9)' instead of '(Insn & 0xff90) >> 7'

1127

The same opcode is used for MIPS64r6 too. We should pick GPR32/GPR64 according to the subtarget

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
144

Nit: Blank line at EOF

test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
144

Nit: Blank line at EOF

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
162

Nit: Blank line at EOF

test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
162

Nit: Blank line at EOF

This revision is now accepted and ready to land.Jan 28 2015, 8:05 AM
vmedic closed this revision.Jan 29 2015, 3:35 AM

Suggested changes applied. Committed revision 227430.