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[mips] Enable code generation for MIPS-III.
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Authored by vkalintiris on Dec 1 2014, 9:27 AM.

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Summary

This commit enables the MIPS-III target and adds support for code
generation of SELECT nodes. We have to use pseudo-instructions with
custom inserters for these nodes as MIPS-III CPUs do not have
conditional-move instructions.

Depends on D6212

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vkalintiris updated this revision to Diff 16772.Dec 1 2014, 9:27 AM
vkalintiris retitled this revision from to [mips] Enable code generation for MIPS-III..
vkalintiris updated this object.
vkalintiris edited the test plan for this revision. (Show Details)
vkalintiris added a reviewer: dsanders.
vkalintiris added a subscriber: Unknown Object (MLST).
dsanders accepted this revision.Dec 8 2014, 7:29 AM
dsanders edited edge metadata.

LGTM with a style nit and with the DecoderNamespace's removed (if they aren't really needed).

lib/Target/Mips/MipsCondMov.td
287–288

Style nit:

def PseudoSELECT_I64 : Select_Pseudo<GPR64Opnd> {
  let DecoderNamespace = "Mips64" in
}

is preferable if the let only applies to a single def. Similarly below.

One related question is: Is it necessary to set the DecoderNamespace? As far as I know it only affects the disassembler tables and pseudo's aren't included in those tables.

This revision is now accepted and ready to land.Dec 8 2014, 7:29 AM
This revision was automatically updated to reflect the committed changes.