[AVR] Fix incorrect source regclass of LDWRdPtr

[Jim]

Summary

LDWRdPtr would be expanded to ld+ldd. ldd only accepts the pointer register is Y or Z.
So the register class of pointer of LDWRdPtr should be PTRDISPREGS instead of PTRREGS.

[dylanmckay]

lib/Target/AVR/AVRInstrInfo.td

1163 ↗

(On Diff #200923)

Thanks for fixing this comment

lib/Target/AVR/AVRRegisterInfo.td

175 ↗

(On Diff #200923)

I can't tell why the removal of Y is needed.

LDWRdPtr expands to LDRdPtr and LDDRdPtrQ.

LDRdPtr accepts any pointer register (X, Y, or Z), and as you point out, LDDRdPtrQ only accepts DREGS_WITHOUT_Z_WORKAROUND: (AKA some GPRs and X, Y). The register constraints over the instruction pair is the intersection of the register classes for these sub instructions, which is the set of pointer registers { X, Y }

What are your thoughts?

[Jim]

lib/Target/AVR/AVRRegisterInfo.td

168 ↗

(On Diff #200923)

Since we change the register class of pointer for LDWRdPtr to the small one . We have the same issue like Z register.

175 ↗

(On Diff #200923)

LDRdPtr accepts X, Y or Z as pointer register, But LDDRdPtrQ only accepts Y or Z as pointer register.
I changed the pointer register of LDWRdPtr from {X, Y, Z} to {Y, Z}. Since their intersection of registers are Y or Z (Register class PTRDISPREGS). Y has more register pressure due to this change. So I removed Y from DREGS_WITHOUT_Z_WORKAROUND. In my experiment, if it is without the removal of Y, it has the same issue, ran out of registers, as Z.

test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir

1 ↗

(On Diff #200923)

The source register and pointer register of LDDWRdPtrQ will not be the same. So I deleted this test.

[dylanmckay]

lib/Target/AVR/AVRRegisterInfo.td

175 ↗

(On Diff #200923)

That makes sense, thanks

[dylanmckay]

Nice work, thanks for the patch @Jim

llvm/trunk/lib/Target/AVR/AVRInstrInfo.td

def LDRdPtr : FSTLD<0,
                       (ins LDSTPtrReg:$ptrreg),
                       "ld\t$reg, $ptrreg",
                       [(set GPR8:$reg, (load i16:$ptrreg))]>,
                 Requires<[HasSRAM]>;
 
   // LDW Rd+1:Rd, P
   //
   // Expands to:
-  // ld Rd,   P+
-  // ld Rd+1, P
+  // ld  Rd,   P
+  // ldd Rd+1, P+1
   let Constraints = "@earlyclobber $reg" in
   def LDWRdPtr : Pseudo<(outs DREGS:$reg),
-                        (ins PTRREGS:$ptrreg),
+                        (ins PTRDISPREGS:$ptrreg),
                         "ldw\t$reg, $ptrreg",
                         [(set i16:$reg, (load i16:$ptrreg))]>,
                  Requires<[HasSRAM]>;
 }
 
 // Indirect loads (with postincrement or predecrement).
 let mayLoad = 1,
 hasSideEffects = 0,
def LDDRdPtrQ : FSTDLDD<0,
                   Requires<[HasSRAM]>;
 
   // LDDW Rd+1:Rd, P+q
   //
   // Expands to:
   // ldd Rd,   P+q
   // ldd Rd+1, P+q+1
   let Constraints = "@earlyclobber $dst" in
-  def LDDWRdPtrQ : Pseudo<(outs DREGS_WITHOUT_Z_WORKAROUND:$dst),
+  def LDDWRdPtrQ : Pseudo<(outs DREGS_WITHOUT_YZ_WORKAROUND:$dst),
                           (ins memri:$memri),
                           "lddw\t$dst, $memri",
                           [(set i16:$dst, (load addr:$memri))]>,
                    Requires<[HasSRAM]>;
 
   // An identical pseudo instruction to LDDWRdPtrQ, expect restricted to the Y
   // register and without the @earlyclobber flag.
   //

llvm/trunk/lib/Target/AVR/AVRRegisterInfo.td

 //
 // This is used by instructions which cause high pointer register
 // contention which leads to an assertion in the register allocator.
 //
 // There is no technical reason why instructions that use this class
 // cannot use Z; it's simply a workaround a regalloc bug.
 //
 // More information can be found in PR39553.
-def DREGS_WITHOUT_Z_WORKAROUND : RegisterClass<"AVR", [i16], 8,
+def DREGS_WITHOUT_YZ_WORKAROUND : RegisterClass<"AVR", [i16], 8,
   (
     // Return value and arguments.
     add R25R24, R19R18, R21R20, R23R22,
     // Scratch registers.
     R27R26,
     // Callee saved registers.
-    R29R28, R17R16, R15R14, R13R12, R11R10,
+    R17R16, R15R14, R13R12, R11R10,
     R9R8, R7R6, R5R4, R3R2, R1R0
   )>;
 
 // 16-bit register class for immediate instructions.
 def DLDREGS : RegisterClass<"AVR", [i16], 8,
   (
     // Return value and arguments.
     add R25R24, R19R18, R21R20, R23R22,

llvm/trunk/test/CodeGen/AVR/load.ll

 ; RUN: llc -mattr=avr6,sram < %s -march=avr | FileCheck %s
 
 define i8 @load8(i8* %x) {
 ; CHECK-LABEL: load8:
 ; CHECK: ld r24, {{[XYZ]}}
   %1 = load i8, i8* %x
   ret i8 %1
 }
 
 define i16 @load16(i16* %x) {
 ; CHECK-LABEL: load16:
-; CHECK: ld r24,  [[PTR:[XYZ]]]
+; CHECK: ld r24,  [[PTR:[YZ]]]
 ; CHECK: ldd r25, [[PTR]]+1
   %1 = load i16, i16* %x
   ret i16 %1
 }
 
 define i8 @load8disp(i8* %x) {
 ; CHECK-LABEL: load8disp:
 ; CHECK: ldd r24, {{[YZ]}}+63

 ; CHECK: ldd r25, [[PTR]]+63
   %1 = getelementptr inbounds i16, i16* %x, i64 31
   %2 = load i16, i16* %1
   ret i16 %2
 }
 
 define i16 @load16nodisp(i16* %x) {
 ; CHECK-LABEL: load16nodisp:
-; CHECK: movw r26, r24
-; CHECK: subi r26, 192
-; CHECK: sbci r27, 255
-; CHECK: ld r24,  [[PTR:[XYZ]]]
+; CHECK: movw r30, r24
+; CHECK: subi r30, 192
+; CHECK: sbci r31, 255
+; CHECK: ld r24,  [[PTR:[YZ]]]
 ; CHECK: ldd r25, [[PTR]]+1
   %1 = getelementptr inbounds i16, i16* %x, i64 32
   %2 = load i16, i16* %1
   ret i16 %2
 }
 
 define i8 @load8postinc(i8* %x, i8 %y) {
 ; CHECK-LABEL: load8postinc:

llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir

-# RUN: llc -O0  %s -o - -march=avr | FileCheck %s
-
-# This test checks the expansion of the 16-bit 'LDDWRdPtrQ' pseudo instruction.
-#
-# This test ensures that the pseudo expander can correctly handle the case
-# where we are expanding a 16-bit LDD instruction where the source and
-# destination registers are the same.
-#
-# The instruction itself is earlyclobber and so ISel will never produce an
-# instruction like this, but the stack slot loading can and will.
-
---- |
-  target triple = "avr--"
-  define void @test_lddwrdptrq() {
-  entry:
-    ret void
-  }
-...
-
----
-name:            test_lddwrdptrq
-tracksRegLiveness: true
-body: |
-  bb.0.entry:
-
-    ; CHECK-LABEL: test_lddwrdptrq
-
-    ; CHECK:      ldd [[SCRATCH:r[0-9]+]], Y+10
-    ; CHECK-NEXT: push [[SCRATCH]]
-    ; CHECK-NEXT: ldd [[SCRATCH]], Y+11
-    ; CHECK-NEXT: mov r29, [[SCRATCH]]
-    ; CHECK-NEXT: pop r28
-
-    early-clobber $r29r28 = LDDWRdPtrQ undef $r29r28, 10
-...

llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir

 ---
 name:            test_lddwrdptrq
 tracksRegLiveness: true
 body: |
   bb.0.entry:
 
     ; CHECK-LABEL: test_lddwrdptrq
 
-    ; CHECK:      ldd     r28, Z+10
-    ; CHECK-NEXT: ldd     r29, Z+11
+    ; CHECK:      ldd     r24, Z+10
+    ; CHECK-NEXT: ldd     r25, Z+11
 
-    early-clobber $r29r28 = LDDWRdPtrQ undef $r31r30, 10
+    early-clobber $r25r24 = LDDWRdPtrQ undef $r31r30, 10
 ...