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Differential D62036

[SystemZ] Bugfix in SystemZTargetLowering::combineIntDIVREM()
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Authored by jonpa on May 16 2019, 2:53 PM.

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Summary

Make sure to not unroll a vector division/remainder (with a constant splat divisor) after type legalization, since the scalar type may then be illegal.

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jonpa created this revision.May 16 2019, 2:53 PM

Herald added a subscriber: dmgreen. · View Herald TranscriptMay 16 2019, 2:53 PM

(This patch is NFC on benchmarks).

LGTM, thanks!

This revision is now accepted and ready to land.May 16 2019, 4:50 PM

r360965

Revision Contents

Path

Size

lib/

Target/

SystemZ/

SystemZISelLowering.cpp

2 lines

test/

CodeGen/

SystemZ/

vec-rem.ll

13 lines

Diff 199910

lib/Target/SystemZ/SystemZISelLowering.cpp

This file is larger than 256 KB, so syntax highlighting is disabled by default.

Show First 20 Lines • Show All 5,835 Lines • ▼ Show 20 Lines	SDValue SystemZTargetLowering::combineIntDIVREM(
EVT VT = N->getValueType(0);		EVT VT = N->getValueType(0);
// In the case where the divisor is a vector of constants a cheaper		// In the case where the divisor is a vector of constants a cheaper
// sequence of instructions can replace the divide. BuildSDIV is called to		// sequence of instructions can replace the divide. BuildSDIV is called to
// do this during DAG combining, but it only succeeds when it can build a		// do this during DAG combining, but it only succeeds when it can build a
// multiplication node. The only option for SystemZ is ISD::SMUL_LOHI, and		// multiplication node. The only option for SystemZ is ISD::SMUL_LOHI, and
// since it is not Legal but Custom it can only happen before		// since it is not Legal but Custom it can only happen before
// legalization. Therefore we must scalarize this early before Combine		// legalization. Therefore we must scalarize this early before Combine
// 1. For widened vectors, this is already the result of type legalization.		// 1. For widened vectors, this is already the result of type legalization.
if (VT.isVector() && isTypeLegal(VT) &&		if (DCI.Level == BeforeLegalizeTypes && VT.isVector() && isTypeLegal(VT) &&
DAG.isConstantIntBuildVectorOrConstantInt(N->getOperand(1)))		DAG.isConstantIntBuildVectorOrConstantInt(N->getOperand(1)))
return DAG.UnrollVectorOp(N);		return DAG.UnrollVectorOp(N);
return SDValue();		return SDValue();
}		}

SDValue SystemZTargetLowering::unwrapAddress(SDValue N) const {		SDValue SystemZTargetLowering::unwrapAddress(SDValue N) const {
if (N->getOpcode() == SystemZISD::PCREL_WRAPPER)		if (N->getOpcode() == SystemZISD::PCREL_WRAPPER)
return N->getOperand(0);		return N->getOperand(0);
▲ Show 20 Lines • Show All 1,632 Lines • Show Last 20 Lines

test/CodeGen/SystemZ/vec-rem.ll

This file was added.

				; Verify that we do not create illegal scalar urems after type legalization.
				;
				; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13

				define <16 x i8> @main(i16 %arg) {
				bb:
				%tmp6 = insertelement <16 x i16> undef, i16 %arg, i32 0
				%tmp7 = shufflevector <16 x i16> %tmp6, <16 x i16> undef, <16 x i32> zeroinitializer
				%tmp8 = insertelement <16 x i8> <i8 undef, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, i8 undef, i32 0
				%tmp11 = urem <16 x i16> %tmp7, <i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265, i16 29265>
				%tmp12 = trunc <16 x i16> %tmp11 to <16 x i8>
				ret <16 x i8> %tmp12
				}