[AggressiveAntiDepBreaker] Handle predicate operands better

[jmolloy]

Summary

[note: I tried hard to make a test for this. I thought Hexagon might be a good target, but alas it has a control register that aliases all of its predicate registers, which makes AggressiveAntiDependencyBreaker bail out even after this patch]

For targets that have a predicate register class, we want to be able to break antidepedencies in that regclass. This patch enhances AggressiveAntiDepBreaker to understand that even though an instruction is predicated, it may still unconditionally read the predicate operand and so can be handled by the existing logic.

To do this, a target hook is created. No test as no targets have this functionality.

[hfinkel]

Why don't we always do this? Isn't assuming that the register is always read the conservatively-correct thing to do here?

include/llvm/CodeGen/TargetInstrInfo.h

1253

We'd need to document whether Reg must already occur as a read register in one of the MI's MO, or if this function should simply return false in this case.

include/llvm/CodeGen/TargetInstrInfo.h

public:
 
   /// Return true if the specified instruction can be predicated.
   /// By default, this returns true for every instruction with a
   /// PredicateOperand.
   virtual bool isPredicable(const MachineInstr &MI) const {
     return MI.getDesc().isPredicable();
   }
 
+  /// Reg is used in MI. Return true if Reg is always guaranteed to be read by
+  /// MI. For example, a predicated instruction may not use its operand
+  /// registers if the predicate is false. But a predicated instruction would
+  /// always use its predicate operand.
+  virtual bool isOperandUseGuaranteed(const MachineInstr &MI, unsigned Reg) {
+    return false;
+  }
+
   /// Return true if it's safe to move a machine
   /// instruction that defines the specified register class.
   virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
     return true;
   }
 
   /// Test if the given instruction should be considered a scheduling boundary.
   /// This primarily includes labels and terminators.

lib/CodeGen/AggressiveAntiDepBreaker.cpp

void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
   // STR %r0, killed %r6, %reg0, 0, 0, %cpsr; mem:ST4[%395]
   // %r6 = LDR %sp, %reg0, 100, 0, %cpsr; mem:LD4[FixedStack12]
   // STR %r0, killed %r6, %reg0, 0, 14, %reg0; mem:ST4[%396](align=8)
   //
   // The first R6 kill is not really a kill since it's killed by a predicated
   // instruction which may not be executed. The second R6 def may or may not
   // re-define R6 so it's not safe to change it since the last R6 use cannot be
   // changed.
-  bool Special = MI.isCall() || MI.hasExtraSrcRegAllocReq() ||
-                 TII->isPredicated(MI) || MI.isInlineAsm();
+  bool Special = MI.isCall() || MI.hasExtraSrcRegAllocReq() || MI.isInlineAsm();
+  bool IsPredicated = TII->isPredicated(MI);
 
   // Scan the register uses for this instruction and update
   // live-ranges, groups and RegRefs.
   for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
     MachineOperand &MO = MI.getOperand(i);
     if (!MO.isReg() || !MO.isUse()) continue;
     unsigned Reg = MO.getReg();
     if (Reg == 0) continue;
 
     LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
                       << State->GetGroup(Reg));
 
     // It wasn't previously live but now it is, this is a kill. Forget
     // the previous live-range information and start a new live-range
     // for the register.
     HandleLastUse(Reg, Count, "(last-use)");
 
     if (Special) {
       LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
       State->UnionGroups(Reg, 0);
     }
+    if (IsPredicated && !TII->isOperandUseGuaranteed(MI, Reg)) {
+      LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(predicated)");
+      State->UnionGroups(Reg, 0);
+    }
 
     // Note register reference...
     const TargetRegisterClass *RC = nullptr;
     if (i < MI.getDesc().getNumOperands())
       RC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
     AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
     RegRefs.insert(std::make_pair(Reg, RR));
   }