[mips] Tolerate the use of the %z inline asm operand modifier with non-immediates.

[tomatabacu]

Summary

Currently, we give an error if %z is used with non-immediates, instead of continuing as if the %z isn't there.

For example, you use the %z operand modifier along with the "Jr" constraints ("r" makes the operand a register, and "J" makes it an immediate, but only if its value is 0).
In this case, you want the compiler to print "$0" if the inline asm input operand turns out to be an immediate zero and you want it to print the register containing the operand, if it's not.

We give an error in the latter case, and we shouldn't (GCC also doesn't).

[dsanders]

test/CodeGen/Mips/inlineasm-operand-code.ll

71

$0 shouldn't be permitted

83

$0 shouldn't be permitted

89

Shouldn't this be restricted to $0?

[tomatabacu]

Addressed Daniel's concerns.

[tomatabacu]

test/CodeGen/Mips/inlineasm-operand-code.ll

89

No, because in this case we no longer have the "J" constraint (which makes zero-values into immediates), so the value is always put into a register.

[dsanders]

LGTM with a small change so that we have to correct the test once we've fixed the materialization of 0.

test/CodeGen/Mips/inlineasm-operand-code.ll

89

The reason I think it should be $0 is that materializing 0 can be done without any code. Whereas the above examples passes in the immediate 0 and printed it as $0, in this code I believe this one should be passing in the register $0.

As we discussed off-list, the code generator is currently materializing 0 with 'addiu $1, $zero, 0'. We need to fix this but it's not related to your patch.

For now, could you add an explicit check for the 'addiu ${{[0-9]+}}, $zero, 0' along with a fixme comment explaining the issue. This way, we will be prompted to correct the test when we fix the materialization problem.

[tomatabacu]

test/CodeGen/Mips/inlineasm-operand-code.ll

89

There's no need for an additional check for addiu, as the test would already fail if the materialization of 0 was fixed.
This is because, for the first argument of the mtc0 instruction, we're checking for any register that is not $0, so if the currently non-$0 register changes into $0, the test will fail.

I'll still add a FIXME with an explanation, though.

[tomatabacu]

Added FIXME with explanation, as suggested by Daniel.

[dsanders]

test/CodeGen/Mips/inlineasm-operand-code.ll

89

Good point. LGTM.

lib/Target/Mips/MipsAsmPrinter.cpp

case 'd': // decimal const int
       return false;
     case 'm': // decimal const int minus 1
       if ((MO.getType()) != MachineOperand::MO_Immediate)
         return true;
       O << MO.getImm() - 1;
       return false;
     case 'z': {
       // $0 if zero, regular printing otherwise
-      if (MO.getType() != MachineOperand::MO_Immediate)
-        return true;
-      int64_t Val = MO.getImm();
-      if (Val)
-        O << Val;
-      else
+      if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
         O << "$0";
         return false;
       }
+      // If not, call printOperand as normal.
+      break;
+    }
     case 'D': // Second part of a double word register operand
     case 'L': // Low order register of a double word register operand
     case 'M': // High order register of a double word register operand
     {
       if (OpNum == 0)
         return true;
       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
       if (!FlagsOP.isImm())

test/CodeGen/Mips/inlineasm-operand-code.ll

 ;CHECK_LITTLE_32:    #NO_APP
   tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 -3) ;
 
 ; z with 0
 ;CHECK_LITTLE_32:    #APP
 ;CHECK_LITTLE_32:    addiu ${{[0-9]+}},${{[0-9]+}},$0
 ;CHECK_LITTLE_32:    #NO_APP
   tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
+
+; z with non-zero and the "r"(register) and "J"(integer zero) constraints
+;CHECK_LITTLE_32:    #APP
+;CHECK_LITTLE_32:    mtc0 ${{[0-9]+}}, ${{[0-9]+}}
+;CHECK_LITTLE_32:    #NO_APP
+  call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind
+
+; z with zero and the "r"(register) and "J"(integer zero) constraints
+;CHECK_LITTLE_32:    #APP
+;CHECK_LITTLE_32:    mtc0 $0, ${{[0-9]+}}
+;CHECK_LITTLE_32:    #NO_APP
+  call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind
+
+; z with non-zero and just the "r"(register) constraint
+;CHECK_LITTLE_32:    #APP
+;CHECK_LITTLE_32:    mtc0 ${{[0-9]+}}, ${{[0-9]+}}
+;CHECK_LITTLE_32:    #NO_APP
+  call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind
+
+; z with zero and just the "r"(register) constraint
+;CHECK_LITTLE_32:    #APP
+;CHECK_LITTLE_32:    mtc0 ${{[0-9]+}}, ${{[0-9]+}}
+;CHECK_LITTLE_32:    #NO_APP
+  call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind
   ret i32 0
 }
 
 ; a long long in 32 bit mode (use to assert)
 define i32 @constraint_longlong() nounwind {
 entry:
 ;CHECK_LITTLE_32-LABEL: constraint_longlong:
 ;CHECK_LITTLE_32:    #APP