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Differential D60188

[AArch64] Update v8.5a MTE instructions
ClosedPublic

Authored by javed.absar on Apr 3 2019, 2:43 AM.

Details

Reviewers
DavidSpickett
Commits
rG5820db93c925: [AArch64] Update v8.5a MTE LDG/STG instructions
rL357583: [AArch64] Update v8.5a MTE LDG/STG instructions
Summary

The latest MTE specification adds register Xt to the STG instruction family:

STG [Xn, #offset] -> STG Xt, [Xn, #offset]

The tag written to memory is taken from Xt rather than Xn.

The LDG instruction also was changed to read return address from Xt:

LDG Xt, [Xn, #offset].

This patch includes those changes and tests.

Diff Detail

Repository
rL LLVM

Event Timeline

javed.absar created this revision.Apr 3 2019, 2:43 AM
Herald added a subscriber: kristof.beyls. · View Herald TranscriptApr 3 2019, 2:43 AM
DavidSpickett accepted this revision.Apr 3 2019, 2:48 AM

LGTM but add the specification link in the commit msg (https://developer.arm.com/docs/ddi0596/c) and reference LDG/STG in the title.

"Update v8.5a MTE LDG and STG instructions." would be fine.

This revision is now accepted and ready to land.Apr 3 2019, 2:48 AM
Closed by commit rL357583: [AArch64] Update v8.5a MTE LDG/STG instructions (authored by javed.absar). · Explain WhyApr 3 2019, 7:12 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptApr 3 2019, 7:12 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AArch64/
24 lines
test/
MC/
AArch64/
291 lines
232 lines
Disassembler/
AArch64/
241 lines

Diff 193488

llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,028 Lines • ▼ Show 20 Linesclass MemTagVector<bit Load, string asm_insn, string asm_opnds,
let Inst{20-12} = 0b000000000; let Inst{20-12} = 0b000000000;
let Inst{4-0} = Rt; let Inst{4-0} = Rt;
let mayLoad = Load; let mayLoad = Load;
} }
class MemTagLoad<string asm_insn, string asm_opnds> class MemTagLoad<string asm_insn, string asm_opnds>
: BaseMemTag<0b01, 0b00, asm_insn, asm_opnds, "", (outs GPR64:$Rt), : BaseMemTag<0b01, 0b00, asm_insn, asm_opnds, "$Rt = $wback",
(ins GPR64sp:$Rn, simm9s16:$offset)> { (outs GPR64:$wback),
(ins GPR64:$Rt, GPR64sp:$Rn, simm9s16:$offset)> {
bits<5> Rt; bits<5> Rt;
bits<9> offset; bits<9> offset;
let Inst{20-12} = offset; let Inst{20-12} = offset;
let Inst{4-0} = Rt; let Inst{4-0} = Rt;
let mayLoad = 1; let mayLoad = 1;
} }
class BaseMemTagStore<bits<2> opc1, bits<2> opc2, string asm_insn, class BaseMemTagStore<bits<2> opc1, bits<2> opc2, string asm_insn,
string asm_opnds, string cstr, dag oops, dag iops> string asm_opnds, string cstr, dag oops, dag iops>
: BaseMemTag<opc1, opc2, asm_insn, asm_opnds, cstr, oops, iops> { : BaseMemTag<opc1, opc2, asm_insn, asm_opnds, cstr, oops, iops> {
bits<5> Rt; bits<5> Rt;
bits<9> offset; bits<9> offset;
let Inst{20-12} = offset; let Inst{20-12} = offset;
let Inst{4-0} = 0b11111; let Inst{4-0} = Rt;
let Unpredictable{4-0} = 0b11111;
let mayStore = 1; let mayStore = 1;
} }
multiclass MemTagStore<bits<2> opc1, string insn> { multiclass MemTagStore<bits<2> opc1, string insn> {
def Offset : def Offset :
BaseMemTagStore<opc1, 0b10, insn, "\t[$Rn, $offset]", "", BaseMemTagStore<opc1, 0b10, insn, "\t$Rt, [$Rn, $offset]", "",
(outs), (ins GPR64sp:$Rn, simm9s16:$offset)>; (outs), (ins GPR64sp:$Rt, GPR64sp:$Rn, simm9s16:$offset)>;
def PreIndex : def PreIndex :
BaseMemTagStore<opc1, 0b11, insn, "\t[$Rn, $offset]!", BaseMemTagStore<opc1, 0b11, insn, "\t$Rt, [$Rn, $offset]!",
"$Rn = $wback,@earlyclobber $wback", "$Rn = $wback,@earlyclobber $wback",
(outs GPR64sp:$wback), (outs GPR64sp:$wback),
(ins GPR64sp:$Rn, simm9s16:$offset)>; (ins GPR64sp:$Rt, GPR64sp:$Rn, simm9s16:$offset)>;
def PostIndex : def PostIndex :
BaseMemTagStore<opc1, 0b01, insn, "\t[$Rn], $offset", BaseMemTagStore<opc1, 0b01, insn, "\t$Rt, [$Rn], $offset",
"$Rn = $wback,@earlyclobber $wback", "$Rn = $wback,@earlyclobber $wback",
(outs GPR64sp:$wback), (outs GPR64sp:$wback),
(ins GPR64sp:$Rn, simm9s16:$offset)>; (ins GPR64sp:$Rt, GPR64sp:$Rn, simm9s16:$offset)>;
def : InstAlias<insn # "\t[$Rn]", def : InstAlias<insn # "\t$Rt, [$Rn]",
(!cast<Instruction>(NAME # "Offset") GPR64sp:$Rn, 0)>; (!cast<Instruction>(NAME # "Offset") GPR64sp:$Rt, GPR64sp:$Rn, 0)>;
} }
//--- //---
// Exception generation // Exception generation
//--- //---
let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm> class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm>
▲ Show 20 Lines • Show All 6,566 Lines • Show Last 20 Lines

llvm/trunk/test/MC/AArch64/armv8.5a-mte-error.s

Show First 20 Lines • Show All 178 Lines • ▼ Show 20 Lines
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: gmi x0, x1, w2 // CHECK-NEXT: gmi x0, x1, w2
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: gmi #1, x1, x2 // CHECK-NEXT: gmi #1, x1, x2
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: gmi x0, #1, x2 // CHECK-NEXT: gmi x0, #1, x2
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: gmi x0, x1, #1 // CHECK-NEXT: gmi x0, x1, #1
stg stg
stg x0 stg x0
stg [xzr] stg w0
stg [x0, #-4112] stg sp
stg [x0, #4096] stg #1
stg [x0, #8] stg x0, [x0, #-4112]
stg [x0, x1] stg x0, [x0, #4096]
stg [w0] stg x0, [x0, #8]
stg x0, [x0, x1]
stg x0, [w0]
stg x0, [xzr]
stg x0, [#1]
// CHECK: too few operands for instruction // CHECK: too few operands for instruction
// CHECK-NEXT: stg // CHECK-NEXT: stg
// CHECK: invalid operand for instruction // CHECK: too few operands for instruction
// CHECK-NEXT: stg x0 // CHECK-NEXT: stg x0
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: [xzr] // CHECK-NEXT: stg w0
// CHECK: too few operands for instruction
// CHECK-NEXT: stg sp
// CHECK: invalid operand for instruction
// CHECK-NEXT: stg #1
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #-4112 // CHECK-NEXT: #-4112
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #4096 // CHECK-NEXT: #4096
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #8 // CHECK-NEXT: #8
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stg [x0, x1] // CHECK-NEXT: stg x0, [x0, x1]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stg [w0] // CHECK-NEXT: stg x0, [w0]
// CHECK: invalid operand for instruction
// CHECK-NEXT: stg x0, [xzr]
// CHECK: invalid operand for instruction
// CHECK-NEXT: stg x0, [#1]
stzg stzg
stzg x0 stzg x0
stzg [xzr] stzg w0
stzg [x0, #-4112] stzg sp
stzg [x0, #4096] stzg #1
stzg [x0, #8] stzg x0, [x0, #-4112]
stzg [x0, x1] stzg x0, [x0, #4096]
stzg [w0] stzg x0, [x0, #8]
stzg x0, [x0, x1]
stzg x0, [w0]
stzg x0, [xzr]
stzg x0, [#1]
// CHECK: too few operands for instruction // CHECK: too few operands for instruction
// CHECK-NEXT: stzg // CHECK-NEXT: stzg
// CHECK: invalid operand for instruction // CHECK: too few operands for instruction
// CHECK-NEXT: stzg x0 // CHECK-NEXT: stzg x0
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: [xzr] // CHECK-NEXT: stzg w0
// CHECK: too few operands for instruction
// CHECK-NEXT: stzg sp
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzg #1
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #-4112 // CHECK-NEXT: #-4112
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #4096 // CHECK-NEXT: #4096
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #8 // CHECK-NEXT: #8
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stzg [x0, x1] // CHECK-NEXT: stzg x0, [x0, x1]
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzg x0, [w0]
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzg x0, [xzr]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stzg [w0] // CHECK-NEXT: stzg x0, [#1]
stg [x0, #-4112]! stg x0, [x0, #-4112]!
stg [x0, #4096]! stg x0, [x0, #4096]!
stg [x0, #8]! stg x0, [x0, #8]!
stg [x0, x1]! stg x0, [x0, x1]!
stg [w0, #255]! stg x0, [w0]!
stg x0, [xzr]!
stg x0, [#1]!
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #-4112 // CHECK-NEXT: #-4112
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #4096 // CHECK-NEXT: #4096
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #8 // CHECK-NEXT: #8
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stg [x0, x1]! // CHECK-NEXT: stg x0, [x0, x1]!
// CHECK: invalid operand for instruction
// CHECK-NEXT: stg x0, [w0]!
// CHECK: invalid operand for instruction
// CHECK-NEXT: stg x0, [xzr]!
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stg [w0, #255]! // CHECK-NEXT: stg x0, [#1]!
stzg [x0, #-4112]! stzg x0, [x0, #-4112]!
stzg [x0, #4096]! stzg x0, [x0, #4096]!
stzg [x0, #8]! stzg x0, [x0, #8]!
stzg [x0, x1]! stzg x0, [x0, x1]!
stzg [w0, #255]! stzg x0, [w0]!
stzg x0, [xzr]!
stzg x0, [#1]!
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #-4112 // CHECK-NEXT: #-4112
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #4096 // CHECK-NEXT: #4096
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #8 // CHECK-NEXT: #8
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stzg [x0, x1]! // CHECK-NEXT: stzg x0, [x0, x1]!
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stzg [w0, #255]! // CHECK-NEXT: stzg x0, [w0]!
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzg x0, [xzr]!
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzg x0, [#1]!
stg [x0], #-4112 stg x0, [x0], #-4112
stg [x0], #4096 stg x0, [x0], #4096
stg [x0], #8 stg x0, [x0], #8
stg [x0], x1 stg x0, [x0], x1
stg [w0], #255 stg x0, [w0], #255
stg x0, [xzr], #255
stg x0, [#1], #255
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #-4112 // CHECK-NEXT: #-4112
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #4096 // CHECK-NEXT: #4096
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #8 // CHECK-NEXT: #8
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stg [x0], x1 // CHECK-NEXT: stg x0, [x0], x1
// CHECK: invalid operand for instruction
// CHECK-NEXT: stg x0, [w0], #255
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stg [w0], #255 // CHECK-NEXT: stg x0, [xzr], #255
// CHECK: invalid operand for instruction
// CHECK-NEXT: stg x0, [#1], #255
stzg [x0], #-4112 stzg x0, [x0], #-4112
stzg [x0], #4096 stzg x0, [x0], #4096
stzg [x0], #8 stzg x0, [x0], #8
stzg [x0], x1 stzg x0, [x0], x1
stzg [w0], #255 stzg x0, [w0], #255
stzg x0, [xzr], #255
stzg x0, [#1], #255
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #-4112 // CHECK-NEXT: #-4112
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #4096 // CHECK-NEXT: #4096
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #8 // CHECK-NEXT: #8
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stzg [x0], x1 // CHECK-NEXT: stzg x0, [x0], x1
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzg x0, [w0], #255
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stzg [w0], #255 // CHECK-NEXT: stzg x0, [xzr], #255
// CHECK: invalid operand for instruction
// CHECK-NEXT: stzg x0, [#1], #255
st2g st2g
st2g x0 st2g x0
st2g [xzr] st2g w0
st2g [x0, #-4112] st2g sp
st2g [x0, #4096] st2g #1
st2g [x0, #8] st2g x0, [x0, #-4112]
st2g [x0, x1] st2g x0, [x0, #4096]
st2g [w0] st2g x0, [x0, #8]
st2g x0, [x0, x1]
st2g x0, [w0]
st2g x0, [xzr]
st2g x0, [#1]
// CHECK: too few operands for instruction // CHECK: too few operands for instruction
// CHECK-NEXT: st2g // CHECK-NEXT: st2g
// CHECK: invalid operand for instruction // CHECK: too few operands for instruction
// CHECK-NEXT: st2g x0 // CHECK-NEXT: st2g x0
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: [xzr] // CHECK-NEXT: st2g w0
// CHECK: too few operands for instruction
// CHECK-NEXT: st2g sp
// CHECK: invalid operand for instruction
// CHECK-NEXT: st2g #1
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #-4112 // CHECK-NEXT: #-4112
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #4096 // CHECK-NEXT: #4096
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #8 // CHECK-NEXT: #8
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: st2g [x0, x1] // CHECK-NEXT: st2g x0, [x0, x1]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: st2g [w0] // CHECK-NEXT: st2g x0, [w0]
// CHECK: invalid operand for instruction
// CHECK-NEXT: st2g x0, [xzr]
// CHECK: invalid operand for instruction
// CHECK-NEXT: st2g x0, [#1]
stz2g stz2g
stz2g [xzr] stz2g x0
stz2g [x0, #-4112] stz2g w0
stz2g [x0, #4096] stz2g sp
stz2g [x0, #8] stz2g #1
stz2g [x0, x1] stz2g x0, [x0, #-4112]
stz2g [w0] stz2g x0, [x0, #4096]
stz2g x0, [x0, #8]
stz2g x0, [x0, x1]
stz2g x0, [w0]
stz2g x0, [xzr]
stz2g x0, [#1]
// CHECK: too few operands for instruction // CHECK: too few operands for instruction
// CHECK-NEXT: stz2g // CHECK-NEXT: stz2g
// CHECK: too few operands for instruction
// CHECK-NEXT: stz2g x0
// CHECK: invalid operand for instruction
// CHECK-NEXT: stz2g w0
// CHECK: too few operands for instruction
// CHECK-NEXT: stz2g sp
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: [xzr] // CHECK-NEXT: stz2g #1
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #-4112 // CHECK-NEXT: #-4112
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #4096 // CHECK-NEXT: #4096
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #8 // CHECK-NEXT: #8
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stz2g [x0, x1] // CHECK-NEXT: stz2g x0, [x0, x1]
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stz2g [w0] // CHECK-NEXT: stz2g x0, [w0]
// CHECK: invalid operand for instruction
// CHECK-NEXT: stz2g x0, [xzr]
// CHECK: invalid operand for instruction
// CHECK-NEXT: stz2g x0, [#1]
st2g [x0, #-4112]! st2g x0, [x0, #-4112]!
st2g [x0, #4096]! st2g x0, [x0, #4096]!
st2g [x0, #8]! st2g x0, [x0, #8]!
st2g [x0, x1]! st2g x0, [x0, x1]!
st2g [w0, #255]! st2g x0, [w0, #256]!
st2g x0, [xzr, #256]!
st2g x0, [#1, #256]!
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #-4112 // CHECK-NEXT: #-4112
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #4096 // CHECK-NEXT: #4096
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #8 // CHECK-NEXT: #8
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: st2g [x0, x1]! // CHECK-NEXT: st2g x0, [x0, x1]!
// CHECK: invalid operand for instruction
// CHECK-NEXT: st2g x0, [w0, #256]!
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: st2g [w0, #255]! // CHECK-NEXT: st2g x0, [xzr, #256]!
// CHECK: invalid operand for instruction
// CHECK-NEXT: st2g x0, [#1, #256]!
stz2g [x0, #-4112]! stz2g x0, [x0, #-4112]!
stz2g [x0, #4096]! stz2g x0, [x0, #4096]!
stz2g [x0, #8]! stz2g x0, [x0, #8]!
stz2g [x0, x1]! stz2g x0, [x0, x1]!
stz2g [w0, #255]! stz2g x0, [w0, #255]!
stz2g x0, [xzr, #255]!
stz2g x0, [#1, #255]!
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #-4112 // CHECK-NEXT: #-4112
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #4096 // CHECK-NEXT: #4096
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #8 // CHECK-NEXT: #8
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stz2g [x0, x1]! // CHECK-NEXT: stz2g x0, [x0, x1]!
// CHECK: invalid operand for instruction
// CHECK-NEXT: stz2g x0, [w0, #255]!
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stz2g [w0, #255]! // CHECK-NEXT: stz2g x0, [xzr, #255]!
// CHECK: invalid operand for instruction
// CHECK-NEXT: stz2g x0, [#1, #255]!
st2g [x0], #-4112 st2g x0, [x0], #-4112
st2g [x0], #4096 st2g x0, [x0], #4096
st2g [x0], #8 st2g x0, [x0], #8
st2g [x0], x1 st2g x0, [x0], x1
st2g [#1], #255 st2g x0, [w0], #255
st2g x0, [xzr], #255
st2g x0, [#1], #255
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #-4112 // CHECK-NEXT: #-4112
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #4096 // CHECK-NEXT: #4096
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #8 // CHECK-NEXT: #8
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: st2g [x0], x1 // CHECK-NEXT: st2g x0, [x0], x1
// CHECK: invalid operand for instruction
// CHECK-NEXT: st2g x0, [w0], #255
// CHECK: invalid operand for instruction
// CHECK-NEXT: st2g x0, [xzr], #255
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: st2g [#1], #255 // CHECK-NEXT: st2g x0, [#1], #255
stz2g [x0], #-4112 stz2g x0, [x0], #-4112
stz2g [x0], #4096 stz2g x0, [x0], #4096
stz2g [x0], #8 stz2g x0, [x0], #8
stz2g [x0], x1 stz2g x0, [x0], x1
stz2g [#0], x1 stz2g x0, [w0], #255
stz2g x0, [xzr], #255
stz2g x0, [#1], #255
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #-4112 // CHECK-NEXT: #-4112
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #4096 // CHECK-NEXT: #4096
// CHECK: index must be a multiple of 16 in range [-4096, 4080] // CHECK: index must be a multiple of 16 in range [-4096, 4080]
// CHECK-NEXT: #8 // CHECK-NEXT: #8
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stz2g [x0], x1 // CHECK-NEXT: stz2g x0, [x0], x1
// CHECK: invalid operand for instruction
// CHECK-NEXT: stz2g x0, [w0], #255
// CHECK: invalid operand for instruction
// CHECK-NEXT: stz2g x0, [xzr], #255
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: stz2g [#0], x1 // CHECK-NEXT: stz2g x0, [#1], #255
stgp sp, x1, [x2, #16] stgp sp, x1, [x2, #16]
stgp x0, sp, [x2, #16] stgp x0, sp, [x2, #16]
stgp x0, x1, [xzr, #16] stgp x0, x1, [xzr, #16]
stgp x0, x1, [x2, #-1040] stgp x0, x1, [x2, #-1040]
stgp x0, x1, [x2, #1024] stgp x0, x1, [x2, #1024]
stgp x0, x1, [x2, #8] stgp x0, x1, [x2, #8]
stgp x0, x1, [x2, x3] stgp x0, x1, [x2, x3]
▲ Show 20 Lines • Show All 241 Lines • ▼ Show 20 Lines
// The rest can only be used with MSR (reg). // The rest can only be used with MSR (reg).
msr gcr_el1, #1 msr gcr_el1, #1
msr rgsr_el1, #2 msr rgsr_el1, #2
msr tfsr_el1, #3 msr tfsr_el1, #3
msr tfsr_el2, #4 msr tfsr_el2, #4
msr tfsr_el3, #5 msr tfsr_el3, #5
msr tfsr_el12, #6 msr tfsr_el12, #6
msr tfsre0_el1, #7 msr tfsre0_el1, #7
// Is read only
msr gmid_el1, #7 msr gmid_el1, #7
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: gcr_el1 // CHECK-NEXT: gcr_el1
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: rgsr_el1 // CHECK-NEXT: rgsr_el1
// CHECK: invalid operand for instruction // CHECK: invalid operand for instruction
// CHECK-NEXT: tfsr_el1 // CHECK-NEXT: tfsr_el1
▲ Show 20 Lines • Show All 195 Lines • Show Last 20 Lines

llvm/trunk/test/MC/AArch64/armv8.5a-mte.s

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
// NOMTE-NEXT: gmi x0, x1, x2 // NOMTE-NEXT: gmi x0, x1, x2
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: gmi x3, sp, x4 // NOMTE-NEXT: gmi x3, sp, x4
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: gmi xzr, x0, x30 // NOMTE-NEXT: gmi xzr, x0, x30
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: gmi x30, x0, xzr // NOMTE-NEXT: gmi x30, x0, xzr
stg [x1] stg x0, [x1]
stg [x1, #-4096] stg x1, [x1, #-4096]
stg [x2, #4080] stg x2, [x2, #4080]
stg [sp, #16] stg x3, [sp, #16]
stg sp, [sp, #16]
// CHECK: stg [x1] // encoding: [0x3f,0x08,0x20,0xd9]
// CHECK: stg [x1, #-4096] // encoding: [0x3f,0x08,0x30,0xd9] // CHECK: stg x0, [x1] // encoding: [0x20,0x08,0x20,0xd9]
// CHECK: stg [x2, #4080] // encoding: [0x5f,0xf8,0x2f,0xd9] // CHECK: stg x1, [x1, #-4096] // encoding: [0x21,0x08,0x30,0xd9]
// CHECK: stg [sp, #16] // encoding: [0xff,0x1b,0x20,0xd9] // CHECK: stg x2, [x2, #4080] // encoding: [0x42,0xf8,0x2f,0xd9]
// CHECK: stg x3, [sp, #16] // encoding: [0xe3,0x1b,0x20,0xd9]
// CHECK: stg sp, [sp, #16] // encoding: [0xff,0x1b,0x20,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stg // NOMTE-NEXT: stg
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stg // NOMTE-NEXT: stg
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stg // NOMTE-NEXT: stg
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stg // NOMTE-NEXT: stg
// NOMTE: instruction requires: mte
// NOMTE-NEXT: stg
stzg [x1] stzg x0, [x1]
stzg [x1, #-4096] stzg x1, [x1, #-4096]
stzg [x2, #4080] stzg x2, [x2, #4080]
stzg [sp, #16] stzg x3, [sp, #16]
stzg sp, [sp, #16]
// CHECK: stzg [x1] // encoding: [0x3f,0x08,0x60,0xd9]
// CHECK: stzg [x1, #-4096] // encoding: [0x3f,0x08,0x70,0xd9] // CHECK: stzg x0, [x1] // encoding: [0x20,0x08,0x60,0xd9]
// CHECK: stzg [x2, #4080] // encoding: [0x5f,0xf8,0x6f,0xd9] // CHECK: stzg x1, [x1, #-4096] // encoding: [0x21,0x08,0x70,0xd9]
// CHECK: stzg [sp, #16] // encoding: [0xff,0x1b,0x60,0xd9] // CHECK: stzg x2, [x2, #4080] // encoding: [0x42,0xf8,0x6f,0xd9]
// CHECK: stzg x3, [sp, #16] // encoding: [0xe3,0x1b,0x60,0xd9]
// CHECK: stzg sp, [sp, #16] // encoding: [0xff,0x1b,0x60,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stzg // NOMTE-NEXT: stzg
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stzg // NOMTE-NEXT: stzg
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stzg // NOMTE-NEXT: stzg
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stzg // NOMTE-NEXT: stzg
// NOMTE: instruction requires: mte
// NOMTE-NEXT: stzg
stg [x1, #-4096]! stg x0, [x1, #-4096]!
stg [x2, #4080]! stg x1, [x2, #4080]!
stg [sp, #16]! stg x2, [sp, #16]!
stg sp, [sp, #16]!
// CHECK: stg [x1, #-4096]! // encoding: [0x3f,0x0c,0x30,0xd9]
// CHECK: stg [x2, #4080]! // encoding: [0x5f,0xfc,0x2f,0xd9] // CHECK: stg x0, [x1, #-4096]! // encoding: [0x20,0x0c,0x30,0xd9]
// CHECK: stg [sp, #16]! // encoding: [0xff,0x1f,0x20,0xd9] // CHECK: stg x1, [x2, #4080]! // encoding: [0x41,0xfc,0x2f,0xd9]
// CHECK: stg x2, [sp, #16]! // encoding: [0xe2,0x1f,0x20,0xd9]
// CHECK: stg sp, [sp, #16]! // encoding: [0xff,0x1f,0x20,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stg // NOMTE-NEXT: stg
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stg // NOMTE-NEXT: stg
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stg // NOMTE-NEXT: stg
// NOMTE: instruction requires: mte
// NOMTE-NEXT: stg
stzg [x1, #-4096]! stzg x0, [x1, #-4096]!
stzg [x2, #4080]! stzg x1, [x2, #4080]!
stzg [sp, #16]! stzg x2, [sp, #16]!
stzg sp, [sp, #16]!
// CHECK: stzg [x1, #-4096]! // encoding: [0x3f,0x0c,0x70,0xd9]
// CHECK: stzg [x2, #4080]! // encoding: [0x5f,0xfc,0x6f,0xd9] // CHECK: stzg x0, [x1, #-4096]! // encoding: [0x20,0x0c,0x70,0xd9]
// CHECK: stzg [sp, #16]! // encoding: [0xff,0x1f,0x60,0xd9] // CHECK: stzg x1, [x2, #4080]! // encoding: [0x41,0xfc,0x6f,0xd9]
// CHECK: stzg x2, [sp, #16]! // encoding: [0xe2,0x1f,0x60,0xd9]
// CHECK: stzg sp, [sp, #16]! // encoding: [0xff,0x1f,0x60,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stzg // NOMTE-NEXT: stzg
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stzg // NOMTE-NEXT: stzg
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stzg // NOMTE-NEXT: stzg
// NOMTE: instruction requires: mte
// NOMTE-NEXT: stzg
stg [x1], #-4096 stg x0, [x1], #-4096
stg [x2], #4080 stg x1, [x2], #4080
stg [sp], #16 stg x2, [sp], #16
stg sp, [sp], #16
// CHECK: stg [x1], #-4096 // encoding: [0x3f,0x04,0x30,0xd9]
// CHECK: stg [x2], #4080 // encoding: [0x5f,0xf4,0x2f,0xd9] // CHECK: stg x0, [x1], #-4096 // encoding: [0x20,0x04,0x30,0xd9]
// CHECK: stg [sp], #16 // encoding: [0xff,0x17,0x20,0xd9] // CHECK: stg x1, [x2], #4080 // encoding: [0x41,0xf4,0x2f,0xd9]
// CHECK: stg x2, [sp], #16 // encoding: [0xe2,0x17,0x20,0xd9]
// CHECK: stg sp, [sp], #16 // encoding: [0xff,0x17,0x20,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stg // NOMTE-NEXT: stg
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stg // NOMTE-NEXT: stg
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stg // NOMTE-NEXT: stg
// NOMTE: instruction requires: mte
// NOMTE-NEXT: stg
stzg [x1], #-4096 stzg x0, [x1], #-4096
stzg [x2], #4080 stzg x1, [x2], #4080
stzg [sp], #16 stzg x2, [sp], #16
stzg sp, [sp], #16
// CHECK: stzg [x1], #-4096 // encoding: [0x3f,0x04,0x70,0xd9]
// CHECK: stzg [x2], #4080 // encoding: [0x5f,0xf4,0x6f,0xd9] // CHECK: stzg x0, [x1], #-4096 // encoding: [0x20,0x04,0x70,0xd9]
// CHECK: stzg [sp], #16 // encoding: [0xff,0x17,0x60,0xd9] // CHECK: stzg x1, [x2], #4080 // encoding: [0x41,0xf4,0x6f,0xd9]
// CHECK: stzg x2, [sp], #16 // encoding: [0xe2,0x17,0x60,0xd9]
// CHECK: stzg sp, [sp], #16 // encoding: [0xff,0x17,0x60,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stzg // NOMTE-NEXT: stzg
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stzg // NOMTE-NEXT: stzg
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stzg // NOMTE-NEXT: stzg
// NOMTE: instruction requires: mte
// NOMTE-NEXT: stzg
st2g [x1] st2g x0, [x1]
st2g [x1, #-4096] st2g x1, [x1, #-4096]
st2g [x2, #4080] st2g x2, [x2, #4080]
st2g [sp, #16] st2g x3, [sp, #16]
st2g sp, [sp, #16]
// CHECK: st2g [x1] // encoding: [0x3f,0x08,0xa0,0xd9]
// CHECK: st2g [x1, #-4096] // encoding: [0x3f,0x08,0xb0,0xd9] // CHECK: st2g x0, [x1] // encoding: [0x20,0x08,0xa0,0xd9]
// CHECK: st2g [x2, #4080] // encoding: [0x5f,0xf8,0xaf,0xd9] // CHECK: st2g x1, [x1, #-4096] // encoding: [0x21,0x08,0xb0,0xd9]
// CHECK: st2g [sp, #16] // encoding: [0xff,0x1b,0xa0,0xd9] // CHECK: st2g x2, [x2, #4080] // encoding: [0x42,0xf8,0xaf,0xd9]
// CHECK: st2g x3, [sp, #16] // encoding: [0xe3,0x1b,0xa0,0xd9]
// CHECK: st2g sp, [sp, #16] // encoding: [0xff,0x1b,0xa0,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: st2g // NOMTE-NEXT: st2g
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: st2g // NOMTE-NEXT: st2g
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: st2g // NOMTE-NEXT: st2g
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: st2g // NOMTE-NEXT: st2g
// NOMTE: instruction requires: mte
// NOMTE-NEXT: st2g
stz2g [x1] stz2g x0, [x1]
stz2g [x1, #-4096] stz2g x1, [x1, #-4096]
stz2g [x2, #4080] stz2g x2, [x2, #4080]
stz2g [sp, #16] stz2g x3, [sp, #16]
stz2g sp, [sp, #16]
// CHECK: stz2g [x1] // encoding: [0x3f,0x08,0xe0,0xd9]
// CHECK: stz2g [x1, #-4096] // encoding: [0x3f,0x08,0xf0,0xd9] // CHECK: stz2g x0, [x1] // encoding: [0x20,0x08,0xe0,0xd9]
// CHECK: stz2g [x2, #4080] // encoding: [0x5f,0xf8,0xef,0xd9] // CHECK: stz2g x1, [x1, #-4096] // encoding: [0x21,0x08,0xf0,0xd9]
// CHECK: stz2g [sp, #16] // encoding: [0xff,0x1b,0xe0,0xd9] // CHECK: stz2g x2, [x2, #4080] // encoding: [0x42,0xf8,0xef,0xd9]
// CHECK: stz2g x3, [sp, #16] // encoding: [0xe3,0x1b,0xe0,0xd9]
// CHECK: stz2g sp, [sp, #16] // encoding: [0xff,0x1b,0xe0,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stz2g // NOMTE-NEXT: stz2g
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stz2g // NOMTE-NEXT: stz2g
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stz2g // NOMTE-NEXT: stz2g
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stz2g // NOMTE-NEXT: stz2g
// NOMTE: instruction requires: mte
// NOMTE-NEXT: stz2g
st2g [x1, #-4096]! st2g x0, [x1, #-4096]!
st2g [x2, #4080]! st2g x1, [x2, #4080]!
st2g [sp, #16]! st2g x2, [sp, #16]!
st2g sp, [sp, #16]!
// CHECK: st2g [x1, #-4096]! // encoding: [0x3f,0x0c,0xb0,0xd9]
// CHECK: st2g [x2, #4080]! // encoding: [0x5f,0xfc,0xaf,0xd9] // CHECK: st2g x0, [x1, #-4096]! // encoding: [0x20,0x0c,0xb0,0xd9]
// CHECK: st2g [sp, #16]! // encoding: [0xff,0x1f,0xa0,0xd9] // CHECK: st2g x1, [x2, #4080]! // encoding: [0x41,0xfc,0xaf,0xd9]
// CHECK: st2g x2, [sp, #16]! // encoding: [0xe2,0x1f,0xa0,0xd9]
// CHECK: st2g sp, [sp, #16]! // encoding: [0xff,0x1f,0xa0,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: st2g // NOMTE-NEXT: st2g
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: st2g // NOMTE-NEXT: st2g
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: st2g // NOMTE-NEXT: st2g
// NOMTE: instruction requires: mte
// NOMTE-NEXT: st2g
stz2g [x1, #-4096]! stz2g x0, [x1, #-4096]!
stz2g [x2, #4080]! stz2g x1, [x2, #4080]!
stz2g [sp, #16]! stz2g x2, [sp, #16]!
stz2g sp, [sp, #16]!
// CHECK: stz2g [x1, #-4096]! // encoding: [0x3f,0x0c,0xf0,0xd9]
// CHECK: stz2g [x2, #4080]! // encoding: [0x5f,0xfc,0xef,0xd9] // CHECK: stz2g x0, [x1, #-4096]! // encoding: [0x20,0x0c,0xf0,0xd9]
// CHECK: stz2g [sp, #16]! // encoding: [0xff,0x1f,0xe0,0xd9] // CHECK: stz2g x1, [x2, #4080]! // encoding: [0x41,0xfc,0xef,0xd9]
// CHECK: stz2g x2, [sp, #16]! // encoding: [0xe2,0x1f,0xe0,0xd9]
// CHECK: stz2g sp, [sp, #16]! // encoding: [0xff,0x1f,0xe0,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stz2g // NOMTE-NEXT: stz2g
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stz2g // NOMTE-NEXT: stz2g
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stz2g // NOMTE-NEXT: stz2g
// NOMTE: instruction requires: mte
// NOMTE-NEXT: stz2g
st2g [x1], #-4096 st2g x0, [x1], #-4096
st2g [x2], #4080 st2g x1, [x2], #4080
st2g [sp], #16 st2g x2, [sp], #16
st2g sp, [sp], #16
// CHECK: st2g [x1], #-4096 // encoding: [0x3f,0x04,0xb0,0xd9]
// CHECK: st2g [x2], #4080 // encoding: [0x5f,0xf4,0xaf,0xd9] // CHECK: st2g x0, [x1], #-4096 // encoding: [0x20,0x04,0xb0,0xd9]
// CHECK: st2g [sp], #16 // encoding: [0xff,0x17,0xa0,0xd9] // CHECK: st2g x1, [x2], #4080 // encoding: [0x41,0xf4,0xaf,0xd9]
// CHECK: st2g x2, [sp], #16 // encoding: [0xe2,0x17,0xa0,0xd9]
// CHECK: st2g sp, [sp], #16 // encoding: [0xff,0x17,0xa0,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: st2g // NOMTE-NEXT: st2g
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: st2g // NOMTE-NEXT: st2g
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: st2g // NOMTE-NEXT: st2g
// NOMTE: instruction requires: mte
// NOMTE-NEXT: st2g
stz2g [x1], #-4096 stz2g x0, [x1], #-4096
stz2g [x2], #4080 stz2g x1, [x2], #4080
stz2g [sp], #16 stz2g x2, [sp], #16
stz2g sp, [sp], #16
// CHECK: stz2g [x1], #-4096 // encoding: [0x3f,0x04,0xf0,0xd9]
// CHECK: stz2g [x2], #4080 // encoding: [0x5f,0xf4,0xef,0xd9] // CHECK: stz2g x0, [x1], #-4096 // encoding: [0x20,0x04,0xf0,0xd9]
// CHECK: stz2g [sp], #16 // encoding: [0xff,0x17,0xe0,0xd9] // CHECK: stz2g x1, [x2], #4080 // encoding: [0x41,0xf4,0xef,0xd9]
// CHECK: stz2g x2, [sp], #16 // encoding: [0xe2,0x17,0xe0,0xd9]
// CHECK: stz2g sp, [sp], #16 // encoding: [0xff,0x17,0xe0,0xd9]
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stz2g // NOMTE-NEXT: stz2g
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stz2g // NOMTE-NEXT: stz2g
// NOMTE: instruction requires: mte // NOMTE: instruction requires: mte
// NOMTE-NEXT: stz2g // NOMTE-NEXT: stz2g
// NOMTE: instruction requires: mte
// NOMTE-NEXT: stz2g
stgp x0, x1, [x2] stgp x0, x1, [x2]
stgp x0, x1, [x2, #-1024] stgp x0, x1, [x2, #-1024]
stgp x0, x1, [x2, #1008] stgp x0, x1, [x2, #1008]
stgp x0, x1, [sp, #16] stgp x0, x1, [sp, #16]
stgp xzr, x1, [x2, #16] stgp xzr, x1, [x2, #16]
stgp x0, xzr, [x2, #16] stgp x0, xzr, [x2, #16]
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llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt

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# NOMTE-NEXT: [0xe0,0x03,0xdf,0x9a] # NOMTE-NEXT: [0xe0,0x03,0xdf,0x9a]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xe0,0x03,0xdf,0xba] # NOMTE-NEXT: [0xe0,0x03,0xdf,0xba]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x1f,0x00,0xc1,0xba] # NOMTE-NEXT: [0x1f,0x00,0xc1,0xba]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xff,0x03,0xdf,0xba] # NOMTE-NEXT: [0xff,0x03,0xdf,0xba]
[0x3f,0x08,0x30,0xd9] [0x20,0x08,0x30,0xd9]
[0x5f,0xf8,0x2f,0xd9] [0x41,0xf8,0x2f,0xd9]
[0xff,0x1b,0x20,0xd9] [0xe2,0x1b,0x20,0xd9]
[0x23,0x08,0x20,0xd9]
[0x3f,0x08,0x20,0xd9] [0x3f,0x08,0x20,0xd9]
# CHECK: stg [x1, #-4096] # CHECK: stg x0, [x1, #-4096]
# CHECK: stg [x2, #4080] # CHECK: stg x1, [x2, #4080]
# CHECK: stg [sp, #16] # CHECK: stg x2, [sp, #16]
# CHECK: stg [x1] # CHECK: stg x3, [x1]
# CHECK: stg sp, [x1]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x20,0x08,0x30,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x08,0x30,0xd9] # NOMTE-NEXT: [0x41,0xf8,0x2f,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0xf8,0x2f,0xd9] # NOMTE-NEXT: [0xe2,0x1b,0x20,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xff,0x1b,0x20,0xd9] # NOMTE-NEXT: [0x23,0x08,0x20,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x08,0x20,0xd9] # NOMTE-NEXT: [0x3f,0x08,0x20,0xd9]
[0x3f,0x08,0x70,0xd9] [0x20,0x08,0x70,0xd9]
[0x5f,0xf8,0x6f,0xd9] [0x41,0xf8,0x6f,0xd9]
[0xff,0x1b,0x60,0xd9] [0xe2,0x1b,0x60,0xd9]
[0x23,0x08,0x60,0xd9]
[0x3f,0x08,0x60,0xd9] [0x3f,0x08,0x60,0xd9]
# CHECK: stzg [x1, #-4096] # CHECK: stzg x0, [x1, #-4096]
# CHECK: stzg [x2, #4080] # CHECK: stzg x1, [x2, #4080]
# CHECK: stzg [sp, #16] # CHECK: stzg x2, [sp, #16]
# CHECK: stzg [x1] # CHECK: stzg x3, [x1]
# CHECK: stzg sp, [x1]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x08,0x70,0xd9] # NOMTE-NEXT: [0x20,0x08,0x70,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0xf8,0x6f,0xd9] # NOMTE-NEXT: [0x41,0xf8,0x6f,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xff,0x1b,0x60,0xd9] # NOMTE-NEXT: [0xe2,0x1b,0x60,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x23,0x08,0x60,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x08,0x60,0xd9] # NOMTE-NEXT: [0x3f,0x08,0x60,0xd9]
[0x3f,0x0c,0x30,0xd9] [0x20,0x0c,0x30,0xd9]
[0x5f,0xfc,0x2f,0xd9] [0x41,0xfc,0x2f,0xd9]
[0xe2,0x1f,0x20,0xd9]
[0xff,0x1f,0x20,0xd9] [0xff,0x1f,0x20,0xd9]
# CHECK: stg [x1, #-4096]! # CHECK: stg x0, [x1, #-4096]!
# CHECK: stg [x2, #4080]! # CHECK: stg x1, [x2, #4080]!
# CHECK: stg [sp, #16]! # CHECK: stg x2, [sp, #16]!
# CHECK: stg sp, [sp, #16]!
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x0c,0x30,0xd9] # NOMTE-NEXT: [0x20,0x0c,0x30,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x41,0xfc,0x2f,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0xfc,0x2f,0xd9] # NOMTE-NEXT: [0xe2,0x1f,0x20,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xff,0x1f,0x20,0xd9] # NOMTE-NEXT: [0xff,0x1f,0x20,0xd9]
[0x3f,0x0c,0x70,0xd9] [0x20,0x0c,0x70,0xd9]
[0x5f,0xfc,0x6f,0xd9] [0x41,0xfc,0x6f,0xd9]
[0xe2,0x1f,0x60,0xd9]
[0xff,0x1f,0x60,0xd9] [0xff,0x1f,0x60,0xd9]
# CHECK: stzg [x1, #-4096]! # CHECK: stzg x0, [x1, #-4096]!
# CHECK: stzg [x2, #4080]! # CHECK: stzg x1, [x2, #4080]!
# CHECK: stzg [sp, #16]! # CHECK: stzg x2, [sp, #16]!
# CHECK: stzg sp, [sp, #16]!
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x0c,0x70,0xd9] # NOMTE-NEXT: [0x20,0x0c,0x70,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0xfc,0x6f,0xd9] # NOMTE-NEXT: [0x41,0xfc,0x6f,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xe2,0x1f,0x60,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xff,0x1f,0x60,0xd9] # NOMTE-NEXT: [0xff,0x1f,0x60,0xd9]
[0x3f,0x04,0x30,0xd9] [0x20,0x04,0x30,0xd9]
[0x5f,0xf4,0x2f,0xd9] [0x41,0xf4,0x2f,0xd9]
[0xe2,0x17,0x20,0xd9]
[0xff,0x17,0x20,0xd9] [0xff,0x17,0x20,0xd9]
# CHECK: stg [x1], #-4096 # CHECK: stg x0, [x1], #-4096
# CHECK: stg [x2], #4080 # CHECK: stg x1, [x2], #4080
# CHECK: stg [sp], #16 # CHECK: stg x2, [sp], #16
# CHECK: stg sp, [sp], #16
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x04,0x30,0xd9] # NOMTE-NEXT: [0x20,0x04,0x30,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x41,0xf4,0x2f,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0xf4,0x2f,0xd9] # NOMTE-NEXT: [0xe2,0x17,0x20,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xff,0x17,0x20,0xd9] # NOMTE-NEXT: [0xff,0x17,0x20,0xd9]
[0x3f,0x04,0x70,0xd9] [0x20,0x04,0x70,0xd9]
[0x5f,0xf4,0x6f,0xd9] [0x41,0xf4,0x6f,0xd9]
[0xe2,0x17,0x60,0xd9]
[0xff,0x17,0x60,0xd9] [0xff,0x17,0x60,0xd9]
# CHECK: stzg [x1], #-4096 # CHECK: stzg x0, [x1], #-4096
# CHECK: stzg [x2], #4080 # CHECK: stzg x1, [x2], #4080
# CHECK: stzg [sp], #16 # CHECK: stzg x2, [sp], #16
# CHECK: stzg sp, [sp], #16
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x04,0x70,0xd9] # NOMTE-NEXT: [0x20,0x04,0x70,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x41,0xf4,0x6f,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0xf4,0x6f,0xd9] # NOMTE-NEXT: [0xe2,0x17,0x60,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xff,0x17,0x60,0xd9] # NOMTE-NEXT: [0xff,0x17,0x60,0xd9]
[0x3f,0x08,0xb0,0xd9] [0x20,0x08,0xb0,0xd9]
[0x5f,0xf8,0xaf,0xd9] [0x41,0xf8,0xaf,0xd9]
[0xff,0x1b,0xa0,0xd9] [0xe2,0x1b,0xa0,0xd9]
[0x23,0x08,0xa0,0xd9]
[0x3f,0x08,0xa0,0xd9] [0x3f,0x08,0xa0,0xd9]
# CHECK: st2g [x1, #-4096] # CHECK: st2g x0, [x1, #-4096]
# CHECK: st2g [x2, #4080] # CHECK: st2g x1, [x2, #4080]
# CHECK: st2g [sp, #16] # CHECK: st2g x2, [sp, #16]
# CHECK: st2g [x1] # CHECK: st2g x3, [x1]
# CHECK: st2g sp, [x1]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x08,0xb0,0xd9] # NOMTE-NEXT: [0x20,0x08,0xb0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0xf8,0xaf,0xd9] # NOMTE-NEXT: [0x41,0xf8,0xaf,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xff,0x1b,0xa0,0xd9] # NOMTE-NEXT: [0xe2,0x1b,0xa0,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x23,0x08,0xa0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x08,0xa0,0xd9] # NOMTE-NEXT: [0x3f,0x08,0xa0,0xd9]
[0x3f,0x08,0xf0,0xd9] [0x20,0x08,0xf0,0xd9]
[0x5f,0xf8,0xef,0xd9] [0x41,0xf8,0xef,0xd9]
[0xff,0x1b,0xe0,0xd9] [0xe2,0x1b,0xe0,0xd9]
[0x23,0x08,0xe0,0xd9]
[0x3f,0x08,0xe0,0xd9] [0x3f,0x08,0xe0,0xd9]
# CHECK: stz2g [x1, #-4096] # CHECK: stz2g x0, [x1, #-4096]
# CHECK: stz2g [x2, #4080] # CHECK: stz2g x1, [x2, #4080]
# CHECK: stz2g [sp, #16] # CHECK: stz2g x2, [sp, #16]
# CHECK: stz2g [x1] # CHECK: stz2g x3, [x1]
# CHECK: stz2g sp, [x1]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x08,0xf0,0xd9] # NOMTE-NEXT: [0x20,0x08,0xf0,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x41,0xf8,0xef,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0xf8,0xef,0xd9] # NOMTE-NEXT: [0xe2,0x1b,0xe0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xff,0x1b,0xe0,0xd9] # NOMTE-NEXT: [0x23,0x08,0xe0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x08,0xe0,0xd9] # NOMTE-NEXT: [0x3f,0x08,0xe0,0xd9]
[0x3f,0x0c,0xb0,0xd9] [0x20,0x0c,0xb0,0xd9]
[0x5f,0xfc,0xaf,0xd9] [0x41,0xfc,0xaf,0xd9]
[0xe2,0x1f,0xa0,0xd9]
[0xff,0x1f,0xa0,0xd9] [0xff,0x1f,0xa0,0xd9]
# CHECK: st2g [x1, #-4096]! # CHECK: st2g x0, [x1, #-4096]!
# CHECK: st2g [x2, #4080]! # CHECK: st2g x1, [x2, #4080]!
# CHECK: st2g [sp, #16]! # CHECK: st2g x2, [sp, #16]!
# CHECK: st2g sp, [sp, #16]!
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x0c,0xb0,0xd9] # NOMTE-NEXT: [0x20,0x0c,0xb0,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x41,0xfc,0xaf,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0xfc,0xaf,0xd9] # NOMTE-NEXT: [0xe2,0x1f,0xa0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xff,0x1f,0xa0,0xd9] # NOMTE-NEXT: [0xff,0x1f,0xa0,0xd9]
[0x3f,0x0c,0xf0,0xd9] [0x20,0x0c,0xf0,0xd9]
[0x5f,0xfc,0xef,0xd9] [0x41,0xfc,0xef,0xd9]
[0xe2,0x1f,0xe0,0xd9]
[0xff,0x1f,0xe0,0xd9] [0xff,0x1f,0xe0,0xd9]
# CHECK: stz2g [x1, #-4096]! # CHECK: stz2g x0, [x1, #-4096]!
# CHECK: stz2g [x2, #4080]! # CHECK: stz2g x1, [x2, #4080]!
# CHECK: stz2g [sp, #16]! # CHECK: stz2g x2, [sp, #16]!
# CHECK: stz2g sp, [sp, #16]!
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x0c,0xf0,0xd9] # NOMTE-NEXT: [0x20,0x0c,0xf0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0xfc,0xef,0xd9] # NOMTE-NEXT: [0x41,0xfc,0xef,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xe2,0x1f,0xe0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xff,0x1f,0xe0,0xd9] # NOMTE-NEXT: [0xff,0x1f,0xe0,0xd9]
[0x3f,0x04,0xb0,0xd9] [0x20,0x04,0xb0,0xd9]
[0x5f,0xf4,0xaf,0xd9] [0x41,0xf4,0xaf,0xd9]
[0xe2,0x17,0xa0,0xd9]
[0xff,0x17,0xa0,0xd9] [0xff,0x17,0xa0,0xd9]
# CHECK: st2g [x1], #-4096 # CHECK: st2g x0, [x1], #-4096
# CHECK: st2g [x2], #4080 # CHECK: st2g x1, [x2], #4080
# CHECK: st2g [sp], #16 # CHECK: st2g x2, [sp], #16
# CHECK: st2g sp, [sp], #16
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x04,0xb0,0xd9] # NOMTE-NEXT: [0x20,0x04,0xb0,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x41,0xf4,0xaf,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0xf4,0xaf,0xd9] # NOMTE-NEXT: [0xe2,0x17,0xa0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xff,0x17,0xa0,0xd9] # NOMTE-NEXT: [0xff,0x17,0xa0,0xd9]
[0x3f,0x04,0xf0,0xd9] [0x20,0x04,0xf0,0xd9]
[0x5f,0xf4,0xef,0xd9] [0x41,0xf4,0xef,0xd9]
[0xe2,0x17,0xe0,0xd9]
[0xff,0x17,0xe0,0xd9] [0xff,0x17,0xe0,0xd9]
# CHECK: stz2g [x1], #-4096 # CHECK: stz2g x0, [x1], #-4096
# CHECK: stz2g [x2], #4080 # CHECK: stz2g x1, [x2], #4080
# CHECK: stz2g [sp], #16 # CHECK: stz2g x2, [sp], #16
# CHECK: stz2g sp, [sp], #16
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x3f,0x04,0xf0,0xd9] # NOMTE-NEXT: [0x20,0x04,0xf0,0xd9]
# NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x41,0xf4,0xef,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0x5f,0xf4,0xef,0xd9] # NOMTE-NEXT: [0xe2,0x17,0xe0,0xd9]
# NOMTE: warning: invalid instruction encoding # NOMTE: warning: invalid instruction encoding
# NOMTE-NEXT: [0xff,0x17,0xe0,0xd9] # NOMTE-NEXT: [0xff,0x17,0xe0,0xd9]
[0x40,0x04,0x20,0x69] [0x40,0x04,0x20,0x69]
[0x40,0x84,0x1f,0x69] [0x40,0x84,0x1f,0x69]
[0xe0,0x87,0x00,0x69] [0xe0,0x87,0x00,0x69]
[0x5f,0x84,0x00,0x69] [0x5f,0x84,0x00,0x69]
[0x40,0xfc,0x00,0x69] [0x40,0xfc,0x00,0x69]
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