Broken, not for review: X86TargetLowering::EmitLoweredSelect(): ignore harmless instrs between two PHI's

[lebedev.ri]

Summary

See D59001, D59035.

[lebedev.ri]

Was just a proof-of-concept, not anything i to be polished&merged.
The real solution is likely to promote all the i8 ops.

lib/Target/X86/X86ISelLowering.cpp

if (T1.getValueType() == T2.getValueType() &&
         T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
       SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, T1.getValueType(), T2, T1,
                                  CC, Cond);
       return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
     }
   }
 
   // Or finally, promote i8/i16 cmovs if it won't prevent folding a load.
-  // FIXME: we should not limit promotion of i8 case to only when the CMOV is
-  //        legal, but EmitLoweredSelect() can not deail with these extensions
-  //        being inserted between two CMOV's. (in i16 case too TBN)
-  //        https://bugs.llvm.org/show_bug.cgi?id=40974
-  if (((Op.getValueType() == MVT::i8 && Subtarget.hasCMov()) ||
-       Op.getValueType() == MVT::i16) &&
+  if ((Op.getValueType() == MVT::i8 || Op.getValueType() == MVT::i16) &&
       !MayFoldLoad(Op1) && !MayFoldLoad(Op2)) {
     Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1);
     Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2);
     SDValue Ops[] = { Op2, Op1, CC, Cond };
     SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, MVT::i32, Ops);
     return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
   }
 
X86TargetLowering::EmitLoweredCascadedSelect(MachineInstr &FirstCMOV,
 
   // Now remove the CMOVs.
   FirstCMOV.eraseFromParent();
   SecondCascadedCMOV.eraseFromParent();
 
   return SinkMBB;
 }
 
+template <typename IterT>
+inline bool isHarmlessInstructionBetweenTwoCMOVPhis(IterT It) {
+  if (It->isDebugInstr() || It->isImplicitDef() || It->isExtractSubreg() ||
+      It->isInsertSubreg() || It->isSubregToReg() || It->isMoveReg() ||
+      It->isCopy())
+    return true;
+  switch (It->getOpcode()) {
+  case ISD::SIGN_EXTEND:
+  case ISD::ZERO_EXTEND:
+  case ISD::ANY_EXTEND:
+  case ISD::TRUNCATE:
+  case ISD::SIGN_EXTEND_INREG:
+  case X86::MOVZX16rr16:
+  case X86::MOVZX16rr8:
+  case X86::MOVZX32rr16:
+  case X86::MOVZX32rr8:
+  case X86::MOVZX32rr8_NOREX:
+  case X86::MOVZX64rr16:
+  case X86::MOVZX64rr8:
+  case X86::MOVSX16rr16:
+  case X86::MOVSX16rr32:
+  case X86::MOVSX16rr8:
+  case X86::MOVSX32rr16:
+  case X86::MOVSX32rr32:
+  case X86::MOVSX32rr8:
+  case X86::MOVSX32rr8_NOREX:
+  case X86::MOVSX64rr16:
+  case X86::MOVSX64rr32:
+  case X86::MOVSX64rr8:
+    return true;
+  default:
+    return false;
+  }
+  // FIXME: can we instead simply accept all non-control-flow-altering instrs?
+}
+
+template <typename IterT>
+inline IterT skipHarmlessInstructionsBetweenTwoPhisForward(IterT It,
+                                                           IterT End) {
+  while (It != End && isHarmlessInstructionBetweenTwoCMOVPhis(It))
+    It++;
+  return It;
+}
+
 MachineBasicBlock *
 X86TargetLowering::EmitLoweredSelect(MachineInstr &MI,
                                      MachineBasicBlock *ThisMBB) const {
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   DebugLoc DL = MI.getDebugLoc();
 
   // To "insert" a SELECT_CC instruction, we actually have to insert the
   // diamond control-flow pattern.  The incoming instruction knows the
X86TargetLowering::EmitLoweredSelect(MachineInstr &MI,
   MachineBasicBlock::iterator NextMIIt = MachineBasicBlock::iterator(MI);
 
   // Check for case 1, where there are multiple CMOVs with the same condition
   // first.  Of the two cases of multiple CMOV lowerings, case 1 reduces the
   // number of jumps the most.
 
   if (isCMOVPseudo(MI)) {
     // See if we have a string of CMOVS with the same condition. Skip over
-    // intervening debug insts.
+    // intervening harmless insts.
     while (NextMIIt != ThisMBB->end() && isCMOVPseudo(*NextMIIt) &&
            (NextMIIt->getOperand(3).getImm() == CC ||
-            NextMIIt->getOperand(3).getImm() == OppCC)) {
+            NextMIIt->getOperand(3).getImm() == OppCC) &&
+           // No instruction between the orig CMOV and this new CMOV (excl. all
+           // other CMOV's) may be the definition of op1 or op2 of new CMOV.
+           // Else moving this new CMOV will break def-use chain.
+           llvm::none_of(
+               llvm::make_range(MachineBasicBlock::iterator(MI), NextMIIt),
+               [&NextMIIt](MachineBasicBlock::iterator It) {
+                 if (isCMOVPseudo(*It))
+                   return false; // CMOV can reference previous CMOV's.
+                 return llvm::any_of(
+                     It->operands(), [&NextMIIt](MachineOperand Op) {
+                       if (!Op.isReg() || !Op.isDef())
+                         return false;
+                       return Op.getReg() == NextMIIt->getOperand(1).getReg() ||
+                              Op.getReg() == NextMIIt->getOperand(2).getReg();
+                     });
+               })) {
       LastCMOV = &*NextMIIt;
       ++NextMIIt;
-      NextMIIt = skipDebugInstructionsForward(NextMIIt, ThisMBB->end());
+      NextMIIt = skipHarmlessInstructionsBetweenTwoPhisForward(NextMIIt,
+                                                               ThisMBB->end());
     }
   }
 
   // This checks for case 2, but only do this if we didn't already find
   // case 1, as indicated by LastCMOV == MI.
   if (LastCMOV == &MI && NextMIIt != ThisMBB->end() &&
       NextMIIt->getOpcode() == MI.getOpcode() &&
       NextMIIt->getOperand(2).getReg() == MI.getOperand(2).getReg() &&
X86TargetLowering::EmitLoweredSelect(MachineInstr &MI,
   // live into the sink and copy blocks.
   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
   if (!LastCMOV->killsRegister(X86::EFLAGS) &&
       !checkAndUpdateEFLAGSKill(LastCMOV, ThisMBB, TRI)) {
     FalseMBB->addLiveIn(X86::EFLAGS);
     SinkMBB->addLiveIn(X86::EFLAGS);
   }
 
-  // Transfer any debug instructions inside the CMOV sequence to the sunk block.
-  auto DbgEnd = MachineBasicBlock::iterator(LastCMOV);
-  auto DbgIt = MachineBasicBlock::iterator(MI);
-  while (DbgIt != DbgEnd) {
-    auto Next = std::next(DbgIt);
-    if (DbgIt->isDebugInstr())
-      SinkMBB->push_back(DbgIt->removeFromParent());
-    DbgIt = Next;
+  // Transfer any other instructions inside the CMOV sequence to the sunk block.
+  auto HarmlessEnd = MachineBasicBlock::iterator(LastCMOV);
+  auto HarmlessIt = MachineBasicBlock::iterator(MI);
+  while (HarmlessIt != HarmlessEnd) {
+    auto Next = std::next(HarmlessIt);
+    if (isHarmlessInstructionBetweenTwoCMOVPhis(HarmlessIt))
+      SinkMBB->push_back(HarmlessIt->removeFromParent());
+    HarmlessIt = Next;
   }
 
   // Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
   SinkMBB->splice(SinkMBB->end(), ThisMBB,
                   std::next(MachineBasicBlock::iterator(LastCMOV)),
                   ThisMBB->end());
   SinkMBB->transferSuccessorsAndUpdatePHIs(ThisMBB);
 

test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll

 ; I386-NOCMOV:       # %bb.0:
 ; I386-NOCMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; I386-NOCMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; I386-NOCMOV-NEXT:    addl %ecx, %eax
 ; I386-NOCMOV-NEXT:    addb {{[0-9]+}}(%esp), %cl
 ; I386-NOCMOV-NEXT:    cmpb %cl, %al
 ; I386-NOCMOV-NEXT:    jge .LBB1_2
 ; I386-NOCMOV-NEXT:  # %bb.1:
-; I386-NOCMOV-NEXT:    movl %ecx, %eax
+; I386-NOCMOV-NEXT:    movzbl %cl, %eax
 ; I386-NOCMOV-NEXT:  .LBB1_2:
 ; I386-NOCMOV-NEXT:    # kill: def $al killed $al killed $eax
 ; I386-NOCMOV-NEXT:    retl
 ;
 ; I386-CMOV-LABEL: neg_only_one_truncation:
 ; I386-CMOV:       # %bb.0:
 ; I386-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; I386-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx

 ; I686-NOCMOV:       # %bb.0:
 ; I686-NOCMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; I686-NOCMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; I686-NOCMOV-NEXT:    addl %ecx, %eax
 ; I686-NOCMOV-NEXT:    addb {{[0-9]+}}(%esp), %cl
 ; I686-NOCMOV-NEXT:    cmpb %cl, %al
 ; I686-NOCMOV-NEXT:    jge .LBB1_2
 ; I686-NOCMOV-NEXT:  # %bb.1:
-; I686-NOCMOV-NEXT:    movl %ecx, %eax
+; I686-NOCMOV-NEXT:    movzbl %cl, %eax
 ; I686-NOCMOV-NEXT:  .LBB1_2:
 ; I686-NOCMOV-NEXT:    # kill: def $al killed $al killed $eax
 ; I686-NOCMOV-NEXT:    retl
 ;
 ; I686-CMOV-LABEL: neg_only_one_truncation:
 ; I686-CMOV:       # %bb.0:
 ; I686-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; I686-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
; X86_64-NEXT:    retq
   ret i8 %t2
 }
 
 ; One value come from regs
 
 define i8 @negative_CopyFromReg(i32 %a1_wide, i32 %a2_wide_orig, i32 %inc) nounwind {
 ; I386-NOCMOV-LABEL: negative_CopyFromReg:
 ; I386-NOCMOV:       # %bb.0:
-; I386-NOCMOV-NEXT:    movb {{[0-9]+}}(%esp), %al
+; I386-NOCMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; I386-NOCMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; I386-NOCMOV-NEXT:    addl {{[0-9]+}}(%esp), %ecx
 ; I386-NOCMOV-NEXT:    cmpb %cl, %al
 ; I386-NOCMOV-NEXT:    jge .LBB3_2
 ; I386-NOCMOV-NEXT:  # %bb.1:
 ; I386-NOCMOV-NEXT:    movl %ecx, %eax
 ; I386-NOCMOV-NEXT:  .LBB3_2:
+; I386-NOCMOV-NEXT:    # kill: def $al killed $al killed $eax
 ; I386-NOCMOV-NEXT:    retl
 ;
 ; I386-CMOV-LABEL: negative_CopyFromReg:
 ; I386-CMOV:       # %bb.0:
 ; I386-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; I386-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; I386-CMOV-NEXT:    addl {{[0-9]+}}(%esp), %eax
 ; I386-CMOV-NEXT:    cmpb %al, %cl
 ; I386-CMOV-NEXT:    cmovgel %ecx, %eax
 ; I386-CMOV-NEXT:    # kill: def $al killed $al killed $eax
 ; I386-CMOV-NEXT:    retl
 ;
 ; I686-NOCMOV-LABEL: negative_CopyFromReg:
 ; I686-NOCMOV:       # %bb.0:
-; I686-NOCMOV-NEXT:    movb {{[0-9]+}}(%esp), %al
+; I686-NOCMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; I686-NOCMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; I686-NOCMOV-NEXT:    addl {{[0-9]+}}(%esp), %ecx
 ; I686-NOCMOV-NEXT:    cmpb %cl, %al
 ; I686-NOCMOV-NEXT:    jge .LBB3_2
 ; I686-NOCMOV-NEXT:  # %bb.1:
 ; I686-NOCMOV-NEXT:    movl %ecx, %eax
 ; I686-NOCMOV-NEXT:  .LBB3_2:
+; I686-NOCMOV-NEXT:    # kill: def $al killed $al killed $eax
 ; I686-NOCMOV-NEXT:    retl
 ;
 ; I686-CMOV-LABEL: negative_CopyFromReg:
 ; I686-CMOV:       # %bb.0:
 ; I686-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; I686-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; I686-CMOV-NEXT:    addl {{[0-9]+}}(%esp), %eax
 ; I686-CMOV-NEXT:    cmpb %al, %cl
; X86_64-NEXT:    retq
   ret i8 %t2
 }
 
 ; Both values come from regs
 
 define i8 @negative_CopyFromRegs(i32 %a1_wide, i32 %a2_wide) nounwind {
 ; I386-NOCMOV-LABEL: negative_CopyFromRegs:
 ; I386-NOCMOV:       # %bb.0:
-; I386-NOCMOV-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; I386-NOCMOV-NEXT:    movb {{[0-9]+}}(%esp), %al
+; I386-NOCMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; I386-NOCMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; I386-NOCMOV-NEXT:    cmpb %cl, %al
 ; I386-NOCMOV-NEXT:    jge .LBB4_2
 ; I386-NOCMOV-NEXT:  # %bb.1:
 ; I386-NOCMOV-NEXT:    movl %ecx, %eax
 ; I386-NOCMOV-NEXT:  .LBB4_2:
+; I386-NOCMOV-NEXT:    # kill: def $al killed $al killed $eax
 ; I386-NOCMOV-NEXT:    retl
 ;
 ; I386-CMOV-LABEL: negative_CopyFromRegs:
 ; I386-CMOV:       # %bb.0:
 ; I386-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; I386-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; I386-CMOV-NEXT:    cmpb %al, %cl
 ; I386-CMOV-NEXT:    cmovgel %ecx, %eax
 ; I386-CMOV-NEXT:    # kill: def $al killed $al killed $eax
 ; I386-CMOV-NEXT:    retl
 ;
 ; I686-NOCMOV-LABEL: negative_CopyFromRegs:
 ; I686-NOCMOV:       # %bb.0:
-; I686-NOCMOV-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; I686-NOCMOV-NEXT:    movb {{[0-9]+}}(%esp), %al
+; I686-NOCMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; I686-NOCMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; I686-NOCMOV-NEXT:    cmpb %cl, %al
 ; I686-NOCMOV-NEXT:    jge .LBB4_2
 ; I686-NOCMOV-NEXT:  # %bb.1:
 ; I686-NOCMOV-NEXT:    movl %ecx, %eax
 ; I686-NOCMOV-NEXT:  .LBB4_2:
+; I686-NOCMOV-NEXT:    # kill: def $al killed $al killed $eax
 ; I686-NOCMOV-NEXT:    retl
 ;
 ; I686-CMOV-LABEL: negative_CopyFromRegs:
 ; I686-CMOV:       # %bb.0:
 ; I686-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; I686-CMOV-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; I686-CMOV-NEXT:    cmpb %al, %cl
 ; I686-CMOV-NEXT:    cmovgel %ecx, %eax

test/CodeGen/X86/cmov-promotion.ll

 ; CMOV-NEXT:    movl $237, %eax
 ; CMOV-NEXT:    cmovnel %ecx, %eax
 ; CMOV-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CMOV-NEXT:    retq
 ;
 ; NO_CMOV-LABEL: cmov_zpromotion_8_to_16:
 ; NO_CMOV:       # %bb.0:
 ; NO_CMOV-NEXT:    testb $1, {{[0-9]+}}(%esp)
-; NO_CMOV-NEXT:    movb $117, %al
+; NO_CMOV-NEXT:    movl $117, %eax
 ; NO_CMOV-NEXT:    jne .LBB0_2
 ; NO_CMOV-NEXT:  # %bb.1:
-; NO_CMOV-NEXT:    movb $-19, %al
+; NO_CMOV-NEXT:    movl $237, %eax
 ; NO_CMOV-NEXT:  .LBB0_2:
-; NO_CMOV-NEXT:    movzbl %al, %eax
 ; NO_CMOV-NEXT:    # kill: def $ax killed $ax killed $eax
 ; NO_CMOV-NEXT:    retl
   %t0 = select i1 %c, i8 117, i8 -19
   %ret = zext i8 %t0 to i16
   ret i16 %ret
 }
 
 define i32 @cmov_zpromotion_8_to_32(i1 %c) {
 ; CMOV-LABEL: cmov_zpromotion_8_to_32:
 ; CMOV:       # %bb.0:
 ; CMOV-NEXT:    testb $1, %dil
 ; CMOV-NEXT:    movl $126, %ecx
 ; CMOV-NEXT:    movl $255, %eax
 ; CMOV-NEXT:    cmovnel %ecx, %eax
 ; CMOV-NEXT:    retq
 ;
 ; NO_CMOV-LABEL: cmov_zpromotion_8_to_32:
 ; NO_CMOV:       # %bb.0:
 ; NO_CMOV-NEXT:    testb $1, {{[0-9]+}}(%esp)
-; NO_CMOV-NEXT:    movb $126, %al
+; NO_CMOV-NEXT:    movl $126, %eax
 ; NO_CMOV-NEXT:    jne .LBB1_2
 ; NO_CMOV-NEXT:  # %bb.1:
-; NO_CMOV-NEXT:    movb $-1, %al
+; NO_CMOV-NEXT:    movl $255, %eax
 ; NO_CMOV-NEXT:  .LBB1_2:
-; NO_CMOV-NEXT:    movzbl %al, %eax
 ; NO_CMOV-NEXT:    retl
   %t0 = select i1 %c, i8 12414, i8 -1
   %ret = zext i8 %t0 to i32
   ret i32 %ret
 }
 
 define i64 @cmov_zpromotion_8_to_64(i1 %c) {
 ; CMOV-LABEL: cmov_zpromotion_8_to_64:
 ; CMOV:       # %bb.0:
 ; CMOV-NEXT:    testb $1, %dil
 ; CMOV-NEXT:    movl $126, %ecx
 ; CMOV-NEXT:    movl $255, %eax
 ; CMOV-NEXT:    cmovnel %ecx, %eax
 ; CMOV-NEXT:    retq
 ;
 ; NO_CMOV-LABEL: cmov_zpromotion_8_to_64:
 ; NO_CMOV:       # %bb.0:
 ; NO_CMOV-NEXT:    testb $1, {{[0-9]+}}(%esp)
-; NO_CMOV-NEXT:    movb $126, %al
+; NO_CMOV-NEXT:    movl $126, %eax
 ; NO_CMOV-NEXT:    jne .LBB2_2
 ; NO_CMOV-NEXT:  # %bb.1:
-; NO_CMOV-NEXT:    movb $-1, %al
+; NO_CMOV-NEXT:    movl $255, %eax
 ; NO_CMOV-NEXT:  .LBB2_2:
-; NO_CMOV-NEXT:    movzbl %al, %eax
 ; NO_CMOV-NEXT:    xorl %edx, %edx
 ; NO_CMOV-NEXT:    retl
   %t0 = select i1 %c, i8 12414, i8 -1
   %ret = zext i8 %t0 to i64
   ret i64 %ret
 }
 
 define i32 @cmov_zpromotion_16_to_32(i1 %c) {

 ; CMOV-NEXT:    cmovnel %eax, %ecx
 ; CMOV-NEXT:    movsbl %cl, %eax
 ; CMOV-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CMOV-NEXT:    retq
 ;
 ; NO_CMOV-LABEL: cmov_spromotion_8_to_16:
 ; NO_CMOV:       # %bb.0:
 ; NO_CMOV-NEXT:    testb $1, {{[0-9]+}}(%esp)
-; NO_CMOV-NEXT:    movb $117, %al
+; NO_CMOV-NEXT:    movl $117, %eax
 ; NO_CMOV-NEXT:    jne .LBB6_2
 ; NO_CMOV-NEXT:  # %bb.1:
-; NO_CMOV-NEXT:    movb $-19, %al
+; NO_CMOV-NEXT:    movl $237, %eax
 ; NO_CMOV-NEXT:  .LBB6_2:
 ; NO_CMOV-NEXT:    movsbl %al, %eax
 ; NO_CMOV-NEXT:    # kill: def $ax killed $ax killed $eax
 ; NO_CMOV-NEXT:    retl
   %t0 = select i1 %c, i8 117, i8 -19
   %ret = sext i8 %t0 to i16
   ret i16 %ret
 }
 
 define i32 @cmov_spromotion_8_to_32(i1 %c) {
 ; CMOV-LABEL: cmov_spromotion_8_to_32:
 ; CMOV:       # %bb.0:
 ; CMOV-NEXT:    testb $1, %dil
 ; CMOV-NEXT:    movl $126, %eax
 ; CMOV-NEXT:    movl $255, %ecx
 ; CMOV-NEXT:    cmovnel %eax, %ecx
 ; CMOV-NEXT:    movsbl %cl, %eax
 ; CMOV-NEXT:    retq
 ;
 ; NO_CMOV-LABEL: cmov_spromotion_8_to_32:
 ; NO_CMOV:       # %bb.0:
 ; NO_CMOV-NEXT:    testb $1, {{[0-9]+}}(%esp)
-; NO_CMOV-NEXT:    movb $126, %al
+; NO_CMOV-NEXT:    movl $126, %eax
 ; NO_CMOV-NEXT:    jne .LBB7_2
 ; NO_CMOV-NEXT:  # %bb.1:
-; NO_CMOV-NEXT:    movb $-1, %al
+; NO_CMOV-NEXT:    movl $255, %eax
 ; NO_CMOV-NEXT:  .LBB7_2:
 ; NO_CMOV-NEXT:    movsbl %al, %eax
 ; NO_CMOV-NEXT:    retl
   %t0 = select i1 %c, i8 12414, i8 -1
   %ret = sext i8 %t0 to i32
   ret i32 %ret
 }
 
 define i64 @cmov_spromotion_8_to_64(i1 %c) {
 ; CMOV-LABEL: cmov_spromotion_8_to_64:
 ; CMOV:       # %bb.0:
 ; CMOV-NEXT:    testb $1, %dil
 ; CMOV-NEXT:    movl $126, %eax
 ; CMOV-NEXT:    movl $255, %ecx
 ; CMOV-NEXT:    cmovnel %eax, %ecx
 ; CMOV-NEXT:    movsbq %cl, %rax
 ; CMOV-NEXT:    retq
 ;
 ; NO_CMOV-LABEL: cmov_spromotion_8_to_64:
 ; NO_CMOV:       # %bb.0:
 ; NO_CMOV-NEXT:    testb $1, {{[0-9]+}}(%esp)
-; NO_CMOV-NEXT:    movb $126, %al
+; NO_CMOV-NEXT:    movl $126, %eax
 ; NO_CMOV-NEXT:    jne .LBB8_2
 ; NO_CMOV-NEXT:  # %bb.1:
-; NO_CMOV-NEXT:    movb $-1, %al
+; NO_CMOV-NEXT:    movl $255, %eax
 ; NO_CMOV-NEXT:  .LBB8_2:
 ; NO_CMOV-NEXT:    movsbl %al, %eax
 ; NO_CMOV-NEXT:    movl %eax, %edx
 ; NO_CMOV-NEXT:    sarl $31, %edx
 ; NO_CMOV-NEXT:    retl
   %t0 = select i1 %c, i8 12414, i8 -1
   %ret = sext i8 %t0 to i64
   ret i64 %ret

test/CodeGen/X86/cmovcmov.ll

 ; CMOV-NEXT:    movb %al, {{.*}}(%rip)
 ; CMOV-NEXT:    retq
 ;
 ; NOCMOV-LABEL: no_cascade_opt:
 ; NOCMOV:       # %bb.0: # %entry
 ; NOCMOV-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; NOCMOV-NEXT:    cmpl {{[0-9]+}}(%esp), %eax
 ; NOCMOV-NEXT:    movb $20, %al
-; NOCMOV-NEXT:    movb $20, %cl
-; NOCMOV-NEXT:    jge .LBB7_1
-; NOCMOV-NEXT:  # %bb.2: # %entry
+; NOCMOV-NEXT:    jl .LBB7_2
+; NOCMOV-NEXT:  # %bb.1: # %entry
+; NOCMOV-NEXT:    movb {{[0-9]+}}(%esp), %al
+; NOCMOV-NEXT:  .LBB7_2: # %entry
+; NOCMOV-NEXT:    movzbl %al, %ecx
+; NOCMOV-NEXT:    movl $20, %eax
 ; NOCMOV-NEXT:    jle .LBB7_3
-; NOCMOV-NEXT:  .LBB7_4: # %entry
+; NOCMOV-NEXT:  # %bb.4: # %entry
 ; NOCMOV-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
 ; NOCMOV-NEXT:    jne .LBB7_5
 ; NOCMOV-NEXT:  .LBB7_6: # %entry
 ; NOCMOV-NEXT:    movb %al, g8
 ; NOCMOV-NEXT:    retl
-; NOCMOV-NEXT:  .LBB7_1: # %entry
-; NOCMOV-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; NOCMOV-NEXT:    jg .LBB7_4
 ; NOCMOV-NEXT:  .LBB7_3: # %entry
 ; NOCMOV-NEXT:    movl %ecx, %eax
 ; NOCMOV-NEXT:    cmpl $0, {{[0-9]+}}(%esp)
 ; NOCMOV-NEXT:    je .LBB7_6
 ; NOCMOV-NEXT:  .LBB7_5: # %entry
 ; NOCMOV-NEXT:    movl %ecx, %eax
 ; NOCMOV-NEXT:    movb %al, g8
 ; NOCMOV-NEXT:    retl

test/CodeGen/X86/copy-eflags.ll

 ; cross-block rewrites in at least some narrow cases.
 define void @PR37100(i8 %arg1, i16 %arg2, i64 %arg3, i8 %arg4, i8* %ptr1, i32* %ptr2, i32 %x) nounwind {
 ; X32-LABEL: PR37100:
 ; X32:       # %bb.0: # %bb
 ; X32-NEXT:    pushl %ebp
 ; X32-NEXT:    pushl %ebx
 ; X32-NEXT:    pushl %edi
 ; X32-NEXT:    pushl %esi
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %esi
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ebx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ebp
-; X32-NEXT:    movb {{[0-9]+}}(%esp), %ch
 ; X32-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; X32-NEXT:    movzbl {{[0-9]+}}(%esp), %esi
 ; X32-NEXT:    jmp .LBB3_1
 ; X32-NEXT:    .p2align 4, 0x90
-; X32-NEXT:  .LBB3_5: # %bb1
+; X32-NEXT:  .LBB3_6: # %bb1
 ; X32-NEXT:    # in Loop: Header=BB3_1 Depth=1
-; X32-NEXT:    movl %esi, %eax
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    cltd
 ; X32-NEXT:    idivl %edi
 ; X32-NEXT:  .LBB3_1: # %bb1
 ; X32-NEXT:    # =>This Inner Loop Header: Depth=1
 ; X32-NEXT:    movsbl %cl, %eax
 ; X32-NEXT:    movl %eax, %edx
 ; X32-NEXT:    sarl $31, %edx
 ; X32-NEXT:    cmpl %eax, {{[0-9]+}}(%esp)
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; X32-NEXT:    sbbl %edx, %eax
-; X32-NEXT:    setl %al
+; X32-NEXT:    setge %al
 ; X32-NEXT:    setl %dl
 ; X32-NEXT:    movzbl %dl, %edi
 ; X32-NEXT:    negl %edi
 ; X32-NEXT:    testb %al, %al
-; X32-NEXT:    jne .LBB3_3
-; X32-NEXT:  # %bb.2: # %bb1
+; X32-NEXT:    je .LBB3_2
+; X32-NEXT:  # %bb.3: # %bb1
 ; X32-NEXT:    # in Loop: Header=BB3_1 Depth=1
-; X32-NEXT:    movb %ch, %cl
-; X32-NEXT:  .LBB3_3: # %bb1
+; X32-NEXT:    movl %esi, %ecx
+; X32-NEXT:    jmp .LBB3_4
+; X32-NEXT:    .p2align 4, 0x90
+; X32-NEXT:  .LBB3_2: # in Loop: Header=BB3_1 Depth=1
+; X32-NEXT:    movzbl %cl, %ecx
+; X32-NEXT:  .LBB3_4: # %bb1
 ; X32-NEXT:    # in Loop: Header=BB3_1 Depth=1
 ; X32-NEXT:    movb %cl, (%ebp)
 ; X32-NEXT:    movl (%ebx), %edx
 ; X32-NEXT:    testb %al, %al
-; X32-NEXT:    jne .LBB3_5
-; X32-NEXT:  # %bb.4: # %bb1
+; X32-NEXT:    je .LBB3_6
+; X32-NEXT:  # %bb.5: # %bb1
 ; X32-NEXT:    # in Loop: Header=BB3_1 Depth=1
 ; X32-NEXT:    movl %edx, %edi
-; X32-NEXT:    jmp .LBB3_5
+; X32-NEXT:    jmp .LBB3_6
 ;
 ; X64-LABEL: PR37100:
 ; X64:       # %bb.0: # %bb
 ; X64-NEXT:    movq %rdx, %rsi
 ; X64-NEXT:    movl {{[0-9]+}}(%rsp), %r10d
 ; X64-NEXT:    movzbl %cl, %r11d
 ; X64-NEXT:    .p2align 4, 0x90
 ; X64-NEXT:  .LBB3_1: # %bb1

test/CodeGen/X86/fshl.ll

 
 ;
 ; Variable Funnel Shift
 ;
 
 define i8 @var_shift_i8(i8 %x, i8 %y, i8 %z) nounwind {
 ; X86-LABEL: var_shift_i8:
 ; X86:       # %bb.0:
-; X86-NEXT:    movb {{[0-9]+}}(%esp), %ah
-; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %ch
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %dl
 ; X86-NEXT:    andb $7, %dl
-; X86-NEXT:    movb %al, %ch
-; X86-NEXT:    movb %dl, %cl
-; X86-NEXT:    shlb %cl, %ch
 ; X86-NEXT:    movb $8, %cl
 ; X86-NEXT:    subb %dl, %cl
-; X86-NEXT:    shrb %cl, %ah
+; X86-NEXT:    shrb %cl, %ch
+; X86-NEXT:    movb %al, %dh
+; X86-NEXT:    movb %dl, %cl
+; X86-NEXT:    shlb %cl, %dh
 ; X86-NEXT:    testb %dl, %dl
 ; X86-NEXT:    je .LBB0_2
 ; X86-NEXT:  # %bb.1:
-; X86-NEXT:    orb %ah, %ch
-; X86-NEXT:    movb %ch, %al
+; X86-NEXT:    orb %ch, %dh
+; X86-NEXT:    movzbl %dh, %eax
 ; X86-NEXT:  .LBB0_2:
+; X86-NEXT:    # kill: def $al killed $al killed $eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: var_shift_i8:
 ; X64:       # %bb.0:
 ; X64-NEXT:    andb $7, %dl
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    movl %edx, %ecx
 ; X64-NEXT:    shlb %cl, %al

test/CodeGen/X86/fshr.ll

 
 ;
 ; Variable Funnel Shift
 ;
 
 define i8 @var_shift_i8(i8 %x, i8 %y, i8 %z) nounwind {
 ; X86-LABEL: var_shift_i8:
 ; X86:       # %bb.0:
-; X86-NEXT:    movb {{[0-9]+}}(%esp), %ah
-; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %ch
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %dl
 ; X86-NEXT:    andb $7, %dl
-; X86-NEXT:    movb %al, %ch
+; X86-NEXT:    movb %al, %dh
 ; X86-NEXT:    movb %dl, %cl
-; X86-NEXT:    shrb %cl, %ch
+; X86-NEXT:    shrb %cl, %dh
 ; X86-NEXT:    movb $8, %cl
 ; X86-NEXT:    subb %dl, %cl
-; X86-NEXT:    shlb %cl, %ah
+; X86-NEXT:    shlb %cl, %ch
 ; X86-NEXT:    testb %dl, %dl
 ; X86-NEXT:    je .LBB0_2
 ; X86-NEXT:  # %bb.1:
-; X86-NEXT:    orb %ch, %ah
-; X86-NEXT:    movb %ah, %al
+; X86-NEXT:    orb %dh, %ch
+; X86-NEXT:    movzbl %ch, %eax
 ; X86-NEXT:  .LBB0_2:
+; X86-NEXT:    # kill: def $al killed $al killed $eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: var_shift_i8:
 ; X64:       # %bb.0:
 ; X64-NEXT:    andb $7, %dl
 ; X64-NEXT:    movl %esi, %eax
 ; X64-NEXT:    movl %edx, %ecx
 ; X64-NEXT:    shrb %cl, %al

test/CodeGen/X86/midpoint-int.ll

 ; X64-NEXT:    shrb %al
 ; X64-NEXT:    # kill: def $al killed $al killed $eax
 ; X64-NEXT:    mulb %cl
 ; X64-NEXT:    addb %dil, %al
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: scalar_i8_signed_reg_reg:
 ; X32:       # %bb.0:
-; X32-NEXT:    movb {{[0-9]+}}(%esp), %ah
-; X32-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X32-NEXT:    cmpb %ah, %cl
+; X32-NEXT:    pushl %ebx
+; X32-NEXT:    pushl %esi
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ebx
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movl %eax, %ecx
+; X32-NEXT:    cmpb %bl, %al
 ; X32-NEXT:    setle %dl
-; X32-NEXT:    movb %ah, %ch
+; X32-NEXT:    movl %ebx, %esi
 ; X32-NEXT:    jg .LBB15_2
 ; X32-NEXT:  # %bb.1:
-; X32-NEXT:    movb %cl, %ch
+; X32-NEXT:    movl %eax, %ebx
 ; X32-NEXT:  .LBB15_2:
-; X32-NEXT:    movb %cl, %al
 ; X32-NEXT:    jge .LBB15_4
 ; X32-NEXT:  # %bb.3:
-; X32-NEXT:    movb %ah, %al
+; X32-NEXT:    movl %esi, %eax
 ; X32-NEXT:  .LBB15_4:
-; X32-NEXT:    subb %ch, %al
 ; X32-NEXT:    addb %dl, %dl
 ; X32-NEXT:    decb %dl
+; X32-NEXT:    subb %bl, %al
 ; X32-NEXT:    shrb %al
+; X32-NEXT:    # kill: def $al killed $al killed $eax
 ; X32-NEXT:    mulb %dl
 ; X32-NEXT:    addb %cl, %al
+; X32-NEXT:    popl %esi
+; X32-NEXT:    popl %ebx
 ; X32-NEXT:    retl
   %t3 = icmp sgt i8 %a1, %a2 ; signed
   %t4 = select i1 %t3, i8 -1, i8 1
   %t5 = select i1 %t3, i8 %a2, i8 %a1
   %t6 = select i1 %t3, i8 %a1, i8 %a2
   %t7 = sub i8 %t6, %t5
   %t8 = lshr i8 %t7, 1
   %t9 = mul nsw i8 %t8, %t4 ; signed

 ; X64-NEXT:    shrb %al
 ; X64-NEXT:    # kill: def $al killed $al killed $eax
 ; X64-NEXT:    mulb %cl
 ; X64-NEXT:    addb %dil, %al
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: scalar_i8_unsigned_reg_reg:
 ; X32:       # %bb.0:
-; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X32-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; X32-NEXT:    pushl %ebx
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X32-NEXT:    cmpb %al, %cl
 ; X32-NEXT:    setbe %dl
 ; X32-NEXT:    ja .LBB16_1
 ; X32-NEXT:  # %bb.2:
-; X32-NEXT:    movb %cl, %ah
+; X32-NEXT:    movl %ecx, %ebx
 ; X32-NEXT:    jmp .LBB16_3
 ; X32-NEXT:  .LBB16_1:
-; X32-NEXT:    movb %al, %ah
-; X32-NEXT:    movb %cl, %al
+; X32-NEXT:    movl %eax, %ebx
+; X32-NEXT:    movl %ecx, %eax
 ; X32-NEXT:  .LBB16_3:
-; X32-NEXT:    subb %ah, %al
 ; X32-NEXT:    addb %dl, %dl
 ; X32-NEXT:    decb %dl
+; X32-NEXT:    subb %bl, %al
 ; X32-NEXT:    shrb %al
+; X32-NEXT:    # kill: def $al killed $al killed $eax
 ; X32-NEXT:    mulb %dl
 ; X32-NEXT:    addb %cl, %al
+; X32-NEXT:    popl %ebx
 ; X32-NEXT:    retl
   %t3 = icmp ugt i8 %a1, %a2
   %t4 = select i1 %t3, i8 -1, i8 1
   %t5 = select i1 %t3, i8 %a2, i8 %a1
   %t6 = select i1 %t3, i8 %a1, i8 %a2
   %t7 = sub i8 %t6, %t5
   %t8 = lshr i8 %t7, 1
   %t9 = mul i8 %t8, %t4

 ; X64-NEXT:    shrb %al
 ; X64-NEXT:    # kill: def $al killed $al killed $eax
 ; X64-NEXT:    mulb %dl
 ; X64-NEXT:    addb %cl, %al
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: scalar_i8_signed_mem_reg:
 ; X32:       # %bb.0:
-; X32-NEXT:    movb {{[0-9]+}}(%esp), %ah
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    movb (%ecx), %cl
-; X32-NEXT:    cmpb %ah, %cl
+; X32-NEXT:    pushl %ebx
+; X32-NEXT:    pushl %esi
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ebx
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movzbl (%eax), %eax
+; X32-NEXT:    movl %eax, %ecx
+; X32-NEXT:    cmpb %bl, %al
 ; X32-NEXT:    setle %dl
-; X32-NEXT:    movb %ah, %ch
+; X32-NEXT:    movl %ebx, %esi
 ; X32-NEXT:    jg .LBB17_2
 ; X32-NEXT:  # %bb.1:
-; X32-NEXT:    movb %cl, %ch
+; X32-NEXT:    movl %eax, %ebx
 ; X32-NEXT:  .LBB17_2:
-; X32-NEXT:    movb %cl, %al
 ; X32-NEXT:    jge .LBB17_4
 ; X32-NEXT:  # %bb.3:
-; X32-NEXT:    movb %ah, %al
+; X32-NEXT:    movl %esi, %eax
 ; X32-NEXT:  .LBB17_4:
-; X32-NEXT:    subb %ch, %al
 ; X32-NEXT:    addb %dl, %dl
 ; X32-NEXT:    decb %dl
+; X32-NEXT:    subb %bl, %al
 ; X32-NEXT:    shrb %al
+; X32-NEXT:    # kill: def $al killed $al killed $eax
 ; X32-NEXT:    mulb %dl
 ; X32-NEXT:    addb %cl, %al
+; X32-NEXT:    popl %esi
+; X32-NEXT:    popl %ebx
 ; X32-NEXT:    retl
   %a1 = load i8, i8* %a1_addr
   %t3 = icmp sgt i8 %a1, %a2 ; signed
   %t4 = select i1 %t3, i8 -1, i8 1
   %t5 = select i1 %t3, i8 %a2, i8 %a1
   %t6 = select i1 %t3, i8 %a1, i8 %a2
   %t7 = sub i8 %t6, %t5
   %t8 = lshr i8 %t7, 1

 ; X64-NEXT:    shrb %al
 ; X64-NEXT:    # kill: def $al killed $al killed $eax
 ; X64-NEXT:    mulb %cl
 ; X64-NEXT:    addb %dil, %al
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: scalar_i8_signed_reg_mem:
 ; X32:       # %bb.0:
-; X32-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; X32-NEXT:    pushl %ebx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    movb (%eax), %ah
-; X32-NEXT:    cmpb %ah, %cl
+; X32-NEXT:    movb %al, %dh
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT:    movzbl (%ecx), %ebx
+; X32-NEXT:    cmpb %bl, %al
 ; X32-NEXT:    setle %dl
-; X32-NEXT:    movb %ah, %ch
+; X32-NEXT:    movl %ebx, %ecx
 ; X32-NEXT:    jg .LBB18_2
 ; X32-NEXT:  # %bb.1:
-; X32-NEXT:    movb %cl, %ch
+; X32-NEXT:    movl %eax, %ecx
 ; X32-NEXT:  .LBB18_2:
-; X32-NEXT:    movb %cl, %al
 ; X32-NEXT:    jge .LBB18_4
 ; X32-NEXT:  # %bb.3:
-; X32-NEXT:    movb %ah, %al
+; X32-NEXT:    movl %ebx, %eax
 ; X32-NEXT:  .LBB18_4:
-; X32-NEXT:    subb %ch, %al
 ; X32-NEXT:    addb %dl, %dl
 ; X32-NEXT:    decb %dl
+; X32-NEXT:    subb %cl, %al
 ; X32-NEXT:    shrb %al
+; X32-NEXT:    # kill: def $al killed $al killed $eax
 ; X32-NEXT:    mulb %dl
-; X32-NEXT:    addb %cl, %al
+; X32-NEXT:    addb %dh, %al
+; X32-NEXT:    popl %ebx
 ; X32-NEXT:    retl
   %a2 = load i8, i8* %a2_addr
   %t3 = icmp sgt i8 %a1, %a2 ; signed
   %t4 = select i1 %t3, i8 -1, i8 1
   %t5 = select i1 %t3, i8 %a2, i8 %a1
   %t6 = select i1 %t3, i8 %a1, i8 %a2
   %t7 = sub i8 %t6, %t5
   %t8 = lshr i8 %t7, 1

 ; X64-NEXT:    shrb %al
 ; X64-NEXT:    # kill: def $al killed $al killed $eax
 ; X64-NEXT:    mulb %dl
 ; X64-NEXT:    addb %cl, %al
 ; X64-NEXT:    retq
 ;
 ; X32-LABEL: scalar_i8_signed_mem_mem:
 ; X32:       # %bb.0:
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    pushl %ebx
 ; X32-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT:    movb (%ecx), %cl
-; X32-NEXT:    movb (%eax), %ah
-; X32-NEXT:    cmpb %ah, %cl
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    movzbl (%eax), %eax
+; X32-NEXT:    movb %al, %dh
+; X32-NEXT:    movzbl (%ecx), %ebx
+; X32-NEXT:    cmpb %bl, %al
 ; X32-NEXT:    setle %dl
-; X32-NEXT:    movb %ah, %ch
+; X32-NEXT:    movl %ebx, %ecx
 ; X32-NEXT:    jg .LBB19_2
 ; X32-NEXT:  # %bb.1:
-; X32-NEXT:    movb %cl, %ch
+; X32-NEXT:    movl %eax, %ecx
 ; X32-NEXT:  .LBB19_2:
-; X32-NEXT:    movb %cl, %al
 ; X32-NEXT:    jge .LBB19_4
 ; X32-NEXT:  # %bb.3:
-; X32-NEXT:    movb %ah, %al
+; X32-NEXT:    movl %ebx, %eax
 ; X32-NEXT:  .LBB19_4:
-; X32-NEXT:    subb %ch, %al
 ; X32-NEXT:    addb %dl, %dl
 ; X32-NEXT:    decb %dl
+; X32-NEXT:    subb %cl, %al
 ; X32-NEXT:    shrb %al
+; X32-NEXT:    # kill: def $al killed $al killed $eax
 ; X32-NEXT:    mulb %dl
-; X32-NEXT:    addb %cl, %al
+; X32-NEXT:    addb %dh, %al
+; X32-NEXT:    popl %ebx
 ; X32-NEXT:    retl
   %a1 = load i8, i8* %a1_addr
   %a2 = load i8, i8* %a2_addr
   %t3 = icmp sgt i8 %a1, %a2 ; signed
   %t4 = select i1 %t3, i8 -1, i8 1
   %t5 = select i1 %t3, i8 %a2, i8 %a1
   %t6 = select i1 %t3, i8 %a1, i8 %a2
   %t7 = sub i8 %t6, %t5
   %t8 = lshr i8 %t7, 1
   %t9 = mul nsw i8 %t8, %t4 ; signed
   %a10 = add nsw i8 %t9, %a1 ; signed
   ret i8 %a10
 }

test/CodeGen/X86/pseudo_cmov_lower.ll

-; RUN: llc < %s -mtriple=i386-linux-gnu -o - | FileCheck %s 
+; RUN: llc < %s -mtriple=i386-linux-gnu -o - | FileCheck %s
 
 ; This test checks that only a single js gets generated in the final code
 ; for lowering the CMOV pseudos that get created for this IR.
 ; CHECK-LABEL: foo1:
 ; CHECK: js
 ; CHECK-NOT: js
 define i32 @foo1(i32 %v1, i32 %v2, i32 %v3) nounwind {
 entry:

 ; get lowered into vector length number of selects, which all eventually turn
 ; into a huge number of CMOV_GR8, which are all contiguous, so the optimization
 ; kicks in as long as CMOV_GR8 is supported. I couldn't find a way to get
 ; CMOV_V*I1 pseudo-opcodes to get generated. If a way exists to get CMOV_V*1
 ; pseudo-opcodes to be generated, this test should be replaced with one that
 ; tests those opcodes.
 ;
 ; CHECK-LABEL: foo9:
-; CHECK: ja
+; CHECK-COUNT-119: ja
 ; CHECK-NOT: ja
 define void @foo9(i32 %v1,
                   <8 x i1> %v12, <8 x i1> %v13,
                   <16 x i1> %v22, <16 x i1> %v23,
                   <32 x i1> %v32, <32 x i1> %v33,
                   <64 x i1> %v42, <64 x i1> %v43,
                   i8 * %dst) nounwind {
 entry:

test/CodeGen/X86/select.ll

 ; MCU:       # %bb.0:
 ; MCU-NEXT:    cmpl $127, %eax
 ; MCU-NEXT:    movl $127, %ecx
 ; MCU-NEXT:    jg .LBB21_2
 ; MCU-NEXT:  # %bb.1:
 ; MCU-NEXT:    movl %eax, %ecx
 ; MCU-NEXT:  .LBB21_2:
 ; MCU-NEXT:    cmpl $-128, %ecx
-; MCU-NEXT:    movb $-128, %al
+; MCU-NEXT:    movl $128, %eax
 ; MCU-NEXT:    jl .LBB21_4
 ; MCU-NEXT:  # %bb.3:
 ; MCU-NEXT:    movl %ecx, %eax
 ; MCU-NEXT:  .LBB21_4:
 ; MCU-NEXT:    movb %al, (%edx)
 ; MCU-NEXT:    retl
   %cmp = icmp sgt i32 %src, 127
   %sel1 = select i1 %cmp, i32 127, i32 %src