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RegBankSelect: Allow targets to introduce control flow for mapping
ClosedPublic

Authored by arsenm on Feb 19 2019, 1:11 PM.

Details

Reviewers
qcolombet
Summary

For AMDGPU, if an operand requires an SGPR but is only available as a
VGPR, a loop needs to be introduced until to execute the instruction
with each unique combination of values across all lanes. The rest of
the instructions in the block will be moved to a new block following
the loop. Check if the next instruction's parent changed, and update
the iterators and insertion block if this happened.

Tests will be included in a future patch.

Diff Detail

Event Timeline

arsenm created this revision.Feb 19 2019, 1:11 PM
qcolombet accepted this revision.Feb 19 2019, 3:24 PM

Nice catch!

LGTM. Question below.

lib/CodeGen/GlobalISel/RegBankSelect.cpp
709

Does this potentially breaks the iterators of RPOT?

This revision is now accepted and ready to land.Feb 19 2019, 3:24 PM
arsenm marked an inline comment as done.Feb 19 2019, 3:48 PM
arsenm added inline comments.
lib/CodeGen/GlobalISel/RegBankSelect.cpp
709

No, it builds a complete vector ahead of time. The newly created blocks aren’t visited but I don’t need them to be

qcolombet added inline comments.Feb 19 2019, 4:33 PM
lib/CodeGen/GlobalISel/RegBankSelect.cpp
709

Thanks for double checking!

arsenm closed this revision.Feb 21 2019, 7:47 AM

r354591