[SystemZ] Make sure VEXTEND and VROUND nodes are not emitted without vector support.

[jonpa]

Summary

Building the testsuite with the generic target (z10) revealed missing checks for vector support in combineFP_ROUND() and combineFP_EXTEND().

[uweigand]

Ah, good catch! LGTM.

[jonpa]

r354039.

[thegameg]

This failed to pass the machine verifier in http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-expensive/13579/.

It can be reproduced by adding -verify-machineinstrs to the llc invocation in test/CodeGen/SystemZ/fp-conv-18.mir.

I reverted this in rL354096.

Thanks!

lib/Target/SystemZ/SystemZISelLowering.cpp

SDValue SystemZTargetLowering::combineJOIN_DWORDS(
   if (N->getOperand(0) == N->getOperand(1))
     return DAG.getNode(SystemZISD::REPLICATE, SDLoc(N), N->getValueType(0),
                        N->getOperand(0));
   return SDValue();
 }
 
 SDValue SystemZTargetLowering::combineFP_ROUND(
     SDNode *N, DAGCombinerInfo &DCI) const {
+
+  if (!Subtarget.hasVector())
+    return SDValue();
+
   // (fpround (extract_vector_elt X 0))
   // (fpround (extract_vector_elt X 1)) ->
   // (extract_vector_elt (VROUND X) 0)
   // (extract_vector_elt (VROUND X) 2)
   //
   // This is a special case since the target doesn't really support v2f32s.
   SelectionDAG &DAG = DCI.DAG;
   SDValue Op0 = N->getOperand(0);
for (auto *U : Vec->uses()) {
       }
     }
   }
   return SDValue();
 }
 
 SDValue SystemZTargetLowering::combineFP_EXTEND(
     SDNode *N, DAGCombinerInfo &DCI) const {
+
+  if (!Subtarget.hasVector())
+    return SDValue();
+
   // (fpextend (extract_vector_elt X 0))
   // (fpextend (extract_vector_elt X 2)) ->
   // (extract_vector_elt (VEXTEND X) 0)
   // (extract_vector_elt (VEXTEND X) 1)
   //
   // This is a special case since the target doesn't really support v2f32s.
   SelectionDAG &DAG = DCI.DAG;
   SDValue Op0 = N->getOperand(0);

test/CodeGen/SystemZ/fp-conv-18.mir

+# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z10 -start-before=codegenprepare %s \
+# RUN: -o - | FileCheck %s
+
+# Test that VEXTEND or VROUND nodes are not emitted without vector support.
+
+--- |
+  
+  @.str = external dso_local unnamed_addr constant [21 x i8], align 2
+  
+  define void @fun1() #0 {
+  bb:
+    %tmp = load <4 x float>, <4 x float>* undef, align 16
+    %tmp1 = extractelement <4 x float> %tmp, i32 0
+    %tmp2 = fpext float %tmp1 to double
+    %tmp3 = extractelement <4 x float> %tmp, i32 2
+    %tmp4 = fpext float %tmp3 to double
+    tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([21 x i8], [21 x i8]* @.str, i64 0, i64 0), double %tmp2, double undef, double %tmp4, double undef)
+    ret void
+  }
+  
+  define void @fun2() #0 {
+  bb:
+    %tmp = load <2 x double>, <2 x double>* undef, align 16
+    %tmp1 = extractelement <2 x double> %tmp, i32 0
+    %tmp2 = fptrunc double %tmp1 to float
+    %tmp3 = extractelement <2 x double> %tmp, i32 1
+    %tmp4 = fptrunc double %tmp3 to float
+    tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([21 x i8], [21 x i8]* @.str, i64 0, i64 0), float %tmp2, float undef, float %tmp4, float undef)
+    ret void
+  }
+  
+  declare dso_local void @printf(i8*, ...) #0
+  
+...
+
+# CHECK-LABEL: fun1:
+# CHECK: ldeb
+# CHECK-LABEL: fun2:
+# CHECK: ledbr
+
+---
+name:            fun1
+alignment:       4
+tracksRegLiveness: true
+...
+---
+name:            fun2
+alignment:       4
+tracksRegLiveness: true
+...