[mips] Avoid redudant store when generating code for ExtractElementF64 nodes

[vkalintiris]

Summary

Depends on D5753

[dsanders]

I'm afraid I don't think this patch on the right track. The problem isn't related to which element is extracted, it's that we don't optimize the code after expanding expandExtractElementF64() for both elements. With this patch it will be possible for pre-RA scheduling to cause invalid code by reordering the ExtractElementF64 nodes.

One fairly simple solution I can think of is using DAGCombine to merge both ExtractElementF64's into a single node, then expanding that node such that it only spills once.

lib/Target/Mips/MipsSEFrameLowering.cpp

const MipsSEInstrInfo &TII = *static_cast<const MipsSEInstrInfo *>(
                                      TM.getSubtargetImpl()->getInstrInfo());
     const MipsRegisterInfo &TRI = *static_cast<const MipsRegisterInfo *>(
                                       TM.getSubtargetImpl()->getRegisterInfo());
 
     unsigned DstReg = I->getOperand(0).getReg();
     unsigned SrcReg = I->getOperand(1).getReg();
     unsigned N = I->getOperand(2).getImm();
     int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 - N));
+    // We should store the source register to the stack only when we are
+    // extracting the first element of the pair (which is endianness-dependent)
+    // For the other element of pair the source register will be already saved
+    // on the stack.
+    bool ShouldStoreSrcReg = (Subtarget.isLittle()  && N == 0) ||
+                             (!Subtarget.isLittle() && N == 1);
 
     // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
     // the cases where mfhc1 is not available). 64-bit architectures and
     // MIPS32r2 or later can use FGR64 though.
     assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
            !Subtarget.isFP64bit());
 
     const TargetRegisterClass *RC =
         FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
     const TargetRegisterClass *RC2 = &Mips::GPR32RegClass;
 
     // We re-use the same spill slot each time so that the stack frame doesn't
     // grow too much in functions with a large number of moves.
     int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC);
-    TII.storeRegToStack(MBB, I, SrcReg, I->getOperand(1).isKill(), FI, RC, &TRI,
-                        0);
+
+    if (ShouldStoreSrcReg) {
+      TII.storeRegToStack(MBB, I, SrcReg, I->getOperand(1).isKill(),
+                          FI, RC, &TRI, 0);
+    }
     TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, Offset);
     return true;
   }
 
   return false;
 }
 
 MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI)

test/CodeGen/Mips/fp64a.ll

 ; 32R2-NO-FP64A-LE-DAG: mfhc1   $7, $f0
 
 ; 32R2-NO-FP64A-BE-DAG: mfc1    $7, $f0
 ; 32R2-NO-FP64A-BE-DAG: mfhc1   $6, $f0
 
 ; 32R2-FP64A:           addiu   $sp, $sp, -32
 ; 32R2-FP64A:           sdc1    $f0, 16($sp)
 ; 32R2-FP64A:           lw      $6, 16($sp)
-; FIXME: This store is redundant
-; 32R2-FP64A:           sdc1    $f0, 16($sp)
 ; 32R2-FP64A:           lw      $7, 20($sp)
 
 ; 64-NO-FP64A:          mov.d   $f13, $f0
 }

test/CodeGen/Mips/fpxx.ll

 ; ALL-LABEL:   move_from1:
 
 ; 32-NOFPXX-DAG:   mfc1    $6, $f0
 ; 32-NOFPXX-DAG:   mfc1    $7, $f1
 
 ; 32-FPXX:         addiu   $sp, $sp, -32
 ; 32-FPXX:         sdc1    $f0, 16($sp)
 ; 32-FPXX:         lw      $6, 16($sp)
-; FIXME: This store is redundant
-; 32-FPXX:         sdc1    $f0, 16($sp)
 ; 32-FPXX:         lw      $7, 20($sp)
 
 ; 32R2-NOFPXX-DAG: mfc1    $6, $f0
 ; 32R2-NOFPXX-DAG: mfhc1   $7, $f0
 
 ; 32R2-FPXX-DAG:   mfc1    $6, $f0
 ; 32R2-FPXX-DAG:   mfhc1   $7, $f0