[SystemZ] Implement SystemZOperand::print()

[jonpa]

Summary

I tried compiling a file with "-mllvm -debug", and found that this caused a crash, since there was an unimplemented function in SystemZAsmParser.

I have tried to implement this to make a readable output which basically means trying to print the values of the operands by casting them to the right MCExpr subclass.

I tried to print register names but did not find a trivial way to get the MachineRegisterInfo. Now register integer values are printed instead.

[uweigand]

I tried to print register names but did not find a trivial way to get the MachineRegisterInfo. Now register integer values are printed instead.

You should be using SystemZInstPrinter::getRegisterName, see e.g. how X86Operand::print is implemented.

Also, I think it should be straightforward to also print memory operands correctly.

[jonpa]

OK - now also print registers by name and memory operands.

• Copied the output style from X86, with 'Imm:', 'Reg:', etc.
• Could not think of an instruction with a ImmTLS with a non-null Sym for the test.
• Removed the printing of '?' I tried before and instead print nothing. I found it confusing...

[jonpa]

Fix whitespace errors in test case.

[uweigand]

See inline comment. Otherwise LGTM.

lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

684

Index should also be printed *before* the base.

test/MC/SystemZ/asm-match.s

30

Should be r2, r3 ... see above

[jonpa]

Thanks for review.
Committed as r345349.

test/MC/SystemZ/asm-match.s

30

Oops...

lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
+#include "InstPrinter/SystemZInstPrinter.h"
 #include "MCTargetDesc/SystemZMCTargetDesc.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstBuilder.h"
const MCExpr *getImm() const {
     return Imm;
   }
 
   // Immediate operands with optional TLS symbol.
   bool isImmTLS() const {
     return Kind == KindImmTLS;
   }
 
+  const ImmTLSOp getImmTLS() const {
+    assert(Kind == KindImmTLS && "Not a TLS immediate");
+    return ImmTLS;
+  }
+
   // Memory operands.
   bool isMem() const override {
     return Kind == KindMem;
   }
   bool isMem(MemoryKind MemKind) const {
     return (Kind == KindMem &&
             (Mem.MemKind == MemKind ||
              // A BDMem can be treated as a BDXMem in which the index
public:
   }
   bool isMemDisp12Len4(RegisterKind RegKind) const {
     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10);
   }
   bool isMemDisp12Len8(RegisterKind RegKind) const {
     return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100);
   }
 
+  const MemOp& getMem() const {
+    assert(Kind == KindMem && "Not a Mem operand");
+    return Mem;
+  }
+
   // Override MCParsedAsmOperand.
   SMLoc getStartLoc() const override { return StartLoc; }
   SMLoc getEndLoc() const override { return EndLoc; }
   void print(raw_ostream &OS) const override;
 
   /// getLocRange - Get the range between the first and last token of this
   /// operand.
   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
static struct InsnMatchEntry InsnMatchTable[] = {
   { "ss", SystemZ::InsnSS, 4,
     { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } },
   { "sse", SystemZ::InsnSSE, 3,
     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } },
   { "ssf", SystemZ::InsnSSF, 4,
     { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }
 };
 
+static void printMCExpr(const MCExpr *E, raw_ostream &OS) {
+  if (!E)
+    return;
+  if (auto *CE = dyn_cast<MCConstantExpr>(E))
+    OS << *CE;
+  else if (auto *UE = dyn_cast<MCUnaryExpr>(E))
+    OS << *UE;
+  else if (auto *BE = dyn_cast<MCBinaryExpr>(E))
+    OS << *BE;
+  else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E))
+    OS << *SRE;
+  else
+    OS << *E;
+}
+
 void SystemZOperand::print(raw_ostream &OS) const {
-  llvm_unreachable("Not implemented");
+  switch (Kind) {
+    break;
+  case KindToken:
+    OS << "Token:" << getToken();
+    break;
+  case KindReg:
+    OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg());
+    break;
+  case KindImm:
+    OS << "Imm:";
+    printMCExpr(getImm(), OS);
+    break;
+  case KindImmTLS:
+    OS << "ImmTLS:";
+    printMCExpr(getImmTLS().Imm, OS);
+    if (getImmTLS().Sym) {
+      OS << ", ";
+      printMCExpr(getImmTLS().Sym, OS);
+    }
+    break;
+  case KindMem: {
+    const MemOp &Op = getMem();
+    OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp);
+    if (Op.Base) {
+      OS << "(";
+      if (Op.MemKind == BDLMem)
+        OS << *cast<MCConstantExpr>(Op.Length.Imm) << ",";
+      else if (Op.MemKind == BDRMem)
+        OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ",";
+      OS << SystemZInstPrinter::getRegisterName(Op.Base);
+      if (Op.Index)
+        OS << "," << SystemZInstPrinter::getRegisterName(Op.Index);
+      OS << ")";
+    }
+    break;
+  }
+  default:
+  case KindInvalid:
+    break;
+  }
 }
 
 // Parse one register of the form %<prefix><number>.
 bool SystemZAsmParser::parseRegister(Register &Reg) {
   Reg.StartLoc = Parser.getTok().getLoc();
 
   // Eat the % prefix.
   if (Parser.getTok().isNot(AsmToken::Percent))

test/MC/SystemZ/asm-match.s

+// REQUIRES: asserts
+// RUN: llvm-mc -triple s390x-linux-gnu -debug-only=asm-matcher %s 2>&1 | FileCheck %s
+//
+// Check that debug output prints the operands correctly.
+
+// CHECK: AsmMatcher: found 1 encodings with mnemonic 'sllg'
+// CHECK: Trying to match opcode SLLG
+// CHECK: Matching formal operand class MCK_GR64 against actual operand at index 1 (Reg:r3): match success using generic matcher
+// CHECK: Matching formal operand class MCK_GR64 against actual operand at index 2 (Reg:r0): match success using generic matcher
+// CHECK: Matching formal operand class MCK_BDAddr32Disp20 against actual operand at index 3 (Mem:3): match success using generic matcher
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 1 encodings with mnemonic 'llill'
+// CHECK: Trying to match opcode LLILL
+// CHECK: Matching formal operand class MCK_GR64 against actual operand at index 1 (Reg:r0): match success using generic matcher
+// CHECK: Matching formal operand class MCK_U16Imm against actual operand at index 2 (Imm:0): match success using generic matcher
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 1 encodings with mnemonic 'lgr'
+// CHECK: Trying to match opcode LGR
+// CHECK: Matching formal operand class MCK_GR64 against actual operand at index 1 (Reg:r1): match success using generic matcher
+// CHECK: Matching formal operand class MCK_GR64 against actual operand at index 2 (Reg:r0): match success using generic matcher
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 1 encodings with mnemonic 'lg'
+// CHECK: Trying to match opcode LG
+// CHECK: Matching formal operand class MCK_GR64 against actual operand at index 1 (Reg:r1): match success using generic matcher
+// CHECK: Matching formal operand class MCK_BDXAddr64Disp20 against actual operand at index 2 (Mem:16(r2)): match success using generic matcher
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 1 encodings with mnemonic 'lg'
+// CHECK: Trying to match opcode LG
+// CHECK: Matching formal operand class MCK_GR64 against actual operand at index 1 (Reg:r1): match success using generic matcher
+// CHECK: Matching formal operand class MCK_BDXAddr64Disp20 against actual operand at index 2 (Mem:16(r3,r2)): match success using generic matcher
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 1 encodings with mnemonic 'stmg'
+// CHECK: Trying to match opcode STMG
+// CHECK: Matching formal operand class MCK_GR64 against actual operand at index 1 (Reg:r13): match success using generic matcher
+// CHECK: Matching formal operand class MCK_GR64 against actual operand at index 2 (Reg:r15): match success using generic matcher
+// CHECK: Matching formal operand class MCK_BDAddr64Disp20 against actual operand at index 3 (Mem:104(r15)): match success using generic matcher
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 1 encodings with mnemonic 'mvc'
+// CHECK: Trying to match opcode MVC
+// CHECK: Matching formal operand class MCK_BDLAddr64Disp12Len8 against actual operand at index 1 (Mem:184(8,r15)): match success using generic matcher
+// CHECK: Matching formal operand class MCK_BDAddr64Disp12 against actual operand at index 2 (Mem:8(r2)): match success using generic matcher
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 1 encodings with mnemonic 'mvck'
+// CHECK: Trying to match opcode MVCK
+// CHECK: Matching formal operand class MCK_BDRAddr64Disp12 against actual operand at index 1 (Mem:0(r0,r1)): match success using generic matcher
+// CHECK: Matching formal operand class MCK_BDAddr64Disp12 against actual operand at index 2 (Mem:4095(r15)): match success using generic matcher
+// CHECK: Matching formal operand class MCK_GR64 against actual operand at index 3 (Reg:r2): match success using generic matcher
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 1 encodings with mnemonic 'j'
+// CHECK: Trying to match opcode J
+// CHECK: Matching formal operand class MCK_PCRel16 against actual operand at index 1 (Imm:.Ltmp0+2): match success using generic matcher
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 2: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 1 encodings with mnemonic 'brasl'
+// CHECK: Trying to match opcode BRASL
+// CHECK: Matching formal operand class MCK_GR64 against actual operand at index 1 (Reg:r14): match success using generic matcher
+// CHECK: Matching formal operand class MCK_PCRelTLS32 against actual operand at index 2 (ImmTLS:fun): match success using generic matcher
+// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: .text
+// CHECK: sllg  %r3, %r0, 3
+// CHECK: llill %r0, 0
+// CHECK: lgr %r1, %r0
+// CHECK: lg  %r1, 16(%r2)
+// CHECK: lg  %r1, 16(%r2,%r3)
+// CHECK: stmg  %r13, %r15, 104(%r15)
+// CHECK: mvc 184(8,%r15), 8(%r2)
+// CHECK: mvck  0(%r0,%r1), 4095(%r15), %r2
+// CHECK: .Ltmp0:
+// CHECK: j .Ltmp0+2
+// CHECK: brasl %r14, fun
+  
+        sllg    %r3, %r0, 3 
+        llill %r0, 0
+        lgr %r1, %r0
+        lg      %r1, 16(%r2)
+        lg      %r1, 16(%r2,%r3)
+        stmg    %r13, %r15, 104(%r15)
+        mvc     184(8,%r15), 8(%r2)
+        mvck    0(%r0,%r1), 4095(%r15), %r2
+.Ltmp0:
+        j .Ltmp0+2
+        brasl   %r14, fun