Avoid generating FGETSIGN for f16

[scanon]

Summary

Current SimplifyDemandedBits attempts to generate FGETSIGN from a bitcast of f16->i16 that only wants the signbit. That on its own is fine, except that we end up producing a bad shift node downstream. If we fix *that*, we'll run into issues legalizing the FGETSIGN in such a way that we don't end up right back with a bitcast followed by a shift, which is what we started with.

So. Instead simply skip out if we have a f16, which is the same thing we do for f128. This maybe isn't ideal, but it fixes the immediate problem (a crash) and a long-term right fix is somewhat non-obvious, so this will do fine.

https://bugs.llvm.org/show_bug.cgi?id=38038

[ab]

LGTM. Not the biggest fan of CodeGen/Generic tests, but it gets the job done, I suppose ;) I wouldn't be surprised if it failed on some target that can't even handle half parameters, so you might want to load it instead, put it in x86, or wait and see - your pick.

[scanon]

In D49524#1168723, @ab wrote:

I wouldn't be surprised if it failed on some target that can't even handle half parameters

This is a good point. I'll fix this somehow before committing.

lib/CodeGen/SelectionDAG/TargetLowering.cpp

case ISD::BITCAST:
     // thing demanded, turn this into a FGETSIGN.
     if (!TLO.LegalOperations() && !VT.isVector() &&
         !Op.getOperand(0).getValueType().isVector() &&
         NewMask == APInt::getSignMask(Op.getValueSizeInBits()) &&
         Op.getOperand(0).getValueType().isFloatingPoint()) {
       bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT);
       bool i32Legal  = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
       if ((OpVTLegal || i32Legal) && VT.isSimple() &&
+           Op.getOperand(0).getValueType() != MVT::f16 &&
            Op.getOperand(0).getValueType() != MVT::f128) {
         // Cannot eliminate/lower SHL for f128 yet.
         EVT Ty = OpVTLegal ? VT : MVT::i32;
         // Make a FGETSIGN + SHL to move the sign bit into the appropriate
         // place.  We expect the SHL to be eliminated by other optimizations.
         SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
         unsigned OpVTSizeInBits = Op.getValueSizeInBits();
         if (!OpVTLegal && OpVTSizeInBits > 32)

test/CodeGen/Generic/pr38038.ll

+; RUN: llc < %s
+; PR38038
+
+define i8 @crash(half)  {
+entry:
+  %1 = bitcast half %0 to i16
+  %.lobit = lshr i16 %1, 15
+  %2 = trunc i16 %.lobit to i8
+  ret i8 %2
+}