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Differential D48822

[X86] Fast-isel tests for lowered truncation intrinsics
ClosedPublic

Authored by mike.dvoretsky on Jul 2 2018, 2:28 AM.

Details

Reviewers
craig.topper
RKSimon
Commits
rG89c919c20b59: [X86] Fast-isel tests for lowered truncation intrinsics
rL336645: [X86] Fast-isel tests for lowered truncation intrinsics
Summary

This patch adds fast-isel tests for the IR patterns produced for truncation intrinsics in D48712.

Diff Detail

Repository
rL LLVM

Event Timeline

mike.dvoretsky created this revision.Jul 2 2018, 2:28 AM
Herald added a subscriber: llvm-commits. · View Herald TranscriptJul 2 2018, 2:28 AM
mike.dvoretsky mentioned this in D48712: [X86] Lowering integer truncation intrinsics to native IR.Jul 2 2018, 2:31 AM
RKSimon accepted this revision.Jul 2 2018, 6:39 AM

LGTM with one minor - thanks

llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll
3144 ↗(On Diff #153687)

You should be able to drop the "local_unnamed_addr #0" tag

This revision is now accepted and ready to land.Jul 2 2018, 6:39 AM
Closed by commit rL336645: [X86] Fast-isel tests for lowered truncation intrinsics (authored by mike.dvoretsky). · Explain WhyJul 10 2018, 1:31 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
test/
CodeGen/
X86/
13 lines
102 lines

Diff 154767

llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics-fast-isel.ll

Show First 20 Lines • Show All 727 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%arg0 = bitcast i16 %a0 to <16 x i1> %arg0 = bitcast i16 %a0 to <16 x i1>
%arg1 = bitcast <2 x i64> %a1 to <8 x i16> %arg1 = bitcast <2 x i64> %a1 to <8 x i16>
%res0 = shufflevector <8 x i16> %arg1, <8 x i16> undef, <16 x i32> zeroinitializer %res0 = shufflevector <8 x i16> %arg1, <8 x i16> undef, <16 x i32> zeroinitializer
%res1 = select <16 x i1> %arg0, <16 x i16> %res0, <16 x i16> zeroinitializer %res1 = select <16 x i1> %arg0, <16 x i16> %res0, <16 x i16> zeroinitializer
%res2 = bitcast <16 x i16> %res1 to <4 x i64> %res2 = bitcast <16 x i16> %res1 to <4 x i64>
ret <4 x i64> %res2 ret <4 x i64> %res2
} }
define <2 x i64> @test_mm_cvtepi16_epi8(<2 x i64> %__A) {
; CHECK-LABEL: test_mm_cvtepi16_epi8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: ret{{[l|q]}}
entry:
%0 = bitcast <2 x i64> %__A to <8 x i16>
%conv.i = trunc <8 x i16> %0 to <8 x i8>
%shuf.i = shufflevector <8 x i8> %conv.i, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%1 = bitcast <16 x i8> %shuf.i to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @test_mm256_cvtepi16_epi8(<4 x i64> %__A) { define <2 x i64> @test_mm256_cvtepi16_epi8(<4 x i64> %__A) {
; CHECK-LABEL: test_mm256_cvtepi16_epi8: ; CHECK-LABEL: test_mm256_cvtepi16_epi8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpmovwb %ymm0, %xmm0 ; CHECK-NEXT: vpmovwb %ymm0, %xmm0
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: ret{{[l|q]}} ; CHECK-NEXT: ret{{[l|q]}}
entry: entry:
%0 = bitcast <4 x i64> %__A to <16 x i16> %0 = bitcast <4 x i64> %__A to <16 x i16>
▲ Show 20 Lines • Show All 230 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,135 Lines • ▼ Show 20 Linesentry:
%tmp1 = and <2 x i64> %__Y, <i64 4294967295, i64 4294967295> %tmp1 = and <2 x i64> %__Y, <i64 4294967295, i64 4294967295>
%tmp2 = mul nuw <2 x i64> %tmp1, %tmp %tmp2 = mul nuw <2 x i64> %tmp1, %tmp
%tmp3 = bitcast i8 %__M to <8 x i1> %tmp3 = bitcast i8 %__M to <8 x i1>
%extract.i = shufflevector <8 x i1> %tmp3, <8 x i1> undef, <2 x i32> <i32 0, i32 1> %extract.i = shufflevector <8 x i1> %tmp3, <8 x i1> undef, <2 x i32> <i32 0, i32 1>
%tmp4 = select <2 x i1> %extract.i, <2 x i64> %tmp2, <2 x i64> zeroinitializer %tmp4 = select <2 x i1> %extract.i, <2 x i64> %tmp2, <2 x i64> zeroinitializer
ret <2 x i64> %tmp4 ret <2 x i64> %tmp4
} }
define <2 x i64> @test_mm_cvtepi32_epi8(<2 x i64> %__A) {
; CHECK-LABEL: test_mm_cvtepi32_epi8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,8,12],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: ret{{[l|q]}}
entry:
%0 = bitcast <2 x i64> %__A to <4 x i32>
%conv.i = trunc <4 x i32> %0 to <4 x i8>
%shuf.i = shufflevector <4 x i8> %conv.i, <4 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
%1 = bitcast <16 x i8> %shuf.i to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @test_mm_cvtepi32_epi16(<2 x i64> %__A) {
; CHECK-LABEL: test_mm_cvtepi32_epi16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: ret{{[l|q]}}
entry:
%0 = bitcast <2 x i64> %__A to <4 x i32>
%conv.i = trunc <4 x i32> %0 to <4 x i16>
%shuf.i = shufflevector <4 x i16> %conv.i, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%1 = bitcast <8 x i16> %shuf.i to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @test_mm_cvtepi64_epi8(<2 x i64> %__A) {
; CHECK-LABEL: test_mm_cvtepi64_epi8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,8],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: ret{{[l|q]}}
entry:
%conv.i = trunc <2 x i64> %__A to <2 x i8>
%shuf.i = shufflevector <2 x i8> %conv.i, <2 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
%0 = bitcast <16 x i8> %shuf.i to <2 x i64>
ret <2 x i64> %0
}
define <2 x i64> @test_mm_cvtepi64_epi16(<2 x i64> %__A) {
; CHECK-LABEL: test_mm_cvtepi64_epi16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,8,9],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT: ret{{[l|q]}}
entry:
%conv.i = trunc <2 x i64> %__A to <2 x i16>
%shuf.i = shufflevector <2 x i16> %conv.i, <2 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
%0 = bitcast <8 x i16> %shuf.i to <2 x i64>
ret <2 x i64> %0
}
define <2 x i64> @test_mm_cvtepi64_epi32(<2 x i64> %__A) {
; CHECK-LABEL: test_mm_cvtepi64_epi32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,2],zero,zero
; CHECK-NEXT: ret{{[l|q]}}
entry:
%conv.i = trunc <2 x i64> %__A to <2 x i32>
%shuf.i = shufflevector <2 x i32> %conv.i, <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%0 = bitcast <4 x i32> %shuf.i to <2 x i64>
ret <2 x i64> %0
}
define <2 x i64> @test_mm256_cvtepi32_epi16(<4 x i64> %__A) local_unnamed_addr #0 { define <2 x i64> @test_mm256_cvtepi32_epi16(<4 x i64> %__A) local_unnamed_addr #0 {
; CHECK-LABEL: test_mm256_cvtepi32_epi16: ; CHECK-LABEL: test_mm256_cvtepi32_epi16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpmovdw %ymm0, %xmm0 ; CHECK-NEXT: vpmovdw %ymm0, %xmm0
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: ret{{[l|q]}} ; CHECK-NEXT: ret{{[l|q]}}
entry: entry:
%0 = bitcast <4 x i64> %__A to <8 x i32> %0 = bitcast <4 x i64> %__A to <8 x i32>
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Linesentry:
%conv.i.i = trunc <4 x i64> %__A to <4 x i32> %conv.i.i = trunc <4 x i64> %__A to <4 x i32>
%0 = bitcast i8 %__M to <8 x i1> %0 = bitcast i8 %__M to <8 x i1>
%extract.i = shufflevector <8 x i1> %0, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract.i = shufflevector <8 x i1> %0, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%1 = select <4 x i1> %extract.i, <4 x i32> %conv.i.i, <4 x i32> zeroinitializer %1 = select <4 x i1> %extract.i, <4 x i32> %conv.i.i, <4 x i32> zeroinitializer
%2 = bitcast <4 x i32> %1 to <2 x i64> %2 = bitcast <4 x i32> %1 to <2 x i64>
ret <2 x i64> %2 ret <2 x i64> %2
} }
define <2 x i64> @test_mm256_cvtepi64_epi8(<4 x i64> %__A) {
; CHECK-LABEL: test_mm256_cvtepi64_epi8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpmovqb %ymm0, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: ret{{[l|q]}}
entry:
%conv.i = trunc <4 x i64> %__A to <4 x i8>
%shuf.i = shufflevector <4 x i8> %conv.i, <4 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
%0 = bitcast <16 x i8> %shuf.i to <2 x i64>
ret <2 x i64> %0
}
define <2 x i64> @test_mm256_cvtepi64_epi16(<4 x i64> %__A) {
; CHECK-LABEL: test_mm256_cvtepi64_epi16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpmovqw %ymm0, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: ret{{[l|q]}}
entry:
%conv.i = trunc <4 x i64> %__A to <4 x i16>
%shuf.i = shufflevector <4 x i16> %conv.i, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%0 = bitcast <8 x i16> %shuf.i to <2 x i64>
ret <2 x i64> %0
}
define <2 x i64> @test_mm256_cvtepi32_epi8(<4 x i64> %__A) {
; CHECK-LABEL: test_mm256_cvtepi32_epi8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpmovdb %ymm0, %xmm0
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: ret{{[l|q]}}
entry:
%0 = bitcast <4 x i64> %__A to <8 x i32>
%conv.i = trunc <8 x i32> %0 to <8 x i8>
%shuf.i = shufflevector <8 x i8> %conv.i, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%1 = bitcast <16 x i8> %shuf.i to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @test_mm_ternarylogic_epi32(<2 x i64> %__A, <2 x i64> %__B, <2 x i64> %__C) { define <2 x i64> @test_mm_ternarylogic_epi32(<2 x i64> %__A, <2 x i64> %__B, <2 x i64> %__C) {
; CHECK-LABEL: test_mm_ternarylogic_epi32: ; CHECK-LABEL: test_mm_ternarylogic_epi32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpternlogd $4, %xmm2, %xmm1, %xmm0 ; CHECK-NEXT: vpternlogd $4, %xmm2, %xmm1, %xmm0
; CHECK-NEXT: ret{{[l|q]}} ; CHECK-NEXT: ret{{[l|q]}}
entry: entry:
%0 = bitcast <2 x i64> %__A to <4 x i32> %0 = bitcast <2 x i64> %__A to <4 x i32>
%1 = bitcast <2 x i64> %__B to <4 x i32> %1 = bitcast <2 x i64> %__B to <4 x i32>
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