Remove SETCCE use from Lanai's backend

[deadalnix]

Summary

This creates a small perf regression, but after talking with Jacques Pienaar, he was good with it to get things moving toward removng SETCCE.

[jpienaar]

Looks good and as discussed the regression will be addressed by using carry.

The changes in LanaiAluCode.h seem unrelated, is that change needed for this too?

[deadalnix]

The change in LanaiAluCode.h are indeed unrelated, let me remove them.

[deadalnix]

Revert changes in LanaiAluCode.h

llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h

public:
   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
-  SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 
   unsigned getRegisterByName(const char *RegName, EVT VT,
                              SelectionDAG &DAG) const override;
   std::pair<unsigned, const TargetRegisterClass *>
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,

llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp

LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
   computeRegisterProperties(TRI);
 
   setStackPointerRegisterToSaveRestore(Lanai::SP);
 
   setOperationAction(ISD::BR_CC, MVT::i32, Custom);
   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
   setOperationAction(ISD::SETCC, MVT::i32, Custom);
-  setOperationAction(ISD::SETCCE, MVT::i32, Custom);
   setOperationAction(ISD::SELECT, MVT::i32, Expand);
   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
 
   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
   setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
   setOperationAction(ISD::JumpTable, MVT::i32, Custom);
   setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
 
SDValue LanaiTargetLowering::LowerOperation(SDValue Op,
   case ISD::BlockAddress:
     return LowerBlockAddress(Op, DAG);
   case ISD::JumpTable:
     return LowerJumpTable(Op, DAG);
   case ISD::SELECT_CC:
     return LowerSELECT_CC(Op, DAG);
   case ISD::SETCC:
     return LowerSETCC(Op, DAG);
-  case ISD::SETCCE:
-    return LowerSETCCE(Op, DAG);
   case ISD::SHL_PARTS:
     return LowerSHL_PARTS(Op, DAG);
   case ISD::SRL_PARTS:
     return LowerSRL_PARTS(Op, DAG);
   case ISD::VASTART:
     return LowerVASTART(Op, DAG);
   case ISD::DYNAMIC_STACKALLOC:
     return LowerDYNAMIC_STACKALLOC(Op, DAG);
for (unsigned int I = 0; I < sizeof(SignedDigit) / sizeof(SignedDigit[0]);
     if (SignedDigit[I] == 1)
       Res = DAG.getNode(ISD::ADD, DL, VT, Res, Op);
     else if (SignedDigit[I] == -1)
       Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op);
   }
   return Res;
 }
 
-SDValue LanaiTargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
-  SDValue LHS = Op.getOperand(0);
-  SDValue RHS = Op.getOperand(1);
-  SDValue Carry = Op.getOperand(2);
-  SDValue Cond = Op.getOperand(3);
-  SDLoc DL(Op);
-
-  LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
-  SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
-  SDValue Flag = DAG.getNode(LanaiISD::SUBBF, DL, MVT::Glue, LHS, RHS, Carry);
-  return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
-}
-
 SDValue LanaiTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
   SDValue LHS = Op.getOperand(0);
   SDValue RHS = Op.getOperand(1);
   SDValue Cond = Op.getOperand(2);
   SDLoc DL(Op);
 
   LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
   SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);

llvm/trunk/test/CodeGen/Lanai/comparisons_i64.ll

 ; CHECK-NEXT: sne
 define i32 @ne_i64(i64 inreg %x, i64 inreg %y) {
   %a = icmp ne i64 %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: slt_i64:
-; CHECK: sub.f %r7, %r19, %r3
-; CHECK: subb.f %r6, %r18, %r3
-; CHECK-NEXT: slt
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: slt %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: sult %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
 define i32 @slt_i64(i64 inreg %x, i64 inreg %y) {
   %a = icmp slt i64 %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: sle_i64:
-; CHECK: sub.f %r19, %r7, %r3
-; CHECK: subb.f %r18, %r6, %r3
-; CHECK-NEXT: sge %rv
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sle %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: sule %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
 define i32 @sle_i64(i64 inreg %x, i64 inreg %y) {
   %a = icmp sle i64 %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: ult_i64:
-; CHECK: sub.f %r7, %r19, %r3
-; CHECK: subb.f %r6, %r18, %r3
-; CHECK-NEXT: sult %rv
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sult %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: sult %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
 define i32 @ult_i64(i64 inreg %x, i64 inreg %y) {
   %a = icmp ult i64 %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: ule_i64:
-; CHECK: sub.f %r19, %r7, %r3
-; CHECK: subb.f %r18, %r6, %r3
-; CHECK-NEXT: suge %rv
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sule %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: sule %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
 define i32 @ule_i64(i64 inreg %x, i64 inreg %y) {
   %a = icmp ule i64 %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: sgt_i64:
-; CHECK: sub.f %r19, %r7, %r3
-; CHECK: subb.f %r18, %r6, %r3
-; CHECK-NEXT: slt %rv
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sgt %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: sugt %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
 define i32 @sgt_i64(i64 inreg %x, i64 inreg %y) {
   %a = icmp sgt i64 %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: sge_i64:
-; CHECK: sub.f %r7, %r19, %r3
-; CHECK: subb.f %r6, %r18, %r3
-; CHECK-NEXT: sge %rv
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sge %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: suge %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
 define i32 @sge_i64(i64 inreg %x, i64 inreg %y) {
   %a = icmp sge i64 %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: ugt_i64:
-; CHECK: sub.f %r19, %r7, %r3
-; CHECK: subb.f %r18, %r6, %r3
-; CHECK-NEXT: sult %rv
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sugt %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: sugt %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
 define i32 @ugt_i64(i64 inreg %x, i64 inreg %y) {
   %a = icmp ugt i64 %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }
 
 ; CHECK-LABEL: uge_i64:
-; CHECK: sub.f %r7, %r19, %r3
-; CHECK: subb.f %r6, %r18, %r3
-; CHECK-NEXT: suge %rv
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: suge %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: suge %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
 define i32 @uge_i64(i64 inreg %x, i64 inreg %y) {
   %a = icmp uge i64 %x, %y
   %b = zext i1 %a to i32
   ret i32 %b
 }