[SelectionDAG] Refactor code by adding RegsForValue::getRegsAndSizes(). NFCI

[bjope]

Summary

Added a helper method in RegsForValue to get a list with
all the <RegNumber, RegSize> pairs that we want to iterate
over in SelectionDAGBuilder::EmitFuncArgumentDbgValue and
in SelectionDAGBuilder::visitIntrinsicCall.

[vsk]

Thanks! I can't wait until we're able to use C++17 structured bindings in llvm. It'd be really nice to write 'auto [Reg, Size] = ...', or 'auto [Count, VT] = ...'

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h

1057

Maybe just 'Return a list ...'?

[bjope]

Rebased after rL331464

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h

struct RegsForValue {
   void AddInlineAsmOperands(unsigned Kind, bool HasMatching,
                             unsigned MatchingIdx, const SDLoc &dl,
                             SelectionDAG &DAG, std::vector<SDValue> &Ops) const;
 
   /// Check if the total RegCount is greater than one.
   bool occupiesMultipleRegs() const {
     return std::accumulate(RegCount.begin(), RegCount.end(), 0) > 1;
   }
+
+  /// Populate the OutVec with a list of registers and their sizes.
+  SmallVector<std::pair<unsigned, unsigned>, 4> getRegsAndSizes() const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
     for (unsigned i = 0; i != NumRegs; ++i) {
       assert(Reg < Regs.size() && "Mismatch in # registers expected");
       unsigned TheReg = Regs[Reg++];
       Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
     }
   }
 }
 
+SmallVector<std::pair<unsigned, unsigned>, 4>
+RegsForValue::getRegsAndSizes() const {
+  SmallVector<std::pair<unsigned, unsigned>, 4> OutVec;
+  unsigned I = 0;
+  for (auto CountAndVT : zip_first(RegCount, RegVTs)) {
+    unsigned RegCount = std::get<0>(CountAndVT);
+    MVT RegisterVT = std::get<1>(CountAndVT);
+    unsigned RegisterSize = RegisterVT.getSizeInBits();
+    for (unsigned E = I + RegCount; I != E; ++I)
+      OutVec.push_back(std::make_pair(Regs[I], RegisterSize));
+  }
+  return OutVec;
+}
+
 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis *aa,
                                const TargetLibraryInfo *li) {
   AA = aa;
   GFI = gfi;
   LibInfo = li;
   DL = &DAG.getDataLayout();
   Context = DAG.getContext();
   LPadToCallSiteMap.clear();
bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
 
   if (!Op) {
     // Check if ValueMap has reg number.
     DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
     if (VMI != FuncInfo.ValueMap.end()) {
       const auto &TLI = DAG.getTargetLoweringInfo();
       RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), VMI->second,
                        V->getType(), isABIRegCopy(V));
-      unsigned NumRegs =
-          std::accumulate(RFV.RegCount.begin(), RFV.RegCount.end(), 0);
-      if (NumRegs > 1) {
-        unsigned I = 0;
+      if (RFV.occupiesMultipleRegs()) {
         unsigned Offset = 0;
-        auto RegisterVT = RFV.RegVTs.begin();
-        for (auto RegCount : RFV.RegCount) {
-          unsigned RegisterSize = (RegisterVT++)->getSizeInBits();
-          for (unsigned E = I + RegCount; I != E; ++I) {
-            // The vregs are guaranteed to be allocated in sequence.
-            Op = MachineOperand::CreateReg(VMI->second + I, false);
-            auto FragmentExpr = DIExpression::createFragmentExpression(
-                Expr, Offset, RegisterSize);
-            if (!FragmentExpr)
-              continue;
-            FuncInfo.ArgDbgValues.push_back(
-                BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsDbgDeclare,
-                        Op->getReg(), Variable, *FragmentExpr));
-            Offset += RegisterSize;
-          }
+        for (auto RegAndSize : RFV.getRegsAndSizes()) {
+          Op = MachineOperand::CreateReg(RegAndSize.first, false);
+              Expr, Offset, RegAndSize.second);
+          Offset += RegAndSize.second;
         }
         return true;
       }
       Op = MachineOperand::CreateReg(VMI->second, false);
       IsIndirect = IsDbgDeclare;
     }
   }
 
if (isa<PHINode>(V)) {
       auto VMI = FuncInfo.ValueMap.find(V);
       if (VMI != FuncInfo.ValueMap.end()) {
         unsigned Reg = VMI->second;
         // The PHI node may be split up into several MI PHI nodes (in
         // FunctionLoweringInfo::set).
         RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
                          V->getType(), false);
         if (RFV.occupiesMultipleRegs()) {
-          unsigned I = 0;
           unsigned Offset = 0;
-          for (auto CountAndVT : zip_first(RFV.RegCount, RFV.RegVTs)) {
-            unsigned RegCount = std::get<0>(CountAndVT);
-            MVT RegisterVT = std::get<1>(CountAndVT);
-            unsigned RegisterSize = RegisterVT.getSizeInBits();
-            for (unsigned E = I + RegCount; I != E; ++I) {
-              auto FragmentExpr = DIExpression::createFragmentExpression(
-                  Expression, Offset, RegisterSize);
-              if (!FragmentExpr)
-                continue;
-              // The vregs are guaranteed to be allocated in sequence.
-              SDV = DAG.getVRegDbgValue(Variable, *FragmentExpr, Reg + I,
-                                        false, dl, SDNodeOrder);
-              DAG.AddDbgValue(SDV, nullptr, false);
-              Offset += RegisterSize;
-            }
+          for (auto RegAndSize : RFV.getRegsAndSizes()) {
+                Expression, Offset, RegAndSize.second);
+            SDV = DAG.getVRegDbgValue(Variable, *FragmentExpr,
+                                      RegAndSize.first,
+            Offset += RegAndSize.second;
           }
         } else {
           SDV = DAG.getVRegDbgValue(Variable, Expression, Reg, false, dl,
                                     SDNodeOrder);
           DAG.AddDbgValue(SDV, nullptr, false);
         }
         return nullptr;
       }