[Sparc] Fix addressing mode when using 64-bit values in inline assembly

[dcederman]

Summary

If a 64-bit register is used as an operand in inline assembly together with a memory reference, the memory addressing will be wrong. The addressing will be a single reg, instead of reg+reg or reg+imm. This will generate a bad offset value or an exception in printMemOperand().

For example:

long long int val = 5;
long long int mem;
__asm__ volatile ("std %1, %0":"=m"(mem):"r"(val));

becomes:

std %i0, [%i2+589833]

The problem is that SelectInlineAsmMemoryOperand() is never called for the memory references if one of the operands is a 64-bit register. By calling SelectInlineAsmMemoryOperands() in tryInlineAsm() the Sparc version of SelectInlineAsmMemoryOperand() gets called for each memory reference.

A comment above SelectInlineAsmMemoryOperands() says that it should only be called by tblgen. So alternatively one could call SelectCode() on the new Node instead, or copy the content of SelectInlineAsmMemoryOperands() to tryInlineAsm().

[jyknight]

Looks reasonable to me -- SelectInlineAsmMemoryOperands is called in the equivalent generic INLINEASM select code so it makes sense to do so here too. I wonder if the same bug exists on ARM, which has effectively the same code.

[jyknight]

(forgot to click accept)

[dcederman]

Thanks!

In D45761#1073006, @jyknight wrote:

I wonder if the same bug exists on ARM, which has effectively the same code.

The ARM backend does not change addressing mode in its SelectInlineAsmMemoryOperand(), so I do not think it matters if it gets called or not. But I could create a similar patch for ARM.

lib/Target/Sparc/SparcISelDAGToDAG.cpp

for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
     }
   }
 
   if (Glue.getNode())
     AsmNodeOperands.push_back(Glue);
   if (!Changed)
     return false;
 
+  SelectInlineAsmMemoryOperands(AsmNodeOperands, SDLoc(N));
+
   SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
       CurDAG->getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
   New->setNodeId(-1);
   ReplaceNode(N, New.getNode());
   return true;
 }
 
 void SparcDAGToDAGISel::Select(SDNode *N) {

test/CodeGen/SPARC/inlineasm.ll

 
 ; CHECK-LABEL: faddd:
 ; CHECK: faddd  %f0, %f2, %f0
 define double @faddd(double, double) local_unnamed_addr #2 {
 entry:
   %2 = tail call double asm sideeffect "faddd  $1, $2, $0;", "=f,f,e"(double %0, double %1) #7
   ret double %2
 }
+
+; CHECK-LABEL: test_addressing_mode_i64:
+; CHECK: std %l0, [%o0]
+define void @test_addressing_mode_i64(i64* %out) {
+entry:
+  call void asm "std %l0, $0", "=*m,r"(i64* nonnull %out, i64 0)
+  ret void
+}