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[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs
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Authored by craig.topper on Apr 5 2018, 8:09 PM.

Details

Summary

This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency.

Apparently we were inconsistent about whether the store has latency or not thus the test changes.

I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5.

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Repository
rL LLVM

Event Timeline

craig.topper created this revision.Apr 5 2018, 8:09 PM
andreadb accepted this revision.Apr 6 2018, 2:47 AM

Nice cleanup!

LGTM.

lib/Target/X86/X86InstrArithmetic.td
855–856 ↗(On Diff #141270)

It is a shame that we cannot concatenate lists in tablegen. If we had the concept of read sequence (and concatenation), we could have avoided to have to repeat ReadDefault for five times.

924 ↗(On Diff #141270)

Nice catch.

This revision is now accepted and ready to land.Apr 6 2018, 2:47 AM
This revision was automatically updated to reflect the committed changes.