[X86] Introduce cldemote instruction

[GBuella]

Summary

Hint to hardware to move the cache line containing the
address to a more distant level of the cache without
writing back to memory.

[craig.topper]

LGTM

[GBuella]

Rebase

llvm/trunk/include/llvm/IR/IntrinsicsX86.td

let TargetPrefix = "x86" in {
   // Write back and invalidate
   def int_x86_wbinvd : GCCBuiltin<"__builtin_ia32_wbinvd">,
       Intrinsic<[], [], []>;
 
   // Write back no-invalidate
   def int_x86_wbnoinvd : GCCBuiltin<"__builtin_ia32_wbnoinvd">,
       Intrinsic<[], [], []>;
 }
+
+//===----------------------------------------------------------------------===//
+// Cache-line demote
+
+let TargetPrefix = "x86" in {
+  def int_x86_cldemote : GCCBuiltin<"__builtin_ia32_cldemote">,
+      Intrinsic<[], [llvm_ptr_ty], []>;
+}

llvm/trunk/lib/Support/Host.cpp

bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
   Features["shstk"]           = HasLeaf7 && ((ECX >>  7) & 1);
   Features["gfni"]            = HasLeaf7 && ((ECX >>  8) & 1);
   Features["vaes"]            = HasLeaf7 && ((ECX >>  9) & 1) && HasAVXSave;
   Features["vpclmulqdq"]      = HasLeaf7 && ((ECX >> 10) & 1) && HasAVXSave;
   Features["avx512vnni"]      = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
   Features["avx512bitalg"]    = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
   Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
   Features["rdpid"]           = HasLeaf7 && ((ECX >> 22) & 1);
+  Features["cldemote"]        = HasLeaf7 && ((ECX >> 25) & 1);
 
   Features["ibt"] = HasLeaf7 && ((EDX >> 20) & 1);
 
   bool HasLeafD = MaxLevel >= 0xd &&
                   !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
 
   // Only enable XSAVE if OS has enabled support for saving YMM state.
   Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;

llvm/trunk/lib/Target/X86/X86.td

 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
                                       "Support RDSEED instruction">;
 def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
                                        "Support LAHF and SAHF instructions">;
 def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
                                       "Enable MONITORX/MWAITX timer functionality">;
 def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
                                       "Enable Cache Line Zero">;
+def FeatureCLDEMOTE  : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
+                                      "Enable Cache Demote">;
 def FeatureMPX     : SubtargetFeature<"mpx", "HasMPX", "true",
                                       "Support MPX instructions">;
 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
                                      "Use LEA for adjusting the stack pointer">;
 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
                                      "HasSlowDivide32", "true",
                                      "Use 8-bit divide for positive values less than 256">;
 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",

llvm/trunk/lib/Target/X86/X86InstrInfo.td

 def HasRDSEED    : Predicate<"Subtarget->hasRDSEED()">;
 def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">;
 def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">;
 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
 def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">;
 def HasLAHFSAHF  : Predicate<"Subtarget->hasLAHFSAHF()">;
 def HasMWAITX    : Predicate<"Subtarget->hasMWAITX()">;
 def HasCLZERO    : Predicate<"Subtarget->hasCLZERO()">;
+def HasCLDEMOTE  : Predicate<"Subtarget->hasCLDEMOTE()">;
 def FPStackf32   : Predicate<"!Subtarget->hasSSE1()">;
 def FPStackf64   : Predicate<"!Subtarget->hasSSE2()">;
 def HasMPX       : Predicate<"Subtarget->hasMPX()">;
 def HasSHSTK     : Predicate<"Subtarget->hasSHSTK()">;
 def HasIBT       : Predicate<"Subtarget->hasIBT()">;
 def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">;
 def HasCLWB      : Predicate<"Subtarget->hasCLWB()">;
 def HasWBNOINVD  : Predicate<"Subtarget->hasWBNOINVD()">;

 let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
 def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
                    "clflushopt\t$src", [(int_x86_clflushopt addr:$src)]>, PD;
 
 let Predicates = [HasCLWB], SchedRW = [WriteLoad] in
 def CLWB       : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src",
                    [(int_x86_clwb addr:$src)]>, PD;
 
+def CLDEMOTE : I<0x1C, MRM0m, (outs), (ins i8mem:$src), "cldemote\t$src",
+                   [(int_x86_cldemote addr:$src)]>, TB, Requires<[HasCLDEMOTE]>;
+
 //===----------------------------------------------------------------------===//
 // Subsystems.
 //===----------------------------------------------------------------------===//
 
 include "X86InstrArithmetic.td"
 include "X86InstrCMovSetCC.td"
 include "X86InstrExtension.td"
 include "X86InstrControl.td"

llvm/trunk/lib/Target/X86/X86Subtarget.h

protected:
   bool HasLAHFSAHF;
 
   /// Processor has MONITORX/MWAITX instructions.
   bool HasMWAITX;
 
   /// Processor has Cache Line Zero instruction
   bool HasCLZERO;
 
+  /// Processor has Cache Line Demote instruction
+  bool HasCLDEMOTE;
+
   /// Processor has Prefetch with intent to Write instruction
   bool HasPREFETCHWT1;
 
   /// True if SHLD instructions are slow.
   bool IsSHLDSlow;
 
   /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
   //  PMULUDQ.
bool hasSSEPrefetch() const {
     // level OR if we have prfchw, but don't already have a read prefetch from
     // 3dnow.
     return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
   }
   bool hasRDSEED() const { return HasRDSEED; }
   bool hasLAHFSAHF() const { return HasLAHFSAHF; }
   bool hasMWAITX() const { return HasMWAITX; }
   bool hasCLZERO() const { return HasCLZERO; }
+  bool hasCLDEMOTE() const { return HasCLDEMOTE; }
   bool isSHLDSlow() const { return IsSHLDSlow; }
   bool isPMULLDSlow() const { return IsPMULLDSlow; }
   bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
   bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
   int getGatherOverhead() const { return GatherOverhead; }
   int getScatterOverhead() const { return ScatterOverhead; }
   bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
   bool hasCmpxchg16b() const { return HasCmpxchg16b; }

llvm/trunk/lib/Target/X86/X86Subtarget.cpp

void X86Subtarget::initializeEnvironment() {
   HasBITALG = false;
   HasSHA = false;
   HasPREFETCHWT1 = false;
   HasPRFCHW = false;
   HasRDSEED = false;
   HasLAHFSAHF = false;
   HasMWAITX = false;
   HasCLZERO = false;
+  HasCLDEMOTE = false;
   HasMPX = false;
   HasSHSTK = false;
   HasIBT = false;
   HasSGX = false;
   HasCLFLUSHOPT = false;
   HasCLWB = false;
   HasWBNOINVD = false;
   HasRDPID = false;

llvm/trunk/test/CodeGen/X86/cldemote-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-linux -mattr=+cldemote | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i386-pc-linux -mattr=+cldemote | FileCheck %s --check-prefix=X32
+
+define void @test_cldemote(i8* %p) {
+; X64-LABEL: test_cldemote:
+; X64:       # %bb.0: # %entry
+; X64-NEXT:    cldemote (%rdi)
+; X64-NEXT:    retq
+;
+; X32-LABEL: test_cldemote:
+; X32:       # %bb.0: # %entry
+; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    cldemote (%eax)
+; X32-NEXT:    retl
+entry:
+  tail call void @llvm.x86.cldemote(i8* %p)
+  ret void
+}
+
+declare void @llvm.x86.cldemote(i8*)

llvm/trunk/test/MC/Disassembler/X86/x86-32.txt

 # CHECK: ptwritel -559038737(%ebx,%ecx,8)
 0xf3 0x0f 0xae 0xa4 0xcb 0xef 0xbe 0xad 0xde
 
 # CHECK: ptwritel %eax
 0xf3 0x0f 0xae 0xe0
 
 # CHECK: wbnoinvd
 0xf3 0x0f 0x09
+
+# CHECK: cldemote 4(%eax)
+0x0f 0x1c 0x40 0x04
+
+# CHECK: cldemote -559038737(%ebx,%ecx,8)
+0x0f,0x1c,0x84,0xcb,0xef,0xbe,0xad,0xde

llvm/trunk/test/MC/Disassembler/X86/x86-64.txt

 # CHECK: ptwriteq -559038737(%rbx,%rcx,8)
 0xf3 0x48 0x0f 0xae 0xa4 0xcb 0xef 0xbe 0xad 0xde
 
 # CHECK: ptwriteq %rax
 0xf3 0x48 0x0f 0xae 0xe0
 
 # CHECK: wbnoinvd
 0xf3 0x0f 0x09
+
+# CHECK: cldemote 4(%rax)
+0x0f 0x1c 0x40 0x04
+
+# CHECK: cldemote -559038737(%rbx,%rcx,8)
+0x0f,0x1c,0x84,0xcb,0xef,0xbe,0xad,0xde

llvm/trunk/test/MC/X86/x86-32-coverage.s

 // CHECK:  encoding: [0x0f,0x01,0xfc]
           clzero
 
 // CHECK: lock addl %esi, (%edi)
 // INTEL: lock add dword ptr [edi], esi
 // CHECK:  encoding: [0xf0,0x01,0x37]
           lock add %esi, (%edi)
 
+// CHECK: cldemote 4(%eax)
+// CHECK:  encoding: [0x0f,0x1c,0x40,0x04]
+          cldemote 4(%eax)
+
+// CHECK: cldemote 3735928559(%ebx,%ecx,8)
+// CHECK:  encoding: [0x0f,0x1c,0x84,0xcb,0xef,0xbe,0xad,0xde]
+          cldemote 0xdeadbeef(%ebx,%ecx,8)

llvm/trunk/test/MC/X86/x86-64.s

 // CHECK: ptwriteq %rax
 // CHECK:  encoding: [0xf3,0x48,0x0f,0xae,0xe0]
 ptwriteq %rax
 
 // CHECK: wbnoinvd
 // CHECK:  encoding: [0xf3,0x0f,0x09]
 wbnoinvd
 
+// CHECK: cldemote 4(%rax)
+// CHECK:  encoding: [0x0f,0x1c,0x40,0x04]
+cldemote 4(%rax)
+
+// CHECK: cldemote 3735928559(%rbx,%rcx,8)
+// CHECK:  encoding: [0x0f,0x1c,0x84,0xcb,0xef,0xbe,0xad,0xde]
+cldemote 0xdeadbeef(%rbx,%rcx,8)
+
 //  __asm __volatile(
 //    "pushf        \n\t"
 //    "popf       \n\t"
 //    "rep        \n\t"
 //    ".byte  0x0f, 0xa7, 0xd0"
 //  );
 // CHECK: pushfq
 // CHECK-NEXT: popfq