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[X86][Znver1] Remove ReadAfterLd from BSR/BSF in Zen scheduler model
AbandonedPublic

Authored by craig.topper on Mar 23 2018, 11:06 AM.

Reviewers

RKSimon
GGanesh

Summary

These are unary instructions not binary. The only source operand are the 5 memory address pieces which are not ReadAfterLd

Looks like this is no longer necessary after Simon added WriteBitScan

Path

Size

lib/

Target/

X86/

2 lines

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	def ZnWriteALULat3Ld : SchedWriteRes<[ZnAGU, ZnALU]> {			def ZnWriteALULat3Ld : SchedWriteRes<[ZnAGU, ZnALU]> {
	let Latency = 7;			let Latency = 7;
	}			}

	// BSF BSR.			// BSF BSR.
	// r,r.			// r,r.
	def : InstRW<[ZnWriteALULat3], (instregex "BS(R\|F)(16\|32\|64)rr")>;			def : InstRW<[ZnWriteALULat3], (instregex "BS(R\|F)(16\|32\|64)rr")>;
	// r,m.			// r,m.
	def : InstRW<[ZnWriteALULat3Ld, ReadAfterLd], (instregex "BS(R\|F)(16\|32\|64)rm")>;			def : InstRW<[ZnWriteALULat3Ld], (instregex "BS(R\|F)(16\|32\|64)rm")>;

	// BT.			// BT.
	// r,r/i.			// r,r/i.
	def : InstRW<[WriteShift], (instregex "BT(16\|32\|64)r(r\|i8)")>;			def : InstRW<[WriteShift], (instregex "BT(16\|32\|64)r(r\|i8)")>;

	def : InstRW<[WriteShiftLd], (instregex "BT(16\|32\|64)mr")>;			def : InstRW<[WriteShiftLd], (instregex "BT(16\|32\|64)mr")>;
	def : InstRW<[WriteShiftLd], (instregex "BT(16\|32\|64)mi8")>;			def : InstRW<[WriteShiftLd], (instregex "BT(16\|32\|64)mi8")>;

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