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[X86] Use target independent zero_extend/sign_extend nodes for vectors with same number of elements.
AbandonedPublic

Authored by craig.topper on Feb 24 2018, 9:57 PM.

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Reviewers
RKSimon
spatel
Summary

This patch uses ISD::ZERO_EXTEND/SIGN_EXTEND when the number of elements match. I'm still not sure what to do about the cases when the number of elements don't match, but we can't use ZERO/SIGN_EXTEND_VECTOR_INREG either. Maybe we can use ZERO/SIGN_EXTEND_VECTOR_INREG with the vector sizes matched and emit a subreg extract in the isel output to get the xmm register as an input?

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craig.topper created this revision.Feb 24 2018, 9:57 PM

We seem to be doing a LOT of work to adhere to the limitations of ISD::*_EXTEND_VECTOR_INREG - would it be too drastic to change the rules to allow the input vector to be smaller in size, maybe require it to be a legal type?

Most of the code related to zero/sign_extend_vector_inreg is in the type legalizer. DAG combiner doesn't really do anything that cares about the rules. Not sure what the impact to other targets would be if we start messing with the legalization. Maybe we can keep type legalizing it the same way, but relax the rule. Then X86 would need to custom lower it to split?

I looked into just using extend_vector_inreg with 256 or 512 bit input types and then force an EXTRACT_SUBREG in the isel output patterns. But that failed when I couldn't represent (v64i32 (zero_extend_vector_inreg (v64i8))) on a non-BWI target since v64i8 isn't legal.

@craig.topper What do you want to do with this patch? I'm happy to accept it more or less as it is - I do think we're putting off the inevitable about just changing everything to an improved version of *_EXTEND_VECTOR_INREG but its unlikely to get sorted out before the next branch.

I did play around with loosening the extend_vector_inreg restrctions a while back. Most of the changes I found are in the legalizers as that's where most of the rules matter.

I also tried just using extend_vector_inreg as is and emitting an extract_subvector during isel. But I couldn't use extend_vector_inreg of v64i8->v8i64 for vpmovbw %xmm, %zmm with +avx512,-avx512bw becuase the v64i8 type isn't legal.

This patch has been sitting for a while so it probably needs to be rebased.

Abandon this for D54346 instead ?

craig.topper abandoned this revision.Nov 10 2018, 10:00 AM