[mips] Support 'z' inline asm constraint

[atanasyan]

Summary

The 'z' constraint is used to deal with the floating-point condition code register. Using this constraint the following short, although useless piece of code

float a = 1.0, b = 2.0;
int res;
__asm__ __volatile__(
       "c.eq.s %1,%2"
   : "+z" (res) : "f" (a), "f" (a) : );

translated to this series of assembler commands

ctc1    $1, $fcc0
c.eq.s  $f2, $f0
cfc1    $1, $fcc0

So we can read/write the floating-point condition code register from/to a variable.

This patch adds support for the 'z' constraint on LLVM level only. One more fix is required to support the constraint in the Clang.

[sdardis]

Reading and writing to the fcc register set directly is somewhat cumbersome, in that we have to perform mask and shift operations or bit insertions. If that constraint can allocate any fcc register it will probably require some sort of pseudo instruction to generate the correct sequence.

lib/Target/Mips/MipsISelLowering.cpp

3655

Document the constraint in the above comment.

lib/Target/Mips/MipsSEInstrInfo.cpp

106–107

This is insufficient to read a particular fcc register. cfc1 and ctc1 operate on the float point control registers, not the fcc register set. The $fcsr register or the $fccr register can used to read/write the entire set of $fcc registers (i'd suggest the $fccr / $25). You then have to mask off the non-relevant bits.

Additionally, it may require a pseudo instruction which uses a scratch GPR and is expanded post register allocation to make the correct sequence if any other register that $fcc0 is used.

test/CodeGen/Mips/inlineasm_constraint_z.ll

1

This need -verify-machineinstrs, also use -mtriple=mips-unknown-linux-gnu and use the update_llc_checks script.

[atanasyan]

I discussed the 'z' constraint with Matthew Fortune and we reached a conclusion that it does not make a sense to support this constraint in LLVM. Probably the 'z' constraint should be marked as "internal" in the gcc code.

Anyway, thanks for review.

lib/Target/Mips/MipsISelLowering.cpp

if (Constraint.size() == 1) {
     switch (Constraint[0]) {
       default : break;
       case 'd':
       case 'y':
       case 'f':
       case 'c':
       case 'l':
       case 'x':
+      case 'z':
         return C_RegisterClass;
       case 'R':
         return C_Memory;
     }
   }
 
   if (Constraint == "ZC")
     return C_Memory;
if (Subtarget.hasMSA() && type->isVectorTy() &&
         cast<VectorType>(type)->getBitWidth() == 128)
       weight = CW_Register;
     else if (type->isFloatTy())
       weight = CW_Register;
     break;
   case 'c': // $25 for indirect jumps
   case 'l': // lo register
   case 'x': // hilo register pair
+  case 'z': // FCSR
     if (type->isIntegerTy())
       weight = CW_SpecificReg;
     break;
   case 'I': // signed 16 bit immediate
   case 'J': // integer zero
   case 'K': // unsigned 16 bit immediate
   case 'L': // signed 32 bit immediate where lower 16 bits are 0
   case 'N': // immediate in the range of -65535 to -1 (inclusive)
case 'l': // use the `lo` register to store values
       if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
         return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
       return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
     case 'x': // use the concatenated `hi` and `lo` registers
               // to store doubleword values
       // Fixme: Not triggering the use of both hi and low
       // This will generate an error message
       return std::make_pair(0U, nullptr);
+    case 'z': // Use a floating-point condition code register.
+      if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
+        return std::make_pair((unsigned)Mips::FCC0, &Mips::FCCRegClass);
+      // This will generate an error message
+      return std::make_pair(0U, nullptr);
     }
   }
 
   std::pair<unsigned, const TargetRegisterClass *> R;
   R = parseRegForInlineAsmConstraint(Constraint, VT);
 
   if (R.second)
     return R;

lib/Target/Mips/MipsSEInstrInfo.cpp

else if (Mips::HI32RegClass.contains(SrcReg)) {
       SrcReg = 0;
     } else if (Mips::LO32RegClass.contains(SrcReg)) {
       Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
       SrcReg = 0;
     } else if (Mips::HI32DSPRegClass.contains(SrcReg))
       Opc = Mips::MFHI_DSP;
     else if (Mips::LO32DSPRegClass.contains(SrcReg))
       Opc = Mips::MFLO_DSP;
+    else if (Mips::FCCRegClass.contains(SrcReg))
+      Opc = Mips::CFC1;
     else if (Mips::DSPCCRegClass.contains(SrcReg)) {
       BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
         .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
       return;
     }
     else if (Mips::MSACtrlRegClass.contains(SrcReg))
       Opc = Mips::CFCMSA;
   }
   else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
     if (Mips::CCRRegClass.contains(DestReg))
       Opc = Mips::CTC1;
     else if (Mips::FGR32RegClass.contains(DestReg))
       Opc = Mips::MTC1;
     else if (Mips::HI32RegClass.contains(DestReg))
       Opc = Mips::MTHI, DestReg = 0;
     else if (Mips::LO32RegClass.contains(DestReg))
       Opc = Mips::MTLO, DestReg = 0;
     else if (Mips::HI32DSPRegClass.contains(DestReg))
       Opc = Mips::MTHI_DSP;
     else if (Mips::LO32DSPRegClass.contains(DestReg))
       Opc = Mips::MTLO_DSP;
+    else if (Mips::FCCRegClass.contains(DestReg))
+      Opc = Mips::CTC1;
     else if (Mips::DSPCCRegClass.contains(DestReg)) {
       BuildMI(MBB, I, DL, get(Mips::WRDSP))
         .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
         .addReg(DestReg, RegState::ImplicitDefine);
       return;
     } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
       BuildMI(MBB, I, DL, get(Mips::CTCMSA))
           .addReg(DestReg)

test/CodeGen/Mips/inlineasm_constraint_z.ll

+; RUN: llc -march=mips < %s | FileCheck %s
+
+define void @foo() {
+entry:
+; CHECK-LABEL: foo:
+
+  %a = alloca i32, align 4
+  %0 = load i32, i32* %a, align 4
+
+  %1 = call i32 asm sideeffect "c.eq.s $1,$2", "=z,f,f,0,~{$1}"(float 1.0, float 2.0, i32 %0)
+; CHECK: ctc1    $[[R:[0-9]+]], $fcc0
+; CHECK: c.eq.s  $f0, $f1
+; CHECK: cfc1    $[[R]], $fcc0
+
+  store i32 %1, i32* %a, align 4
+  ret void
+}