[mips] Initial implementation of abicalls.

[matheusalmeida]

I haven't checked what other strange things GCC does with -m[no-]abicalls so I'm calling this an initial implementation. The Linux Kernel is one example of a piece of software built with -mno-abicalls.

[tomatabacu]

Commandeered to finish off the patch and make it ready for commit.

[tomatabacu]

Rebased.

[dsanders]

LGTM with a nit.

We are still a long way from having proper -mno-abicalls support at this point but it's definitely a start.

lib/Target/Mips/MipsSubtarget.h

60

Is the 'bit' part of the name intentional? It doesn't look like it refers to any bit/bits.

[tomatabacu]

lib/Target/Mips/MipsSubtarget.h

60

I'm not sure. That's how Matheus named it, so I left it like that.

[dsanders]

lib/Target/Mips/MipsSubtarget.h

60

In that case I'm going to drop the 'bit' suffix before I commit. Thanks.

[dsanders]

Committed in r215194.

So far you've mostly been finishing of Matheus's patches but I think you've pretty much got the hang of necessary submission quality, etc so I think you should ask Chris Lattner for commit access. You'll still be subject to pre-commit reviews but you'll be able to commit your own work once you've got a 'LGTM'.

lib/Target/Mips/Mips.td

 include "MipsCallingConv.td"
 
 def MipsInstrInfo : InstrInfo;
 
 //===----------------------------------------------------------------------===//
 // Mips Subtarget features                                                    //
 //===----------------------------------------------------------------------===//
 
+def FeatureABICalls    : SubtargetFeature<"abicalls", "IsABICallsbit", "true",
+                                "SVR4-style position-independent code.">;
 def FeatureGP64Bit     : SubtargetFeature<"gp64", "IsGP64bit", "true",
                                 "General Purpose Registers are 64-bit wide.">;
 def FeatureFP64Bit     : SubtargetFeature<"fp64", "IsFP64bit", "true",
                                 "Support 64-bit FP registers.">;
 def FeatureNaN2008     : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
                                 "IEEE 754-2008 NaN encoding.">;
 def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
                                 "true", "Only supports single precision float">;

lib/Target/Mips/MipsAsmPrinter.cpp

 void MipsAsmPrinter::
 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
                 const char *Modifier) {
   const MachineOperand &MO = MI->getOperand(opNum);
   O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
 }
 
 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
-  // TODO: Need to add -mabicalls and -mno-abicalls flags.
-  // Currently we assume that -mabicalls is the default.
-  bool IsABICalls = true;
+  bool IsABICalls = Subtarget->isABICalls();
   if (IsABICalls) {
     getTargetStreamer().emitDirectiveAbiCalls();
     Reloc::Model RM = Subtarget->getRelocationModel();
     // FIXME: This condition should be a lot more complicated that it is here.
     //        Ideally it should test for properties of the ABI and not the ABI
     //        itself.
     //        For the moment, I'm only correcting enough to make MIPS-IV work.
     if (RM == Reloc::Static && !Subtarget->isABI_N64())

lib/Target/Mips/MipsRegisterInfo.cpp

if (Subtarget.isTargetNaCl()) {
     Reserved.set(Mips::T6);   // Reserved for control flow mask.
     Reserved.set(Mips::T7);   // Reserved for memory access mask.
     Reserved.set(Mips::T8);   // Reserved for thread pointer.
   }
 
   for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
     Reserved.set(ReservedGPR64[I]);
 
+  // For mno-abicalls, GP is a program invariant!
+  if (!Subtarget.isABICalls()) {
+    Reserved.set(Mips::GP);
+    Reserved.set(Mips::GP_64);
+  }
+
   if (Subtarget.isFP64bit()) {
     // Reserve all registers in AFGR64.
     for (RegIter Reg = Mips::AFGR64RegClass.begin(),
          EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
       Reserved.set(*Reg);
   } else {
     // Reserve all registers in FGR64.
     for (RegIter Reg = Mips::FGR64RegClass.begin(),

lib/Target/Mips/MipsSubtarget.h

protected:
   // IsLittle - The target is Little Endian
   bool IsLittle;
 
   // IsSingleFloat - The target only supports single precision float
   // point operations. This enable the target to use all 32 32-bit
   // floating point registers instead of only using even ones.
   bool IsSingleFloat;
 
+  // IsABICallsbit - SVR4-style position-independent code.
+  bool IsABICallsbit;
+
   // IsFP64bit - The target processor has 64-bit floating point registers.
   bool IsFP64bit;
 
   // IsNan2008 - IEEE 754-2008 NaN encoding.
   bool IsNaN2008bit;
 
   // IsFP64bit - General-purpose registers are 64 bits wide
   bool IsGP64bit;
public:
   bool hasMips64r2() const {
     return MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6;
   }
   bool hasMips64r6() const { return MipsArchVersion == Mips64r6; }
 
   bool hasCnMips() const { return HasCnMips; }
 
   bool isLittle() const { return IsLittle; }
+  bool isABICalls() const { return IsABICallsbit; }
   bool isFP64bit() const { return IsFP64bit; }
   bool isNaN2008() const { return IsNaN2008bit; }
   bool isNotFP64bit() const { return !IsFP64bit; }
   bool isGP64bit() const { return IsGP64bit; }
   bool isGP32bit() const { return !IsGP64bit; }
   bool isSingleFloat() const { return IsSingleFloat; }
   bool isNotSingleFloat() const { return !IsSingleFloat; }
   bool hasVFPU() const { return HasVFPU; }

lib/Target/Mips/MipsSubtarget.cpp

 
 void MipsSubtarget::anchor() { }
 
 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
                              const std::string &FS, bool little,
                              Reloc::Model _RM, MipsTargetMachine *_TM)
     : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
       MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
-      IsFP64bit(false), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false),
-      HasCnMips(false), IsLinux(true), HasMips3_32(false), HasMips3_32r2(false),
-      HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
-      InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
-      InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
-      AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
-      RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT) {
+      IsABICallsbit(true), IsFP64bit(false), IsNaN2008bit(false),
+      IsGP64bit(false), HasVFPU(false), HasCnMips(false), IsLinux(true),
+      HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
+      HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
+      InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
+      HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
+      HasMSA(false), RM(_RM), OverrideMode(NoOverride), TM(_TM),
+      TargetTriple(TT) {
   std::string CPUName = CPU;
   CPUName = selectMipsCPU(TT, CPUName);
 
   // Parse features string.
   ParseSubtargetFeatures(CPUName, FS);
 
   if (InMips16Mode && !TM->Options.UseSoftFloat) {
     // Hard float for mips16 means essentially to compile as soft float